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61. 发明申请

US20060026548A1 Method, system and program product for providing a configuration specification language supporting selective presentation of configuration entities 有权
标题翻译：用于提供支持配置实体的选择性呈现的配置规范语言的方法，系统和程序产品
公开(公告)号：US20060026548A1
公开(公告)日：2006-02-02
申请号：US10902595
申请日：2004-07-29
申请人： Wolfgang Roesner , Derek Williams
发明人： Wolfgang Roesner , Derek Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains a latch having a respective plurality of different possible latch values. With one or more statements in one or more files, a configuration entity is associated with the latch. The configuration entity has a plurality of different settings and each setting reflects which of the plurality of different possible values is loaded in the associated latch. A controlling value set for at least one instance of the configuration entity is also defined in one or more files. The controlling value set indicates at least one controlling value for which presentation of a current setting of the configuration entity instance is restricted. Thereafter, in response to a request to present at least a partial state of the digital system, a current setting of the configuration entity instance is excluded from presentation by reference to a configuration database indicating the controlling value set.
摘要翻译：在至少一个硬件定义语言（HDL）文件中，指定包含数字系统的功能部分的至少一个设计实体。设计实体逻辑地包含具有相应多个不同可能锁存值的锁存器。在一个或多个文件中使用一个或多个语句，配置实体与锁存器相关联。配置实体具有多个不同的设置，并且每个设置反映多个不同的可能值中的哪一个加载到相关联的锁存器中。对于配置实体的至少一个实例设置的控制值也被定义在一个或多个文件中。控制值集合指示限制配置实体的当前设置的呈现的至少一个控制值。此后，响应于呈现数字系统的至少部分状态的请求，通过参考指示控制值集合的配置数据库将配置实体实例的当前设置排除在呈现之外。

62. 发明申请

US20060022275A1 Planar dual-gate transistor and method for fabricating a planar dual-gate transistor 审中-公开
标题翻译：平面双栅晶体管和制造平面双栅晶体管的方法
公开(公告)号：US20060022275A1
公开(公告)日：2006-02-02
申请号：US11177235
申请日：2005-07-07
申请人： Gurkan llicali , Richard Luyken , Wolfgang Roesner
发明人： Gurkan llicali , Richard Luyken , Wolfgang Roesner
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66772 , H01L29/66628 , H01L29/78618 , H01L29/78648
摘要： A method for fabricating a double-gate transistor including defining an active area on an SOI substrate, forming a first gate region on the SOI substrate, forming source/drain regions made of silicon-germanium in the active area, forming a channel region from the silicon layer of the SOI substrate, forming a layer having a planar surface above the SOI substrate, the source/drain regions, and the first gate region, bonding a second wafer to the planar surface, and forming a second gate region opposite the first gate region.
摘要翻译：一种用于制造双栅极晶体管的方法，包括在SOI衬底上限定有源区，在SOI衬底上形成第一栅极区，在有源区中形成由硅 - 锗制成的源极/漏极区，从而形成来自硅层，形成在SOI衬底上方具有平坦表面的层，源极/漏极区和第一栅极区，将第二晶片接合到平坦表面，以及形成与第一栅极相对的第二栅极区地区。

63. 发明授权

US06993729B2 Method, system and program product for specifying a dial group for a digital system described by a hardware description language (HDL) model 失效
标题翻译：用于指定由硬件描述语言（HDL）模型描述的数字系统的拨号组的方法，系统和程序产品
公开(公告)号：US06993729B2
公开(公告)日：2006-01-31
申请号：US10425070
申请日：2003-04-28
申请人： Bradley Nelson , Wolfgang Roesner , Hugh Shen , Derek Edward Williams
发明人： Bradley Nelson , Wolfgang Roesner , Hugh Shen , Derek Edward Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5045
摘要： A statement in at least one hardware definition language (HDL) file specifies a plurality of design entities representing a functional portion of a digital system. The plurality of design entities have an associated plurality of configuration latches each having a plurality of different possible latch values, where different sets of latch values for the plurality of configuration latches correspond to different configurations of the functional portion of the digital system. With a statement in the at least one HDL file, a Dial group entity is associated with one of the plurality of design entities. The Dial group entity has a Dial list listing a plurality of Dial entities whose settings collectively control which set of latch values is loaded into the plurality of configuration latches. Membership in the Dial group constrains all instances of the plurality of Dial entities belonging to a particular instance of the Dial group to be set as a group.
摘要翻译：至少一种硬件定义语言（HDL）文件中的语句指定表示数字系统的功能部分的多个设计实体。多个设计实体具有相关联的多个配置锁存器，每个配置锁存器具有多个不同的可能的锁存值，其中用于多个配置锁存器的不同的锁存值集合对应于数字系统的功能部分的不同配置。通过至少一个HDL文件中的语句，Dial组实体与多个设计实体之一相关联。拨号组实体具有列出多个拨号实体的拨号列表，其多个拨号实体的设置共同控制哪个锁存值集合被加载到多个配置锁存器中。 Dial组中的成员资格限制属于Dial组的特定实例的多个Dial实体的所有实例被设置为一组。

64. 发明申请

US20060015314A1 Methods, systems and program products for annotating system traces with control program information and presenting annotated system traces 审中-公开
标题翻译：方法，系统和程序产品，用于通过控制程序信息注释系统跟踪并显示注释的系统跟踪
公开(公告)号：US20060015314A1
公开(公告)日：2006-01-19
申请号：US10880730
申请日：2004-06-30
申请人： Wolfgang Roesner , Derek Williams
发明人： Wolfgang Roesner , Derek Williams
IPC分类号： G06F9/45
CPC分类号： G06F11/3664 , G06F11/3636
摘要： The signal state that a signal of interest within a system under test has during each of a plurality of cycles of operation of the system under test is stored in a trace file. In association with the signal state, information regarding a requested access to the signal state by a control program during a particular cycle among the plurality of cycles is also stored. From the trace files a presentation is generated that presents, for at least a signal of interest within the system under test, a plurality of signal state indications, each indicating a respective state that the signal had during a one of a plurality of cycles of operation of the system under test. The presentation also indicates, in a graphically distinctive manner, at least one cycle of operation during which a control program requested access to a state of the signal, so that the influence of the control program on the state of the system under test is visually apparent.
摘要翻译：被测系统中感兴趣的信号在被测系统的多个操作周期中的每一个期间的信号状态被存储在跟踪文件中。与信号状态相关联，还存储关于在多个周期中的特定周期期间由控制程序请求的访问信号状态的信息。从跟踪文件中产生一个演示文稿，对于至少在被测系统内感兴趣的信号，呈现多个信号状态指示，每个信号状态指示各自表示信号在多个操作周期之一中具有的状态的被测系统。演示文稿还以图形上独特的方式指示至少一个操作周期，在该周期期间控制程序请求访问信号的状态，使得控制程序对被测系统的状态的影响在视觉上是明显的。

65. 发明授权

US06934885B2 Fail thresholding in a batch simulation farm network 失效
标题翻译：批处理模拟农场网络中的失败阈值
公开(公告)号：US06934885B2
公开(公告)日：2005-08-23
申请号：US09997767
申请日：2001-11-30
申请人： Carol Ivash Gabele , Wolfgang Roesner , Derek Edward Williams
发明人： Carol Ivash Gabele , Wolfgang Roesner , Derek Edward Williams
IPC分类号： G01R31/3183 , G06F11/00 , G06F17/50 , H02H3/05
CPC分类号： G06F17/5022 , G01R31/318357
摘要： A method and system for tracking frequently occurring fail events that are detected during testcase simulation of a simulation model within a batch simulation farm in which testcases are executed within respect to a simulation model on one or more simulation clients. In accordance with the method of the present invention, the instrumentation server receives fail event packets from one or more simulation clients. The fail event packets contains an aggregate of detected occurrences of a specified fail event. The instrumentation server monitors the rate of occurrence of the specified fail event from received fail event packets to detect an excess rate of occurrence of the specified fail event.
摘要翻译：一种用于跟踪频繁出现的故障事件的方法和系统，其在批处理模拟场内的仿真模型的测试模拟期间检测到，其中在一个或多个仿真客户端上相对于仿真模型执行测试用例。根据本发明的方法，仪器服务器从一个或多个仿真客户端接收故障事件分组。故障事件数据包包含检测到的指定故障事件的出现次数的聚合。仪器服务器监视从接收的故障事件数据包指定的故障事件的发生率，以检测指定的失败事件的超出发生速率。

66. 发明申请

US20050149893A1 Method, system and program product providing a configuration specification language having split latch support 有权
标题翻译：提供具有分离锁存器支持的配置规范语言的方法，系统和程序产品
公开(公告)号：US20050149893A1
公开(公告)日：2005-07-07
申请号：US10749581
申请日：2003-12-31
申请人： Wolfgang Roesner , Derek Williams
发明人： Wolfgang Roesner , Derek Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Methods, data processing systems, and program products supporting multi-cycle simulation are disclosed. According to one method, a configuration database including at least one data structure representing an instance of a Dial entity is received. The instance of the Dial entity has at least an input, an output, and at least one associated latch within a digital design. A value of the output of the instance of the Dial entity controls a value stored within the associated latch. A control file is also received. The control file indicates that at least one associated latch data structure is to be inserted within the configuration database to represent the latch during multi-cycle simulation. In response to receipt of the configuration database and the control file, the configuration database is processed with reference to the control file to insert within the configuration database at least one latch data structure and to associate, within the configuration database, the at least one latch data structure with the instance of the Dial entity.
摘要翻译：公开了支持多循环模拟的方法，数据处理系统和程序产品。根据一种方法，接收包括表示Dial实体的实例的至少一个数据结构的配置数据库。 Dial实体的实例在数字设计中至少具有输入，输出和至少一个相关联的锁存器。 Dial实例的实例的输出值控制存储在相关联的锁存器内的值。还收到一个控制文件。控制文件指示在多循环模拟期间，至少一个相关联的锁存数据结构将被插入配置数据库中以表示锁存器。响应于接收到配置数据库和控制文件，参考控制文件来处理配置数据库，以在配置数据库内插入至少一个锁存数据结构，并且在配置数据库内将至少一个锁存器数据结构与Dial实体的实例。

67. 发明申请

US20050149309A1 Method, system and program product supporting user tracing in a simulator 失效
标题翻译：在模拟器中支持用户跟踪的方法，系统和程序产品
公开(公告)号：US20050149309A1
公开(公告)日：2005-07-07
申请号：US10750590
申请日：2003-12-31
申请人： Bradley Nelson , Wolfgang Roesner , Derek Williams
发明人： Bradley Nelson , Wolfgang Roesner , Derek Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： According to a method of specifying a trace array for simulation of a digital design, one or more entities within a simulation model are specified with one or more statements in one or more hardware description language (HDL) files. In addition, a trace array for storing data generated through simulation of the simulation model is specified in one or more statements in the one or more HDL files. The HDL files may subsequently be processed to create a simulation model containing at least one design entity and a trace array within the design entity for storing trace data regarding specified signals of interest.
摘要翻译：根据指定用于数字设计的仿真的跟踪阵列的方法，模拟模型中的一个或多个实体用一个或多个硬件描述语言（HDL）文件中的一个或多个语句来指定。另外，在一个或多个HDL文件中的一个或多个语句中指定用于存储通过模拟仿真模型生成的数据的跟踪数组。随后可以处理HDL文件以创建包含设计实体内的至少一个设计实体和跟踪阵列的模拟模型，用于存储关于所关心的指定信号的跟踪数据。

68. 发明授权

US06826732B2 Method, system and program product for utilizing a configuration database to configure a hardware digital system 有权
标题翻译：用于利用配置数据库配置硬件数字系统的方法，系统和程序产品
公开(公告)号：US06826732B2
公开(公告)日：2004-11-30
申请号：US10425075
申请日：2003-04-28
申请人： Bryan Ronald Hunt , Wolfgang Roesner , Derek Edward Williams
发明人： Bryan Ronald Hunt , Wolfgang Roesner , Derek Edward Williams
IPC分类号： G06F1750
CPC分类号： G06F17/5022 , G06F17/5045
摘要： A configuration database associated with a hardware system stores at least one data structure defining a Dial instance and a mapping between each of a plurality of possible input values of the Dial instance and a respective one of a corresponding plurality of output values, where the plurality of output values controls which of a plurality of different possible latch values is placed in a hardware latch to configure the hardware system. The configuration database further indicates an association between the Dial instance and the hardware latch. In response to receipt of a request specifying an input value for the Dial instance, the configuration database is accessed to determine an output value for the Dial instance based upon the mapping. In addition, a latch value is obtained based upon the output value and the association. The latch value is then provided to the hardware system to set the hardware latch to the desired latch value.
摘要翻译：与硬件系统相关联的配置数据库存储定义Dial实例的至少一个数据结构以及Dial实例的多个可能的输入值中的每一个与相应的多个输出值中的相应的一个之间的映射，其中多个输出值控制多个不同可能的锁存值中的哪一个被放置在硬件锁存器中以配置硬件系统。配置数据库还指示Dial实例和硬件锁存器之间的关联。响应于接收到指定Dial实例的输入值的请求，访问配置数据库以基于映射来确定Dial实例的输出值。此外，基于输出值和关联来获得锁存值。然后将锁存值提供给硬件系统，以将硬件锁存器设置为所需的锁存值。

69. 发明授权

US06763505B2 Apparatus and method for automated use of phase abstraction for enhanced verification of circuit designs 有权
标题翻译：自动使用相位抽象以增强电路设计验证的装置和方法
公开(公告)号：US06763505B2
公开(公告)日：2004-07-13
申请号：US10116607
申请日：2002-04-04
申请人： Jason Raymond Baumgartner , Robert Lowell Kanzelman , Wolfgang Roesner
发明人： Jason Raymond Baumgartner , Robert Lowell Kanzelman , Wolfgang Roesner
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： An apparatus and method for automated use of phase abstraction for enhanced verification of circuit designs is provided. With the apparatus and method, latches are “colored,” i.e. classified into different types, based on information obtained from a clock tree of the circuit design. Clock tree primitives contain sufficient information to taxonomize the clocks into their respective phases and identify which latches are gated latches. In coloring the latches, gated latches are replaced in the circuit design with a free running clock, a multiplexor, and a sequence of L1 to Ln latches to provide a feedback path via the data path. This allows the gated latch to be phase abstracted without losing the “gated” functionality of the gated latch in the resulting trace. Once the latches are colored in this way, phase abstraction is performed on the colored circuit design. The phase abstracted netlist is then subjected to verification and a trace is produced. The coloring information of the original circuit, plus information as to the exact nature of the phase abstraction performed, is then used to transform the phase abstracted trace to one which resembles a trace of the circuit without phase abstraction.
摘要翻译：提供了一种用于自动使用相位抽象以用于电路设计的增强验证的装置和方法。利用该装置和方法，锁存器是“彩色的”，即根据从电路设计的时钟树获得的信息被分类成不同类型。时钟树原语包含足够的信息，将时钟分类到各自的相位，并确定哪些锁存器是门控锁存器。在对锁存器进行着色时，门控锁存器在电路设计中被替换为具有自由运行时钟，多路复用器和L1到Ln锁存器的序列，以通过数据路径提供反馈路径。这允许门控锁存器被相位抽取，而不会损失所得到的跟踪中门控锁存器的“选通”功能。一旦锁存器以这种方式着色，相位抽象就在彩色电路设计上执行。然后对相抽象网表进行验证，并生成跟踪。原始电路的着色信息，以及执行相位抽象的确切性质的信息，然后用于将相位抽象曲线转换为类似于没有相位抽象的电路轨迹。

70. 发明授权

US06740910B2 Field-effect transistor, circuit configuration and method of fabricating a field-effect transistor 失效
标题翻译：场效应晶体管，电路结构和制造场效晶体管的方法
公开(公告)号：US06740910B2
公开(公告)日：2004-05-25
申请号：US10352830
申请日：2003-01-28
申请人： Wolfgang Roesner , Richard Johannes Luyken , Johannes Kretz
发明人： Wolfgang Roesner , Richard Johannes Luyken , Johannes Kretz
IPC分类号： H01L2976
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/66439 , H01L29/78642 , H01L51/0048 , H01L51/0052 , H01L51/0512 , Y10S977/938
摘要： The gate region of a field effect transistor comprises at least one through hole wherein a nanoelement is provided which is electrically coupled to the source and the drain. The nanoelement may have the conductance thereof controlled by means of the gate, such that the nanoelement forms a channel region of the field effect transistor.
摘要翻译：场效应晶体管的栅极区域包括至少一个通孔，其中提供了与源极和漏极电耦合的纳米元件。纳米元件可以通过栅极控制其电导，使得纳米元件形成场效应晶体管的沟道区。

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