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61. 发明授权

US4962064A Method of planarization of topologies in integrated circuit structures 失效
标题翻译：集成电路结构拓扑的平面化方法
公开(公告)号：US4962064A
公开(公告)日：1990-10-09
申请号：US193478
申请日：1988-05-12
申请人： Jacob D. Haskell , Craig S. Sander , Steven C. Avanzino , Subhash Gupta
发明人： Jacob D. Haskell , Craig S. Sander , Steven C. Avanzino , Subhash Gupta
IPC分类号： H01L21/302 , H01L21/304 , H01L21/3065 , H01L21/31 , H01L21/3105 , H01L21/316 , H01L21/321 , H01L21/76 , H01L21/762
CPC分类号： H01L21/3212 , H01L21/31056 , H01L21/76229 , Y10S148/051 , Y10S438/959
摘要： A method is disclosed for making a highly planarized integrated circuit structure having deposited oxide portions planarized to the level of adjacent portions of the integrated circuit structure which comprises: deposition, over an integrated circuit structure having first portions at a height higher than the remainder of the integrated circuit structure, a conformal oxide layer; depositing a layer of a planarizing material such as polysilicon over the conformal oxide layer; polishing the structure a first time to expose the highest portions of the underlying conformal oxide layer; etching the structure a first time with an etchant system capable of removing the conformal oxide preferentially to the planarizing material; further polishing the structure a second time to remove planarizing material left from the first etching step; and then optionally etching the remainder of the structure to remove any remaining planarizing material and the remaining conformal oxide over the raised portions of the underlying integrated circuit structure to provide the desired highly planarized structure.

62. 发明申请

US20050090039A1 Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding 有权
公开(公告)号：US20050090039A1
公开(公告)日：2005-04-28
申请号：US10988692
申请日：2004-11-15
申请人： Simon Chooi , Yakub Aliyu , Mei Zhou , John Sudijono , Subhash Gupta , Sudipto Roy , Paul Ho , Yi Xu
发明人： Simon Chooi , Yakub Aliyu , Mei Zhou , John Sudijono , Subhash Gupta , Sudipto Roy , Paul Ho , Yi Xu
IPC分类号： H01L21/44 , H01L21/50 , H01L21/60 , H01L23/48 , H01L23/485 , H01L23/52 , H01L29/40
CPC分类号： H01L24/13 , H01L24/11 , H01L24/81 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05568 , H01L2224/1147 , H01L2224/1308 , H01L2224/13083 , H01L2224/13147 , H01L2224/1319 , H01L2224/1329 , H01L2224/133 , H01L2224/81801 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/15747 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
摘要： A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.

63. 发明授权

US06813796B2 Apparatus and methods to clean copper contamination on wafer edge 失效
标题翻译：清洁晶圆边缘铜污染的设备和方法
公开(公告)号：US06813796B2
公开(公告)日：2004-11-09
申请号：US10357137
申请日：2003-02-03
申请人： Sudipto Ranendra Roy , Subhash Gupta , Simon Chooi , Xu Yi , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono , Paul Kwok Keung Ho
发明人： Sudipto Ranendra Roy , Subhash Gupta , Simon Chooi , Xu Yi , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono , Paul Kwok Keung Ho
IPC分类号： B08B700
CPC分类号： B08B1/04 , B08B3/04
摘要： A new apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface. After contaminants have been removed in this manner from the surface, the surface can be further cleaned by applying DI water.
摘要翻译：提供了可用于清洁半导体衬底的外边缘的新设备。在本发明的第一实施例中，刷子安装在基板周围的基板的表面上，化学品通过其上安装有清洁刷的中空芯被供给到被清洁的表面。待清洁的表面以相对高的速度旋转，从而使沉积在该表面（由刷子）上的化学物质残留在表面的边缘。在本发明的第二实施例中，多孔辊安装在化学容器和待清洁的表面之间，待清洁的表面以相对较高的速度旋转。因此，由界面多孔辊沉积在待清洗的表面上的化学物质保留在该表面的边缘，从而引起表面边缘的最佳清洁作用。污染物以这种方式从表面除去后，可以通过加入去离子水进一步清洁表面。

64. 发明授权

US06720204B2 Method of using hydrogen plasma to pre-clean copper surfaces during Cu/Cu or Cu/metal bonding 有权
标题翻译：在Cu / Cu或Cu /金属接合期间使用氢等离子体预清洁铜表面的方法
公开(公告)号：US06720204B2
公开(公告)日：2004-04-13
申请号：US10120836
申请日：2002-04-11
申请人： John Leonard Sudijono , Yakub Aliyu , Mei Sheng Zhou , Simon Chooi , Subhash Gupta , Sudipto Ranendra Roy , Paul Kwok Keung Ho , Yi Xu
发明人： John Leonard Sudijono , Yakub Aliyu , Mei Sheng Zhou , Simon Chooi , Subhash Gupta , Sudipto Ranendra Roy , Paul Kwok Keung Ho , Yi Xu
IPC分类号： H01L2144
CPC分类号： H01L24/05 , C23G5/00 , H01L21/02046 , H01L21/32136 , H01L23/4824 , H01L24/03 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/85 , H01L2224/04042 , H01L2224/05001 , H01L2224/05073 , H01L2224/05118 , H01L2224/05124 , H01L2224/05155 , H01L2224/05166 , H01L2224/05556 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/4813 , H01L2224/4846 , H01L2224/48463 , H01L2224/4847 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/48824 , H01L2224/48844 , H01L2224/48847 , H01L2224/49111 , H01L2224/85013 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/05042 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/19042 , H01L2924/19043 , H01L2924/00014 , H01L2924/00 , H01L2224/48744 , H01L2924/00015
摘要： A method of bonding a wire to a metal bonding pad, comprising the following steps. A semiconductor die structure having an exposed metal bonding pad within a chamber is provided. The bonding pad has an upper surface. A hydrogen-plasma is produced within the chamber from a plasma source. The metal bonding pad is pre-cleaned and passivated with the hydrogen-plasma to remove any metal oxide formed on the metal bonding pad upper surface. A wire is then bonded to the passivated metal bonding pad.
摘要翻译：一种将金属丝焊接到金属焊盘上的方法，包括以下步骤。提供一种在室内具有暴露的金属接合焊盘的半导体管芯结构。接合垫具有上表面。在等离子体源室内产生氢等离子体。用氢 - 等离子体对金属接合垫进行预清洁和钝化以去除在金属焊盘上表面上形成的任何金属氧化物。然后将线接合到钝化金属接合焊盘。

65. 发明授权

US06692579B2 Method for cleaning semiconductor structures using hydrocarbon and solvents in a repetitive vapor phase/liquid phase sequence 失效
标题翻译：在重复气相/液相序列中使用烃和溶剂清洗半导体结构的方法
公开(公告)号：US06692579B2
公开(公告)日：2004-02-17
申请号：US09764244
申请日：2001-01-19
申请人： Sudipto Ranendra Roy , Yi Xu , Simon Chooi , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono , Paul Kwok Keung Ho , Subhash Gupta
发明人： Sudipto Ranendra Roy , Yi Xu , Simon Chooi , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono , Paul Kwok Keung Ho , Subhash Gupta
IPC分类号： B08B300
CPC分类号： H01L21/02057 , B08B3/00 , C11D7/24 , C11D7/5027 , C11D11/0047 , H01L21/02063 , H01L21/6704
摘要： A method for cleaning a semiconductor structure using vapor phase condensation with a thermally vaporized cleaning agent, a hydrocarbon vaporized by pressure variation, or a combination of the two. In the thermally vaporized cleaning agent process, a semiconductor structure is lowered into a vapor blanket in a thermal gradient cleaning chamber at atmospheric pressure formed by heating a liquid cleaning agent below the vapor blanket and cooling the liquid cleaning agent above the vapor blanket causing it to condense and return to the bottom of the thermal gradient cleaning chamber. The semiconductor structure is then raised above the vapor blanket and the cleaning agent condenses on all of the surfaces of the semiconductor structure removing contaminants and is returned to the bottom of the chamber by gravity. In the pressurized hydrocarbon process, a semiconductor structure is placed into a variable pressure cleaning chamber, having a piston which changes the pressure by reducing or increasing the volume of the chamber. The semiconductor structure first exposed to the hydrocarbon in vapor phase, then the piston is lowered to condense the hydrocarbon. A semiconductor structure can be cleaned by either or both of these processes by repetitive vaporization/condensation cycles.
摘要翻译：一种使用与气相清洗剂进行气相冷凝的半导体结构，通过压力变化蒸发的烃或两者的组合来清洗半导体结构的方法。在热蒸发清洗剂方法中，半导体结构在大气压力的热梯度清洗室内被降低成蒸气层，所述热梯度清洗室通过将蒸气层下方的液体清洗剂加热而形成，并将该液体清洁剂冷却至蒸气层以上冷凝并返回到热梯度清洗室的底部。然后将半导体结构升高到蒸气层上方，并且清洁剂在半导体结构的所有表面上冷凝除去杂质，并通过重力返回到室的底部。在加压烃工艺中，将半导体结构放置在可变压力清洁室中，其具有通过减小或增加室的体积来改变压力的活塞。半导体结构首先暴露于气相中的烃，然后降低活塞以使烃冷凝。半导体结构可以通过这些过程中的任一个或两者通过重复的蒸发/冷凝循环进行清洁。

66. 发明授权

US06429117B1 Method to create copper traps by modifying treatment on the dielectrics surface 有权
标题翻译：通过修改电介质表面处理来产生铜阱的方法
公开(公告)号：US06429117B1
公开(公告)日：2002-08-06
申请号：US09619018
申请日：2000-07-19
申请人： John Sudijono , Yakub Aliyu , Mei Sheng Zhou , Simon Chooi , Subhash Gupta , Sudipto Ranendra Roy , Paul Kwok Keung Ho , Yi Xu
发明人： John Sudijono , Yakub Aliyu , Mei Sheng Zhou , Simon Chooi , Subhash Gupta , Sudipto Ranendra Roy , Paul Kwok Keung Ho , Yi Xu
IPC分类号： H01L214763
CPC分类号： H01L21/76831 , H01L21/3105 , H01L21/31633 , H01L21/31695 , H01L21/76807 , H01L21/76814 , H01L21/76826 , Y10S438/958
摘要： A method of preventing metal penetration and diffusion from metal structures formed over a semiconductor structure, comprising the following steps. A semiconductor structure including a patterned dielectric layer is provided. The patterned dielectric layer includes an opening and an upper surface. The dielectric layer surface is then passivated to form a passivation layer. A metal plug is formed within the dielectric layer opening. The passivation layer prevents penetration and diffusion of metal out from the metal plug into the semiconductor structure and the patterned dielectric layer.
摘要翻译：一种防止在半导体结构上形成的金属结构的金属渗透和扩散的方法，包括以下步骤。提供包括图案化介电层的半导体结构。图案化电介质层包括开口和上表面。然后将介电层表面钝化以形成钝化层。在电介质层开口内形成金属塞。钝化层防止金属从金属插塞渗入并扩散到半导体结构和图案化的介电层中。

67. 发明授权

US06391732B1 Method to form self-aligned, L-shaped sidewall spacers 失效
标题翻译：形成自对准的L形侧壁间隔件的方法
公开(公告)号：US06391732B1
公开(公告)日：2002-05-21
申请号：US09595061
申请日：2000-06-16
申请人： Subhash Gupta , Yelehanka Ramachandramurthy , Vijai Kumar Chhagan
发明人： Subhash Gupta , Yelehanka Ramachandramurthy , Vijai Kumar Chhagan
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/266 , H01L21/31116 , H01L29/6656 , H01L29/7833
摘要： A new method of forming silicon nitride sidewall spacers has been achieved. In addition, a new device profile for a silicon nitride sidewall spacer has been achieved. An isolation region is provided overlying a semiconductor substrate. Polysilicon traces are provided. A liner oxide layer is formed overlying the polysilicon traces and the insulator layer. A silicon nitride layer is formed overlying the liner oxide layer. A polysilicon or amorphous silicon layer is deposited overlying the silicon nitride layer. The polysilicon or amorphous silicon layer is completely oxidized to form a temporary silicon dioxide layer. The temporary silicon dioxide layer is rounded in the corners due to volume expansion during the oxidation step. The temporary silicon dioxide layer is anisotropically etched through to expose horizontal surfaces of the silicon nitride layer while leaving vertical sidewalls of the temporary silicon dioxide layer. The silicon nitride layer is anisotropically etched to form silicon nitride sidewall spacers with an L-shaped profile. The integrated circuit device is completed.
摘要翻译：已经实现了形成氮化硅侧壁间隔物的新方法。此外，已经实现了用于氮化硅侧壁间隔物的新的器件配置。设置在半导体衬底上的隔离区域。提供多晶硅痕迹。在多晶硅迹线和绝缘体层上形成衬里氧化物层。形成覆盖衬垫氧化物层的氮化硅层。沉积氮化硅层上的多晶硅或非晶硅层。多晶硅或非晶硅层被完全氧化以形成临时二氧化硅层。在氧化步骤期间由于体积膨胀，临时二氧化硅层在角部被倒圆。临时二氧化硅层被各向异性地蚀刻以暴露氮化硅层的水平表面，同时留下临时二氧化硅层的垂直侧壁。氮化硅层被各向异性蚀刻以形成具有L形轮廓的氮化硅侧壁间隔物。集成电路装置完成。

68. 发明授权

US06380087B1 CMP process utilizing dummy plugs in damascene process 有权
标题翻译：在镶嵌工艺中使用假插头的CMP工艺
公开(公告)号：US06380087B1
公开(公告)日：2002-04-30
申请号：US09596901
申请日：2000-06-19
申请人： Subhash Gupta , Mei Sheng Zhou , Ramasamy Chockalingam
发明人： Subhash Gupta , Mei Sheng Zhou , Ramasamy Chockalingam
IPC分类号： H01L21302
CPC分类号： H01L24/02 , H01L21/7684 , H01L21/76877 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01082 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , Y10S438/926
摘要： A method of fabricating a semiconductor wafer having at least one integrated circuit, the method comprising the following steps. A semiconductor wafer structure having at least an upper and a lower dielectric layer is provided. The semiconductor wafer structure having a bonding pad area and an interconnect area. At least one active interconnect having a first width is formed in the interconnect area, through the dielectric layers. A plurality of adjacent dummy plugs each having a second width is formed in the bonding pad area, through a portion of the dielectric layers. The semiconductor wafer structure is patterned and etched to form trenches through the upper dielectric layer. The trenches surround each of the at least one active interconnect and the dummy plugs whereby the upper dielectric level between the adjacent dummy plugs is removed. A metallization layer is deposited over the lower dielectric layer, filling the trenches at least to the upper surface of the remaining upper dielectric layer. The metallization layer is planarized to remove the excess of the metallization layer forming a continuous bonding pad within the bonding pad area and including the plurality of adjacent dummy plugs, thus forming at least one damascene structure including the at least one respective active interconnect.
摘要翻译：一种制造具有至少一个集成电路的半导体晶片的方法，所述方法包括以下步骤。提供了至少具有上介电层和下电介质层的半导体晶片结构。该半导体晶片结构具有焊盘区域和互连区域。具有第一宽度的至少一个有源互连通过电介质层形成在互连区域中。通过电介质层的一部分，在焊盘区域中形成多个具有第二宽度的相邻虚拟插头。对半导体晶片结构进行图案化和蚀刻，以形成通过上部电介质层的沟槽。沟槽围绕至少一个有源互连和虚拟插头中的每一个，由此相邻虚拟插头之间的上部电介质层被去除。金属化层沉积在下电介质层上，至少填充到剩余的上电介质层的上表面上的沟槽。金属化层被平坦化以去除在焊盘区域内形成连续接合焊盘的多余的金属化层，并且包括多个相邻的虚设插头，从而形成包括至少一个相应的有源互连的至少一个镶嵌结构。

69. 发明授权

US06309982B1 Method for minimizing copper diffusion by doping an inorganic dielectric layer with a reducing agent 有权
标题翻译：通过用还原剂掺杂无机介电层来最小化铜扩散的方法
公开(公告)号：US06309982B1
公开(公告)日：2001-10-30
申请号：US09803188
申请日：2001-03-12
申请人： Simon Chooi , Yi Xu , Yakub Aliyu , Mei-Sheng Zhou , John Leonard Sudijono , Subhash Gupta , Sudipto Ranendra Roy , Paul Ho
发明人： Simon Chooi , Yi Xu , Yakub Aliyu , Mei-Sheng Zhou , John Leonard Sudijono , Subhash Gupta , Sudipto Ranendra Roy , Paul Ho
IPC分类号： H01L2131
CPC分类号： H01L21/02129 , H01L21/02126 , H01L21/02274 , H01L21/3115 , H01L21/31612 , H01L21/31625
摘要： A method for reducing copper diffusion into an inorganic dielectric layer adjacent to a copper structure by doping the inorganic dielectric layer with a reducing agent (e.g. phosphorous, sulfur, or both) during plasma enhanced chemical vapor deposition. The resulting doped inorganic dielectric layer can reduce copper diffusion without a barrier layer reducing fabrication cost and cycle time, as well as reducing RC delay.
摘要翻译：一种通过在等离子体增强化学气相沉积期间通过用还原剂（例如磷，硫或两者）掺杂无机介电层来减少铜扩散到与铜结构相邻的无机电介质层中的方法。所得到的掺杂无机介电层可以减少铜扩散而无需阻挡层降低制造成本和循环时间，并减少RC延迟。

70. 发明授权

US06261955B1 Application of vapor phase HFACAC-based compound for use in copper decontamination and cleaning processes 失效
标题翻译：应用气相HFACAC基化合物用于铜去污和清洗过程
公开(公告)号：US06261955B1
公开(公告)日：2001-07-17
申请号：US09618262
申请日：2000-07-18
申请人： Yakub Aliyu , Simon Chooi , Mei Sheng Zhou , John Leonard Sudijono , Subhash Gupta , Sudipto Ranendra Roy , Paul Kwok Keung Ho , Yi Xu
发明人： Yakub Aliyu , Simon Chooi , Mei Sheng Zhou , John Leonard Sudijono , Subhash Gupta , Sudipto Ranendra Roy , Paul Kwok Keung Ho , Yi Xu
IPC分类号： H01L2144
CPC分类号： H01L21/02046 , C23F1/12 , H01L21/02079 , Y10S438/906
摘要： An effective copper decontamination method in the fabrication of integrated circuits is achieved. An organic-based HFACAC decontamination compound in vapor phase is sprayed over elemental copper found on equipment or tools or as a spill wherein the compound reacts with all of the elemental copper and forms a volatile compound that can be flushed away thereby completing copper decontamination.
摘要翻译：实现了集成电路制造中有效的铜去污方法。蒸气相中的基于有机的HFACAC去污化合物喷洒在设备或工具上发现的元素铜上，或作为溢出物喷洒，其中化合物与所有元素铜反应并形成可被冲洗掉的挥发性化合物，从而完成铜去污。

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