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61. 发明申请

US20090276190A1 Method and Apparatus For Evaluating Integrated Circuit Design Performance Using Basic Block Vectors, Cycles Per Instruction (CPI) Information and Microarchitecture Dependent Information 有权
标题翻译：使用基本块向量，每个指令周期（CPI）信息和微架构依赖信息来评估集成电路设计性能的方法和装置
公开(公告)号：US20090276190A1
公开(公告)日：2009-11-05
申请号：US12112034
申请日：2008-04-30
申请人： Robert H. Bell, JR. , Thomas W. Chen , Venkat R. Indukuru , Alexander E. Mericas , Pattabi M. Seshadri , Madhavi G. Valluri
发明人： Robert H. Bell, JR. , Thomas W. Chen , Venkat R. Indukuru , Alexander E. Mericas , Pattabi M. Seshadri , Madhavi G. Valluri
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G01R31/318357 , G01R31/318364
摘要： A test system or simulator includes an integrated circuit (IC) benchmark software program that executes workload program software on a semiconductor die IC design model. The benchmark software program includes trace, simulation point, basic block vector (BBV) generation, cycles per instruction (CPI) error, clustering and other programs. The test system also includes CPI stack program software that generates CPI stack data that includes microarchitecture dependent information for each instruction interval of workload program software. The CPI stack data may also include an overall analysis of CPI data for the entire workload program. IC designers may utilize the benchmark software and CPI stack program to develop a reduced representative workload program that includes CPI data as well as microarchitecture dependent information.
摘要翻译：测试系统或模拟器包括在半导体芯片IC设计模型上执行工作负载程序软件的集成电路（IC）基准软件程序。基准软件程序包括跟踪，仿真点，基本块向量（BBV）生成，每个指令周期（CPI）错误，聚类和其他程序。测试系统还包括生成CPI堆栈数据的CPI堆栈程序软件，包括工作负载程序软件的每个指令间隔的微架构依赖信息。 CPI堆栈数据还可以包括整个工作负载程序的CPI数据的总体分析。 IC设计人员可以利用基准软件和CPI堆栈程序来开发一个减少代表性的工作量程序，其中包括CPI数据以及微架构依赖信息。

62. 发明申请

US20090164759A1 Execution of Single-Threaded Programs on a Multiprocessor Managed by an Operating System 有权
标题翻译：在操作系统管理的多处理器上执行单线程序
公开(公告)号：US20090164759A1
公开(公告)日：2009-06-25
申请号：US11959821
申请日：2007-12-19
申请人： Robert H. Bell, JR. , Louis Bennie Capps, JR. , Michael A. Paolini , Michael Jay Shapiro
发明人： Robert H. Bell, JR. , Louis Bennie Capps, JR. , Michael A. Paolini , Michael Jay Shapiro
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3851 , G06F9/505 , G06F2209/5017
摘要： A method and apparatus for speculatively executing a single threaded program within a multi-core processor which includes identifying an idle core within the multi-core processor, performing a look ahead operation on the single thread instructions to identify speculative instructions within the single thread instructions, and allocating the idle core to execute the speculative instructions.
摘要翻译：一种用于在多核处理器内推测性地执行单线程程序的方法和装置，其包括识别所述多核处理器内的空闲核心，对所述单线程指令执行向前操作以识别所述单线程指令内的推测指令，并分配空闲核心以执行推测性指令。

63. 发明授权

US07543109B1 System and method for caching data in a blade server complex 失效
标题翻译：用于在刀片服务器组合中缓存数据的系统和方法
公开(公告)号：US07543109B1
公开(公告)日：2009-06-02
申请号：US12122448
申请日：2008-05-16
申请人： Robert H. Bell, Jr. , Jose R. Escalera , Octavian F. Herescu , Vernon W. Miller , Michael D. Roll
发明人： Robert H. Bell, Jr. , Jose R. Escalera , Octavian F. Herescu , Vernon W. Miller , Michael D. Roll
IPC分类号： G06F12/02
CPC分类号： G06F12/126 , G06F12/0888
摘要： A method for caching data in a blade computing complex includes providing a storage blade that includes a disk operative to store pages of data and a cache memory operative to store at least one of the pages. A processor blade is provided that includes a first memory area to store at least one of the pages and a second memory area configured to store an address of each of the pages and a hint value that is assigned to each of the pages. An address of each of the pages is stored in the second memory area, and a hint is assigned to each of the pages, where the hint is one of: likely to be accessed, may be accessed, and unlikely to be accessed. The page is then stored in storage blade cache memory based on the hint.
摘要翻译：一种用于在刀片计算复合体中缓存数据的方法包括提供包括可操作以存储数据页的盘的存储刀片和可存储至少一个页的高速缓冲存储器。提供了一种处理器刀片，其包括用于存储所述页面中的至少一个的第一存储器区域和被配置为存储每个页面的地址的第二存储器区域以及分配给每个页面的提示值。每个页面的地址被存储在第二存储器区域中，并且提示被分配给每个页面，其中提示是可能被访问的，可能被访问并且不可能被访问。然后基于提示将该页面存储在存储刀片缓存中。

64. 发明申请

US20090138683A1 Dynamic instruction execution using distributed transaction priority registers 审中-公开
标题翻译：使用分布式事务优先级寄存器的动态指令执行
公开(公告)号：US20090138683A1
公开(公告)日：2009-05-28
申请号：US11946615
申请日：2007-11-28
申请人： Louis B. Capps, JR. , Robert H. Bell, JR.
发明人： Louis B. Capps, JR. , Robert H. Bell, JR.
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/30101 , G06F9/5011 , G06F2209/507 , Y02D10/22
摘要： A method, system and program are provided for dynamically assigning priority values to instruction threads in a computer system based on one or more predetermined thread performance tests, and using the assigned instruction priorities to determine how resources are used in the system. By storing the assigning priority values in thread priority registers distributed throughout the computer system, instructions from different threads that are dispatched through the system are allocated system resources based on the priority values assigned to the respective instruction threads. Priority values for individual threads may be updated with control software which tests thread performance and uses the test results to apply predetermined adjustment policies. The test results may be used to optimize the workload allocation of system resources by dynamically assigning thread priority values to individual threads using any desired policy, such as achieving thread execution balance relative to thresholds and to performance of other threads, reducing thread response time, lowering power consumption, etc.
摘要翻译：提供了一种方法，系统和程序，用于基于一个或多个预定的线程性能测试来动态地为计算机系统中的指令线程分配优先级值，并且使用所分配的指令优先级来确定如何在系统中使用资源。通过将分配的优先级值存储在整个计算机系统中分配的线程优先级寄存器中，基于分配给各个指令线程的优先级值，分配来自系统调度的不同线程的指令被分配给系统资源。可以使用测试线程性能的控制软件更新各个线程的优先级值，并使用测试结果来应用预定的调整策略。测试结果可用于通过使用任何期望的策略动态地将线程优先级值分配给各个线程来优化系统资源的工作量分配，例如实现相对于阈值的线程执行平衡以及其他线程的性能，减少线程响应时间，降低功耗等

65. 发明申请

US20090055153A1 Augmenting of Automated Clustering-Based Trace Sampling Methods by User-Directed Phase Detection 有权
标题翻译：通过用户定向相位检测来增强基于自动聚类的跟踪采样方法
公开(公告)号：US20090055153A1
公开(公告)日：2009-02-26
申请号：US11842337
申请日：2007-08-21
申请人： Robert H. Bell, JR. , Wen-Tzer Thomas Chen , Pattabi R. Seshadri , John-David Wellman
发明人： Robert H. Bell, JR. , Wen-Tzer Thomas Chen , Pattabi R. Seshadri , John-David Wellman
IPC分类号： G06F9/455
CPC分类号： G06F9/455 , G06F11/3636 , G06F11/3664
摘要： Computer implemented method, system, and computer usable program code for simulating processor operation in a data processing system. An instruction trace is generated, wherein the instruction trace includes markers specified by a user for identifying interval boundaries for at least one interval of the instruction trace. The instruction trace is divided into a plurality of intervals in consideration of the markers, and the plurality of intervals are formed into a plurality of interval clusters, wherein each interval cluster represents one phase of execution of the instruction trace. At least one interval from each of the plurality of interval clusters is selected as a trace sample to provide a plurality of trace samples, wherein each selected interval is of at least a minimum size, a simulation is performed using the plurality of trace samples, and a result of the simulation is provided to the user.
摘要翻译：用于在数据处理系统中模拟处理器操作的计算机实现的方法，系统和计算机可用程序代码。生成指令轨迹，其中指令轨迹包括由用户指定的用于识别指令轨迹的至少一个间隔的间隔边界的标记。考虑到标记，指令轨迹被分成多个间隔，并且多个间隔被形成为多个间隔簇，其中每个间隔簇表示指令轨迹的执行的一个阶段。选择来自多个间隔群集中的每一个的至少一个间隔作为跟踪样本以提供多个跟踪样本，其中每个选择的间隔至少为最小尺寸，使用多个迹线样本进行模拟，以及向用户提供模拟的结果。

66. 发明申请

US20080307203A1 Scaling Instruction Intervals to Identify Collection Points for Representative Instruction Traces 失效
标题翻译：缩放指令间隔以识别代表性指令跟踪的收集点
公开(公告)号：US20080307203A1
公开(公告)日：2008-12-11
申请号：US11758031
申请日：2007-06-05
申请人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Richard J. Eickemeyer , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
发明人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Richard J. Eickemeyer , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
IPC分类号： G06F9/30
CPC分类号： G06F11/36
摘要： A method, system, and computer program product are provided for identifying instructions to obtain representative traces. A phase instruction budget is calculated for each phase in a set of phases. The phase instruction budget is based on a weight associated with each phase and a global instruction budget. A starting index and an ending index are identified for instructions within a set of intervals in each phase in order to meet the phase instruction budget for that phase, thereby forming a set of interval indices. A determination is made as to whether the instructions within the set of interval indices meet the global instruction budget. Responsive to the global instruction budget being met, the set of interval indices are output as collection points for the representative traces.
摘要翻译：提供方法，系统和计算机程序产品用于识别指令以获得代表性迹线。针对一组阶段中的每个阶段计算相位指令预算。相位指令预算基于与每个阶段相关联的权重和全局指令预算。为了满足该阶段的相位指令预算，为每个阶段的一组间隔内的指令识别开始索引和结束索引，从而形成一组间隔索引。确定区间指标集内的指令是否符合全球指令预算。响应于满足全球指令预算，间隔指数的集合作为代表性跟踪的收集点输出。

67. 发明授权

US07363433B2 Cache member protection with partial make MRU allocation 失效
标题翻译：缓存成员保护部分使MRU分配
公开(公告)号：US07363433B2
公开(公告)日：2008-04-22
申请号：US11054390
申请日：2005-02-09
申请人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/0897 , G06F12/123 , G06F12/128
摘要： A method and apparatus for enabling protection of a particular member of a cache during LRU victim selection. LRU state array includes additional “protection” bits in addition to the state bits. The protection bits serve as a pointer to identify the location of the member of the congruence class that is to be protected. A protected member is not removed from the cache during standard LRU victim selection, unless that member is invalid. The protection bits are pipelined to MRU update logic, where they are used to generate an MRU vector. The particular member identified by the MRU vector (and pointer) is protected from selection as the next LRU victim, unless the member is Invalid. The make MRU operation affects only the lower level LRU state bits arranged a tree-based structure and thus only negates the selection of the protected member, without affecting LRU victim selection of the other members.
摘要翻译：一种用于在LRU受害者选择期间能够保护缓存的特定成员的方法和装置。 LRU状态阵列除了状态位之外还包括额外的“保护”位。保护位用作用于标识要保护的同余类的成员的位置的指针。在标准LRU受害者选择期间，保护成员不会从缓存中删除，除非该成员无效。保护位被流水线到MRU更新逻辑，它们用于生成MRU向量。由MRU向量（和指针）标识的特定成员不被选择作为下一个LRU受害者，除非成员无效。使MRU操作仅影响布置了基于树的结构的较低级LRU状态位，并且因此仅在不影响其他成员的LRU受害者选择的情况下，否定受保护成员的选择。

68. 发明授权

US06950892B2 Method and system for managing distributed arbitration for multicycle data transfer requests 失效
标题翻译：用于管理多周期数据传输请求的分布式仲裁的方法和系统
公开(公告)号：US06950892B2
公开(公告)日：2005-09-27
申请号：US10411463
申请日：2003-04-10
申请人： Robert H. Bell, Jr. , Robert Alan Cargnoni
发明人： Robert H. Bell, Jr. , Robert Alan Cargnoni
IPC分类号： G06F13/372 , G06F12/00 , G06F12/08 , G06F13/14 , G06F13/364 , G06F13/368
CPC分类号： G06F13/364 , G06F12/0846
摘要： A method and system for managing distributed arbitration for multi-cycle data transfer requests provides improved performance in a processing system. A multi-cycle request indicator is provided to a slice arbiter and if a multi-cycle request is present, only one slice is granted its associated bus. The method further blocks any requests from other requesting slices having a lower latency than the first slice until the latency difference between the other requesting slices and the longest latency slice added to a predetermined cycle counter value has expired. The method also blocks further requests from the first slice until the predetermined cycle counter value has elapsed and blocks requests from slices having a higher latency than the first slice until the predetermined cycle counter value less the difference in latencies for the first slice and for the higher latency slice has elapsed.
摘要翻译：用于管理多循环数据传输请求的分布式仲裁的方法和系统在处理系统中提供改善的性能。多周期请求指示符被提供给切片仲裁器，并且如果存在多周期请求，则只有一个切片被授予其相关联的总线。该方法进一步阻止来自具有比第一片低的等待时间的其他请求片的任何请求，直到其他请求片之间的等待时间差与添加到预定周期计数值的最长等待时间片已经期满为止。该方法还阻止来自第一片的进一步请求，直到经过了预定周期计数器值，并且阻止来自具有比第一片的更高等待时间的片的请求，直到预定周期计数值减去第一片的延迟差和较高延迟片已过。

69. 发明授权

US09582284B2 Performance of processors is improved by limiting number of branch prediction levels 有权
标题翻译：通过限制分支预测级别的数量来提高处理器的性能
公开(公告)号：US09582284B2
公开(公告)日：2017-02-28
申请号：US13308696
申请日：2011-12-01
申请人： Robert H. Bell, Jr. , Wen-Tzer T. Chen
发明人： Robert H. Bell, Jr. , Wen-Tzer T. Chen
IPC分类号： G06F9/38 , G06F11/30
CPC分类号： G06F9/3844 , G06F9/3842 , G06F11/30 , G06F11/3024 , G06F11/3409 , G06F2201/81
摘要： A method utilizes information provided by performance monitoring hardware to dynamically adjust the number of levels of speculative branch predictions allowed (typically 3 or 4 per thread) for a processor core. The information includes cycles-per-instruction (CPI) for the processor core and number of memory accesses per unit time. If the CPI is below a CPI threshold; and the number of memory accesses (NMA) per unit time is above a prescribed threshold, the number of levels of speculative branch predictions is reduced per thread for the processor core. Likewise, the number of levels of speculative branch predictions could be increased, from a low level to maximum allowed, if the CPI threshold is exceeded or the number of memory accesses per unit time is below the prescribed threshold.
摘要翻译：一种方法利用由性能监视硬件提供的信息来动态调整对于处理器核心允许的推测分支预测级别（通常为每线程3或4个）。该信息包括处理器核心的每个指令周期（CPI）和每单位时间的存储器访问次数。如果CPI低于CPI阈值; 并且每单位时间的存储器访问次数（NMA）高于规定的阈值，则对于处理器核，每个线程的推测分支预测的级别数量减少。同样地，如果超过CPI阈值或每单位时间的存储器访问次数低于规定的阈值，则可以将推测分支预测的级数从低级别增加到允许的最大级别。

70. 发明授权

US09298458B2 Performance of emerging applications in a virtualized environment using transient instruction streams 有权
公开(公告)号：US09298458B2
公开(公告)日：2016-03-29
申请号：US13427083
申请日：2012-03-22
申请人： Robert H. Bell, Jr. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
发明人： Robert H. Bell, Jr. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30054 , G06F9/30185 , G06F9/3802
摘要： A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction request thread. Subsequent fetches or prefetches in the request thread are treated as transient and are not written to lower-level caches. If an instruction is non-transient, and if a lower-level cache is non-inclusive of the L1 instruction cache, a fetch or prefetch miss that is obtained from memory may be written in both the L1 and the lower-level cache. If it is not inclusive, a cast-out from the L1 instruction cache may be written in the lower-level cache.

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