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61. 发明申请

US20090276191A1 Method And Apparatus For Integrated Circuit Design Model Performance Evaluation Using Basic Block Vector Clustering And Fly-By Vector Clustering 有权
标题翻译：使用基本块矢量聚类和飞行矢量聚类的集成电路设计模型性能评估的方法和装置
公开(公告)号：US20090276191A1
公开(公告)日：2009-11-05
申请号：US12112035
申请日：2008-04-30
申请人： Robert H. Bell, JR. , Wen-Tzer Thomas Chen , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
发明人： Robert H. Bell, JR. , Wen-Tzer Thomas Chen , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G01R31/318357 , G06F11/3428 , G06F11/3457 , G06F11/3664
摘要： A test system or simulator includes an enhanced IC test application sampling software program that executes test application software on a semiconductor die IC design model. The enhanced test application sampling software may include trace, simulation point, CPI error, clustering, instruction budgeting, and other programs. The enhanced test application sampling software generates basic block vectors (BBVs) and fly-by vectors (FBVs) from instruction trace analysis of test application software workloads. The enhanced test application sampling software utilizes the microarchitecture dependent information to generate the FBVs to select representative instruction intervals from the test application software. The enhanced test application sampling software generates a reduced representative test application software program from the BBV and FBV data utilizing a global instruction budgeting analysis method. Designers use the test system with enhanced test application sampling software to evaluate IC design models by using the representative test application software program.
摘要翻译：测试系统或模拟器包括在半导体芯片IC设计模型上执行测试应用软件的增强型IC测试应用采样软件程序。增强的测试应用程序采样软件可能包括跟踪，模拟点，CPI错误，聚类，指令预算和其他程序。增强的测试应用采样软件从测试应用软件工作负载的指令跟踪分析中生成基本块向量（BBV）和飞越向量（FBV）。增强的测试应用采样软件利用微架构依赖信息生成FBV，以从测试应用软件中选择代表性指令间隔。增强的测试应用采样软件利用全球指令预算分析方法，从BBV和FBV数据生成代表性测试应用软件程序。设计人员使用带有增强型测试应用程序采样软件的测试系统，通过使用代表性的测试应用软件程序来评估IC设计模型。

62. 发明申请

US20090164812A1 Dynamic processor reconfiguration for low power without reducing performance based on workload execution characteristics 失效
标题翻译：动态处理器重新配置为低功耗，而不会降低基于工作负载执行特性的性能
公开(公告)号：US20090164812A1
公开(公告)日：2009-06-25
申请号：US11960163
申请日：2007-12-19
申请人： Louis B. Capps, JR. , Robert H. Bell, JR. , Michael J. Shapiro
发明人： Louis B. Capps, JR. , Robert H. Bell, JR. , Michael J. Shapiro
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3243 , Y02D10/152 , Y02D50/20
摘要： A method, system and program are provided for dynamically reconfiguring a pipelined processor to operate with reduced power consumption without reducing existing performance. By monitoring or detecting the performance of individual units or stages in the processor as they execute a given workload, each stage may use high-performance circuitry until such time as a drop in the throughput performance is detected, at which point the stages are reconfigured to use lower-performance circuitry so as to meet the reduced performance throughput requirements using less power. By configuring the processor to back off from high-performance designs to low-performance designs to meet the detected performance characteristics of the executing workload warrant, power dissipation may be optimized.
摘要翻译：提供了一种方法，系统和程序，用于动态重新配置流水线处理器，以降低功耗进行操作，而不会降低现有性能。通过在处理器执行给定工作负载时监视或检测处理器中的各个单元或级的性能，每个级可以使用高性能电路，直到检测到吞吐量性能下降为止，此时将级重新配置为使用低性能电路，以便通过更少的功率来满足降低的性能吞吐量要求。通过将处理器配置为从高性能设计退回到低性能设计，以满足检测到的执行工作量保证的性能特征，可以优化功耗。

63. 发明申请

US20090164399A1 Method for Autonomic Workload Distribution on a Multicore Processor 有权
标题翻译：多核处理器上的自动工作负载分配方法
公开(公告)号：US20090164399A1
公开(公告)日：2009-06-25
申请号：US11959520
申请日：2007-12-19
申请人： Robert H. Bell, JR. , Louis Bennie Capps, JR. , Thomas Edward Cook , Thomas J. Dewkett , Naresh Nayar , Ronald Edward Newhart , Bernadette Ann Pierson , Michael Jay Shapiro
发明人： Robert H. Bell, JR. , Louis Bennie Capps, JR. , Thomas Edward Cook , Thomas J. Dewkett , Naresh Nayar , Ronald Edward Newhart , Bernadette Ann Pierson , Michael Jay Shapiro
IPC分类号： G06F15/76 , G06F15/18
CPC分类号： G06F9/5083
摘要： A multiprocessor system which includes automatic workload distribution. As threads execute in the multiprocessor system, an operating system or hypervisor continuously learns the execution characteristics of the threads and saves the information in thread-specific control blocks. The execution characteristics are used to generate thread performance data. As the thread executes, the operating system continuously uses the performance data to steer the thread to a core that will execute the workload most efficiently.
摘要翻译：一个包含自动工作负载分配的多处理器系统。当线程在多处理器系统中执行时，操作系统或管理程序将持续学习线程的执行特性，并将信息保存在线程特定的控制块中。执行特性用于生成线程性能数据。当线程执行时，操作系统会持续使用性能数据来将线程引导到最高效执行工作负载的内核。

64. 发明申请

US20090138660A1 Power-aware line intervention for a multiprocessor snoop coherency protocol 有权
标题翻译：多处理器侦听一致性协议的功率感知线路干预
公开(公告)号：US20090138660A1
公开(公告)日：2009-05-28
申请号：US11946249
申请日：2007-11-28
申请人： Robert H. Bell, JR. , Louis B. Capps, JR. , Thomas E. Cook , Michael J. Shapiro , Naresh Nayar
发明人： Robert H. Bell, JR. , Louis B. Capps, JR. , Thomas E. Cook , Michael J. Shapiro , Naresh Nayar
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F2212/1028 , Y02D10/13
摘要： A snoop coherency method, system and program are provided for intervening a requested cache line from a plurality of candidate memory sources in a multiprocessor system on the basis of the sensed temperature or power dissipation value at each memory source. By providing temperature or power dissipation sensors in each of the candidate memory sources (e.g., at cores, cache memories, memory controller, etc.) that share a requested cache line, control logic may be used to determine which memory source should source the cache line by using the power sensor signals to signal only the memory source with acceptable power dissipation to provide the cache line to the requester.
摘要翻译：提供窥探一致性方法，系统和程序，用于基于每个存储器源处的感测温度或功率耗散值，在多处理器系统中从多个候选存储器源插入所请求的高速缓存行。通过在共享所请求的高速缓存行的每个候选存储器源（例如，在内核，高速缓冲存储器，存储器控制器等）中提供温度或功率耗散传感器，可以使用控制逻辑来确定哪个存储器源应该来源于高速缓存通过使用功率传感器信号仅以可接受的功率消耗信号通知存储器源，以向请求器提供高速缓存线。

65. 发明授权

US09582284B2 Performance of processors is improved by limiting number of branch prediction levels 有权
标题翻译：通过限制分支预测级别的数量来提高处理器的性能
公开(公告)号：US09582284B2
公开(公告)日：2017-02-28
申请号：US13308696
申请日：2011-12-01
申请人： Robert H. Bell, Jr. , Wen-Tzer T. Chen
发明人： Robert H. Bell, Jr. , Wen-Tzer T. Chen
IPC分类号： G06F9/38 , G06F11/30
CPC分类号： G06F9/3844 , G06F9/3842 , G06F11/30 , G06F11/3024 , G06F11/3409 , G06F2201/81
摘要： A method utilizes information provided by performance monitoring hardware to dynamically adjust the number of levels of speculative branch predictions allowed (typically 3 or 4 per thread) for a processor core. The information includes cycles-per-instruction (CPI) for the processor core and number of memory accesses per unit time. If the CPI is below a CPI threshold; and the number of memory accesses (NMA) per unit time is above a prescribed threshold, the number of levels of speculative branch predictions is reduced per thread for the processor core. Likewise, the number of levels of speculative branch predictions could be increased, from a low level to maximum allowed, if the CPI threshold is exceeded or the number of memory accesses per unit time is below the prescribed threshold.
摘要翻译：一种方法利用由性能监视硬件提供的信息来动态调整对于处理器核心允许的推测分支预测级别（通常为每线程3或4个）。该信息包括处理器核心的每个指令周期（CPI）和每单位时间的存储器访问次数。如果CPI低于CPI阈值; 并且每单位时间的存储器访问次数（NMA）高于规定的阈值，则对于处理器核，每个线程的推测分支预测的级别数量减少。同样地，如果超过CPI阈值或每单位时间的存储器访问次数低于规定的阈值，则可以将推测分支预测的级数从低级别增加到允许的最大级别。

66. 发明授权

US09298458B2 Performance of emerging applications in a virtualized environment using transient instruction streams 有权
公开(公告)号：US09298458B2
公开(公告)日：2016-03-29
申请号：US13427083
申请日：2012-03-22
申请人： Robert H. Bell, Jr. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
发明人： Robert H. Bell, Jr. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30054 , G06F9/30185 , G06F9/3802
摘要： A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction request thread. Subsequent fetches or prefetches in the request thread are treated as transient and are not written to lower-level caches. If an instruction is non-transient, and if a lower-level cache is non-inclusive of the L1 instruction cache, a fetch or prefetch miss that is obtained from memory may be written in both the L1 and the lower-level cache. If it is not inclusive, a cast-out from the L1 instruction cache may be written in the lower-level cache.

67. 发明授权

US08943272B2 Variable cache line size management 有权
标题翻译：可变缓存行大小管理
公开(公告)号：US08943272B2
公开(公告)日：2015-01-27
申请号：US13451742
申请日：2012-04-20
申请人： Robert H. Bell, Jr. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
发明人： Robert H. Bell, Jr. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/08 , G06F12/0811 , G06F12/0897
摘要： According to one aspect of the present disclosure, a method and technique for variable cache line size management is disclosed. The method includes: determining whether an eviction of a cache line from an upper level sectored cache to an unsectored lower level cache is to be performed, wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache; responsive to determining that an eviction is to be performed, identifying referenced sub-sectors of the cache line to be evicted; invalidating unreferenced sub-sectors of the cache line to be evicted; and storing the referenced sub-sectors in the lower level cache.
摘要翻译：根据本公开的一个方面，公开了一种用于可变高速缓存行大小管理的方法和技术。该方法包括：确定是否执行将高速缓存行从高级扇区高速缓存驱逐到未故障的较低级高速缓存，其中高级缓存包括多个子扇区，每个子扇区具有高速缓存行对应于较低级缓存的高速缓存行大小的大小; 响应于确定要执行驱逐，识别要被驱逐的高速缓存行的参考子扇区; 使要删除的缓存行的未引用子扇区无效; 并将所引用的子扇区存储在下级缓存中。

68. 发明授权

US08769210B2 Dynamic prioritization of cache access 有权
标题翻译：高速缓存访问的动态优先级
公开(公告)号：US08769210B2
公开(公告)日：2014-07-01
申请号：US13323076
申请日：2011-12-12
申请人： Robert H. Bell, Jr. , Hong L. Hua , William A. Maron , Mysore S. Srinivas
发明人： Robert H. Bell, Jr. , Hong L. Hua , William A. Maron , Mysore S. Srinivas
IPC分类号： G06F12/08
CPC分类号： G06F12/0815
摘要： Some embodiments of the inventive subject matter are directed to a cache comprising a tracking unit and cache state machines. In some embodiments, the tracking unit is configured to track an amount of cache resources used to service cache misses within a past period. In some embodiments, each of the cache state machines is configured to, determine whether a memory access request results in a cache miss or cache hit, and in response to a cache miss for a memory access request, query the tracking unit for the amount of cache resources used to service cache misses within the past period. In some embodiments, the each of the cache state machines is configured to service the memory access request based, at least in part, on the amount of cache resources used to service the cache misses within the past period according to the tracking unit.
摘要翻译：本发明主题的一些实施例涉及包括跟踪单元和高速缓存状态机的高速缓存。在一些实施例中，跟踪单元被配置为跟踪用于在过去时间段内服务高速缓存未命中的高速缓存资源的量。在一些实施例中，每个高速缓存状态机被配置为，确定存储器访问请求是否导致高速缓存未命中或高速缓存命中，并且响应于存储器访问请求的高速缓存未命中，查询跟踪单元的数量用于在过去一段时间内缓存未命中服务的缓存资源。在一些实施例中，每个高速缓存状态机被配置为至少部分地基于用于根据跟踪单元在过去时段内服务高速缓存未命中的高速缓存资源的量来服务存储器访问请求。

69. 发明授权

US08527956B2 Workload performance projection via surrogate program analysis for future information handling systems 失效
标题翻译：通过代理程序分析进行未来信息处理系统的工作负载性能预测
公开(公告)号：US08527956B2
公开(公告)日：2013-09-03
申请号：US12343467
申请日：2008-12-23
申请人： Robert H. Bell, Jr. , Luigi Brochard , Donald Robert DeSota , Venkat R. Indukuru , Rajendra D. Panda , Sameh S. Sharkawi
发明人： Robert H. Bell, Jr. , Luigi Brochard , Donald Robert DeSota , Venkat R. Indukuru , Rajendra D. Panda , Sameh S. Sharkawi
IPC分类号： G06F9/44
CPC分类号： G06F11/3419 , G06F11/3414 , G06F11/3457 , G06F2201/865 , G06F2201/88
摘要： A performance projection system includes a test IHS and multiple currently existing IHSs. The performance projection system includes user application software and surrogate programs that execute on currently existing IHSs. The performance projection system measures user application software and surrogate program performance during execution on currently existing IHSs. The performance projection systems measures runtime program performance during execution of surrogate programs on a future semiconductor die IC design model or virtualized future system. Designers normalize and compare surrogate program runtime performance data with user application software performance data. Designers un-normalize the normalized runtime performance data to generate a projection of runtime performance on the future system.
摘要翻译：性能投影系统包括测试IHS和多个当前存在的IHS。性能投影系统包括在当前存在的IHS上执行的用户应用软件和代理程序。性能投影系统在目前现有的IHSs的执行过程中测量用户应用软件和代理程序性能。性能投影系统在未来的半导体芯片IC设计模型或虚拟化未来系统执行替代程序期间测量运行时程序性能。设计师将代理程序运行时性能数据与用户应用软件性能数据进行规范化和比较。设计师对规范化的运行时性能数据进行非规范化，以生成对未来系统的运行时性能的投影。

70. 发明申请

US20130151784A1 DYNAMIC PRIORITIZATION OF CACHE ACCESS 失效
标题翻译：缓存访问动态优先
公开(公告)号：US20130151784A1
公开(公告)日：2013-06-13
申请号：US13586518
申请日：2012-08-15
申请人： Robert H. Bell, JR. , Hong L. Hua , William A. Maron , Mysore S. Srinivas
发明人： Robert H. Bell, JR. , Hong L. Hua , William A. Maron , Mysore S. Srinivas
IPC分类号： G06F12/12
CPC分类号： G06F12/0815
摘要： Some embodiments of the inventive subject matter are directed to determining that a memory access request results in a cache miss and determining an amount of cache resources used to service cache misses within a past period in response to determining that the memory access request results in the cache miss. Some embodiments are further directed to determining that servicing the memory access request would increase the amount of cache resources used to service cache misses within the past period to exceed a threshold. In some embodiments, the threshold corresponds to reservation of a given amount of cache resources for potential cache hits. Some embodiments are further directed to rejecting the memory access request in response to the determining that servicing the memory access request would increase the amount of cache resources used to service cache misses within the past period to exceed the threshold.
摘要翻译：本发明的一些实施例涉及确定存储器访问请求导致高速缓存未命中，并且响应于确定存储器访问请求导致高速缓存而确定用于在过去时段内服务高速缓存未命中的高速缓存资源量小姐。一些实施例进一步涉及确定对存储器访问请求的服务将增加用于在过去时间段内服务高速缓存未命中的高速缓存资源的数量超过阈值。在一些实施例中，阈值对应于用于潜在高速缓存命中的给定量的高速缓存资源的预留。响应于确定对存储器访问请求的服务会增加在过去时间段内用于服务高速缓存未命中的高速缓存资源的数量超过阈值，一些实施例进一步涉及拒绝存储器访问请求。

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