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61. 发明授权

US07865792B2 Test generation methods for reducing power dissipation and supply currents 有权
标题翻译：用于降低功耗和电源电流的测试生成方法
公开(公告)号：US07865792B2
公开(公告)日：2011-01-04
申请号：US12703057
申请日：2010-02-09
申请人： Xijiang Lin , Janusz Rajski
发明人： Xijiang Lin , Janusz Rajski
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31721 , G01R31/318357 , G01R31/318575
摘要： Disclosed herein are representative embodiments of methods, apparatus, and systems used for generating test patterns as may be used as part of a test pattern generation process (for example, for use with an automatic test pattern generator (ATPG) software tool). In one exemplary embodiment, hold probabilities are determined for state elements (for example, scan cells) of a circuit design. A test cube is generated targeting one or more faults in the circuit design. In one particular implementation, the test cube initially comprises specified values that target the one or more faults and further comprises unspecified values. The test cube is modified by specifying at least a portion of the unspecified values with values determined at least in part from the hold probabilities and stored.
摘要翻译：这里公开的是用于生成测试图案的方法，装置和系统的代表性实施例，可用作测试图案生成过程的一部分（例如，用于自动测试图案生成器（ATPG）软件工具））。在一个示例性实施例中，为电路设计的状态元素（例如，扫描单元）确定保持概率。产生针对电路设计中的一个或多个故障的测试立方体。在一个特定实现中，测试多维数据集最初包括指定的一个或多个故障的值，并且还包括未指定的值。通过至少部分由保存概率确定的值来指定至少一部分未指定值来修改测试立方体，并存储。

62. 发明申请

US20100313089A1 Scan Test Application Through High-Speed Serial Input/Outputs 有权
标题翻译：通过高速串行输入/输出进行扫描测试应用
公开(公告)号：US20100313089A1
公开(公告)日：2010-12-09
申请号：US12506250
申请日：2009-07-20
申请人： Janusz Rajski , Nilanjan Mukherjee , Mark A. Kassab , Thomas H. Rinderknecht , Mohamed Dessouky
发明人： Janusz Rajski , Nilanjan Mukherjee , Mark A. Kassab , Thomas H. Rinderknecht , Mohamed Dessouky
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318547
摘要： Methods and devices for using high-speed serial links for scan testing are disclosed. The methods can work with any scheme of scan data compression or with uncompressed scan testing. The protocol and hardware to support high speed data transfer reside on both the tester and the device under test. Control data may be transferred along with scan data or be partially generated on chip. Clock signals for testing may be generated on chip as well. In various implementations, the SerDes (Serializer/Deserializer) may be shared with other applications. The Aurora Protocol may be used to transport industry standard protocols. To compensate for effects of asynchronous operation of a conventional high-speed serial link, buffers may be used. The high-speed serial interface may use a data conversion block to drive test cores.
摘要翻译：公开了使用高速串行链路进行扫描测试的方法和装置。这些方法可以使用任何扫描数据压缩或未压缩扫描测试方案。支持高速数据传输的协议和硬件位于测试仪和被测设备上。控制数据可以与扫描数据一起传输或者在芯片上部分产生。用于测试的时钟信号也可以在芯片上生成。在各种实现中，SerDes（串行器/解串器）可以与其他应用共享。极光协议可用于传输行业标准协议。为了补偿常规高速串行链路的异步操作的效果，可以使用缓冲器。高速串行接口可以使用数据转换块来驱动测试核心。

63. 发明申请

US20100306609A1 Low Power Decompression Of Test Cubes 有权
标题翻译：测试立方体的低功率减压
公开(公告)号：US20100306609A1
公开(公告)日：2010-12-02
申请号：US12854786
申请日：2010-08-11
申请人： Janusz Rajski , Grzegorz Mrugalski , Dariusz Czysz , Jerzy Tyszer
发明人： Janusz Rajski , Grzegorz Mrugalski , Dariusz Czysz , Jerzy Tyszer
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31921 , G01R31/318335
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.
摘要翻译：以下公开了用于产生用于测试集成电路的测试图案的方法，装置和系统的代表性实施例。所公开的技术的实施例可以用于提供低功率测试方案，并且可以与各种压缩硬件架构（例如，嵌入式确定性测试（“EDT”）环境）集成。所公开的技术的某些实施例可以在没有硬件修改的情况下降低扫描链中的开关速率，从而降低功耗。其他实施例使用专门的减压硬件和压缩技术来实现低功率测试。

64. 发明申请

US20100306606A1 COMPACTOR INDEPENDENT DIRECT DIAGNOSIS OF TEST HARDWARE 有权
标题翻译：测试硬件的独立直接诊断测试
公开(公告)号：US20100306606A1
公开(公告)日：2010-12-02
申请号：US12790049
申请日：2010-05-28
申请人： Yu Huang , Wu-Tung Cheng , Janusz Rajski
发明人： Yu Huang , Wu-Tung Cheng , Janusz Rajski
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318547 , G06F11/267 , G06F11/27
摘要： Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In one exemplary embodiment, a failure log is received comprising entries indicative of compressed test responses to chain patterns and compressed test responses to scan patterns. A faulty scan chain in the circuit-under-test is identified based at least in part on one or more of the entries indicative of the compressed test responses to chain patterns. One or more faulty scan cell candidates in the faulty scan chain are identified based at least in part on one or more of the entries indicative of the compressed test responses to scan patterns. The one or more identified scan cell candidates can be reported. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Likewise, computer-readable media storing lists of fault candidates identified by any of the disclosed methods are also provided.
摘要翻译：本文公开了用于执行故障诊断的方法，装置和系统。在一个示例性实施例中，接收到故障日志，其包括指示对链模式的压缩测试响应的条目和对扫描模式的压缩测试响应。至少部分地基于指示压缩的测试对链模式的测试响应的一个或多个条目来识别被测电路中的有缺陷的扫描链。至少部分地基于指示对扫描模式的压缩测试响应的一个或多个条目来识别故障扫描链中的一个或多个错误的扫描小区候选。可以报告一个或多个识别的扫描单元候选。还提供了包括用于使计算机执行任何所公开的方法的计算机可执行指令的计算机可读介质。同样，还提供了存储通过任何所公开的方法识别的故障候选列表的计算机可读介质。

65. 发明授权

US07818644B2 Multi-stage test response compactors 有权
标题翻译：多级测试响应压实机
公开(公告)号：US07818644B2
公开(公告)日：2010-10-19
申请号：US11709071
申请日：2007-02-20
申请人： Janusz Rajski , Jerzy Tyszer , Grzegorz Mrugalski , Mark Kassab , Wu-Tung Cheng
发明人： Janusz Rajski , Jerzy Tyszer , Grzegorz Mrugalski , Mark Kassab , Wu-Tung Cheng
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/2851 , G01R31/31723 , G01R31/31727 , G01R31/318547 , G01R31/318563 , G01R31/318566
摘要： Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.
摘要翻译：这里公开了所谓的“X-press”测试响应压实机的示例性实施例。所公开的压实机的某些实施例包括过驱动部分和扫描链选择逻辑。所公开技术的某些实施例提供大约1000×的压实比。所公开的压实机的示例性实施例可以保持与传统的基于扫描的测试场景相同的覆盖范围和大约相同的诊断分辨率。扫描链选择方案的一些实施例可以显着地减少或完全消除在进入压实机的测试响应中发生的未知状态。本文还公开了片上比较器电路和用于产生用于屏蔽选择电路的控制电路的方法的实施例。

66. 发明授权

US07805649B2 Method and apparatus for selectively compacting test responses 有权
标题翻译：用于选择性压实测试响应的方法和装置
公开(公告)号：US07805649B2
公开(公告)日：2010-09-28
申请号：US12396377
申请日：2009-03-02
申请人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
发明人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.
摘要翻译：一种在确定性测试环境中压缩包含未知值或多个故障效应的测试响应的方法和装置。所提出的选择性压实机采用具有用于选择性地将测试响应传递给压实机的选择电路的线性压实机。在一个实施例中，门控逻辑由控制寄存器，解码器和标志寄存器控制。该电路结合任何常规的并行测试响应压缩方案，允许控制电路选择性地使所需扫描链的串行输出以特定时钟速率馈送到并联压实机。第一个标志寄存器确定是否启用所有或只有一些扫描链输出并通过压实器馈送。第二个标志寄存器确定选择器寄存器选择的扫描链是否启用，所有其他扫描链是禁用的，还是禁用所选扫描链，并启用所有其他扫描链。其他实施例允许对可变数目的扫描链输出的选择性掩蔽。

67. 发明授权

US07797603B2 Low power decompression of test cubes 有权
标题翻译：测试立方体的低功率减压
公开(公告)号：US07797603B2
公开(公告)日：2010-09-14
申请号：US11880373
申请日：2007-07-19
申请人： Janusz Rajski , Grzegorz Mrugalski , Dariusz Czysz , Jerzy Tyszer
发明人： Janusz Rajski , Grzegorz Mrugalski , Dariusz Czysz , Jerzy Tyszer
IPC分类号： G01R31/28
CPC分类号： G01R31/31921 , G01R31/318335
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.
摘要翻译：以下公开了用于产生用于测试集成电路的测试图案的方法，装置和系统的代表性实施例。所公开的技术的实施例可以用于提供低功率测试方案，并且可以与各种压缩硬件架构（例如，嵌入式确定性测试（“EDT”）环境）集成。所公开的技术的某些实施例可以在没有硬件修改的情况下降低扫描链中的开关速率，从而降低功耗。其他实施例使用专门的减压硬件和压缩技术来实现低功率测试。

68. 发明申请

US20100229060A1 Compression Based On Deterministic Vector Clustering Of Incompatible Test Cubes 有权
标题翻译：基于不相容性测试立方体的确定性矢量聚类的压缩
公开(公告)号：US20100229060A1
公开(公告)日：2010-09-09
申请号：US12718813
申请日：2010-03-05
申请人： GRZEGORZ MRUGALSKI , Nilanjan Mukherjee , Janusz Rajski , Dariusz Czysz , Jerzy Tyszer
发明人： GRZEGORZ MRUGALSKI , Nilanjan Mukherjee , Janusz Rajski , Dariusz Czysz , Jerzy Tyszer
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31921 , G01R31/318547
摘要： The test data compression scheme is based on deterministic vector clustering. Test cubes that feature many similar specified bits are merged into a parent pattern in the presence of conflicts. The parent pattern along with a control pattern and incremental patterns representing conflicting bits are encoded efficiently. A tri-modal decompressor may be used to decompress the test data.
摘要翻译：测试数据压缩方案基于确定性向量聚类。在存在冲突的情况下，具有许多类似指定位的测试立方体将合并到父模式中。父模式以及表示冲突位的控制模式和增量模式被有效地编码。三模式解压缩器可用于解压缩测试数据。

69. 发明申请

US20090327986A1 GENERATING RESPONSES TO PATTERNS STIMULATING AN ELECTRONIC CIRCUIT WITH TIMING EXCEPTION PATHS 有权
标题翻译：对具有定时异常电位的电子电路刺激模式的响应
公开(公告)号：US20090327986A1
公开(公告)日：2009-12-31
申请号：US12494121
申请日：2009-06-29
申请人： Dhiraj Goswami , Kun-Han Tsai , Mark Kassab , Janusz Rajski
发明人： Dhiraj Goswami , Kun-Han Tsai , Mark Kassab , Janusz Rajski
IPC分类号： G06F17/50
CPC分类号： G01R31/318547 , G01R31/318583
摘要： Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit designs having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing the effect of sensitizing a timing exception path during each time frame associated with a scan pattern. Path sensitization can be determined based on observing whether values injected at starting points of the timing exception paths due to signal transitions and glitches propagate to their end points. The response can be updated by masking the affected end points and propagating unknown values further in the circuit to determine whether they are captured at observation points of the circuit. For instance, the methods and systems described herein may result in reduced unknowns, improved test coverage and test compression.
摘要翻译：可以通过更准确地确定传播到电路中观测点的未知值（其中捕获响应）的具有定时异常路径的电子电路设计来扫描模式（例如，测试模式）的改进的响应。例如，通过分析在与扫描模式相关联的每个时间帧期间对定时异常路径敏感的影响，更准确地确定响应。可以基于观察由于信号转换和毛刺传播到它们的端点而在定时异常路径的起始点处注入的值是否可以确定路径敏化。可以通过在电路中屏蔽受影响的端点和进一步传播未知值来更新响应，以确定它们是否在电路的观测点被捕获。例如，本文描述的方法和系统可以导致未知数减少，改进的测试覆盖和测试压缩。

70. 发明申请

US20090249147A1 FAULT DIAGNOSIS OF COMPRESSED TEST RESPONSES 有权
标题翻译：压力测试反应的故障诊断
公开(公告)号：US20090249147A1
公开(公告)日：2009-10-01
申请号：US12405828
申请日：2009-03-17
申请人： Janusz Rajski , Grzegorz Mrugalski , Artur Pogiel , Jerzy Tyszer , Chen Wang
发明人： Janusz Rajski , Grzegorz Mrugalski , Artur Pogiel , Jerzy Tyszer , Chen Wang
IPC分类号： G01R31/3183 , G06F11/263
CPC分类号： G01R31/318547 , G01R31/31703 , G01R31/318536 , G01R31/318566 , G01R31/318583 , G01R31/31921 , G11C29/40 , G11C29/48 , G11C2029/3202
摘要： Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, at least one error signature comprising multiple bits (including one or more error bits) is received. Plural potential-error-bit-explaining scan cell candidates are evaluated using a search tree. A determination is made as to whether one or more of the evaluated scan cell candidates explain the error bits in the error signature and thereby constitute one or more failing scan cells. An output is provided of any such one or more failing scan cells determined. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Tangible computer-readable media comprising lists of failing scan cells identified by any of the disclosed methods are also provided.
摘要翻译：本文公开了用于诊断来自压缩测试响应的故障扫描单元的方法，装置和系统。例如，在一个非限制性示例性实施例中，接收到包括多个比特（包括一个或多个错误比特）的至少一个错误签名。使用搜索树来评估多个潜在错误位解释扫描单元候选。确定所评估的扫描单元候选中的一个或多个是否解释错误签名中的错误位，从而构成一个或多个故障扫描单元。由确定的任何这样的一个或多个故障扫描单元提供输出。还提供了包括用于使计算机执行任何所公开的方法的计算机可执行指令的有形计算机可读介质。还提供了包括由任何所公开的方法识别的故障扫描单元的列表的有形计算机可读介质。

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