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    • 66. 发明授权
      US07445997B2 Methods of forming non-volatile memory devices having floating gate electrodes 失效
    • Methods of forming non-volatile memory devices having floating gate electrodes
    • 形成具有浮动栅电极的非易失性存储器件的方法
    • US07445997B2
    • 2008-11-04
    • US11103069
    • 2005-04-11
    • Won-Jun Lee , Tae-Hyun Kim , Yong-Sun Ko , Kyung-Hyun Kim , Byoung-Moon Yoon , Ji-Hong Kim
    • Won-Jun Lee , Tae-Hyun Kim , Yong-Sun Ko , Kyung-Hyun Kim , Byoung-Moon Yoon , Ji-Hong Kim
    • H01L21/336
    • H01L27/115 , H01L27/11521
    • Methods of forming non-volatile memory devices include the steps of forming a semiconductor substrate having first and second floating gate electrodes thereon and an electrically insulating region extending between the first and second floating gate electrodes. A step is then performed to etch back the electrically insulating region to expose upper corners of the first and second floating gate electrodes. Another etching step is then performed. This etching step includes exposing upper surfaces and the exposed upper corners of the first and second floating gate electrodes to an etchant that rounds the exposed upper corners of the first and second floating gate electrodes. The step of etching back the electrically insulating region includes etching back the electrically insulating region to expose sidewalls of the first and second floating gate electrodes having heights ranging from about 30 Å to about 200 Å. The step of exposing the upper corners of the first and second floating gate electrodes to an etchant is followed by the step of etching back the electrically insulating region to expose entire sidewalls of the first and second floating gate electrodes.
    • 形成非易失性存储器件的方法包括以下步骤：在其上形成具有第一和第二浮栅的半导体衬底和在第一和第二浮栅之间延伸的电绝缘区。 然后执行步骤以回蚀电绝缘区域以暴露第一和第二浮栅电极的上角。 然后执行另一蚀刻步骤。 该蚀刻步骤包括将第一和第二浮栅电极的上表面和暴露的上角露出到蚀刻剂，该蚀刻剂围绕第一和第二浮栅的暴露的上角。 蚀刻回电绝缘区域的步骤包括蚀刻电绝缘区域以暴露第一和第二浮栅电极的侧壁，其高度范围为约至约200。 将第一和第二浮栅的上角暴露于蚀刻剂的步骤之后是蚀刻电绝缘区以暴露第一和第二浮栅的整个侧壁的步骤。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 68. 发明申请
      US20050266647A1 Method of manufacturing a semiconductor device 失效
    • Method of manufacturing a semiconductor device
    • 制造半导体器件的方法
    • US20050266647A1
    • 2005-12-01
    • US11082616
    • 2005-03-17
    • Tae-hyun Kim , Byoung-moon Yoon , Won-jun Lee , Yong-sun Ko , Kyung-hyun Kim
    • Tae-hyun Kim , Byoung-moon Yoon , Won-jun Lee , Yong-sun Ko , Kyung-hyun Kim
    • H01L21/76 , H01L21/762 , H01L21/8247 , H01L27/115
    • H01L27/11521 , H01L21/76224 , H01L27/115
    • Methods of manufacturing a semiconductor device are provided. A trench is formed in a semiconductor substrate. A first field oxide layer is formed that partially fills the trench. The first field oxide layer defines an active region of the substrate that is adjacent to the trench. An upper portion of sidewalls of the trench extends upward beyond a surface of the first field oxide layer. A first liner is formed on the first field oxide layer and on the portion of the sidewalls of the trench that extend upward beyond the first field oxide layer. A second field oxide layer is formed on the first liner and fills the trench. The second field oxide layer and the first liner are each partially removed to expose a top adjacent surface and upper sidewalls of the trench along the active region of the substrate. A dielectric layer is formed on the exposed top adjacent surface and upper sidewalls of the trench. A gate electrode is formed on the dielectric layer.
    • 提供制造半导体器件的方法。 在半导体衬底中形成沟槽。 形成部分填充沟槽的第一场氧化物层。 第一场氧化物层限定与沟槽相邻的衬底的有源区。 沟槽的侧壁的上部向上延伸超过第一场氧化物层的表面。 第一衬垫形成在第一场氧化物层上并且在沟槽的侧壁的部分上方向上延伸超过第一场氧化物层。 在第一衬垫上形成第二场氧化物层并填充沟槽。 每个部分去除第二场氧化物层和第一衬里以沿着衬底的有源区域暴露沟槽的顶部相邻表面和上侧壁。 介电层形成在沟槽的暴露的顶部相邻表面和上侧壁上。 在电介质层上形成栅电极。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 69. 发明申请
      US20050255654A1 Methods of forming non-volatile memory devices having floating gate electrodes 失效
    • Methods of forming non-volatile memory devices having floating gate electrodes
    • 形成具有浮动栅电极的非易失性存储器件的方法
    • US20050255654A1
    • 2005-11-17
    • US11103069
    • 2005-04-11
    • Won-Jun Lee , Tae-Hyun Kim , Yong-Sun Ko , Kyung-Hyun Kim , Byoung-Moon Yoon , Ji-Hong Kim
    • Won-Jun Lee , Tae-Hyun Kim , Yong-Sun Ko , Kyung-Hyun Kim , Byoung-Moon Yoon , Ji-Hong Kim
    • H01L21/336 , H01L21/8247 , H01L27/115
    • H01L27/115 , H01L27/11521
    • Methods of forming non-volatile memory devices include the steps of forming a semiconductor substrate having first and second floating gate electrodes thereon and an electrically insulating region extending between the first and second floating gate electrodes. A step is then performed to etch back the electrically insulating region to expose upper corners of the first and second floating gate electrodes. Another etching step is then performed. This etching step includes exposing upper surfaces and the exposed upper corners of the first and second floating gate electrodes to an etchant that rounds the exposed upper corners of the first and second floating gate electrodes. The step of etching back the electrically insulating region includes etching back the electrically insulating region to expose sidewalls of the first and second floating gate electrodes having heights ranging from about 30 Å to about 200 Å. The step of exposing the upper corners of the first and second floating gate electrodes to an etchant is followed by the step of etching back the electrically insulating region to expose entire sidewalls of the first and second floating gate electrodes.
    • 形成非易失性存储器件的方法包括以下步骤：在其上形成具有第一和第二浮栅的半导体衬底和在第一和第二浮栅之间延伸的电绝缘区。 然后执行步骤以回蚀电绝缘区域以暴露第一和第二浮栅电极的上角。 然后执行另一蚀刻步骤。 该蚀刻步骤包括将第一和第二浮栅电极的上表面和暴露的上角露出到蚀刻剂，该蚀刻剂围绕第一和第二浮栅的暴露的上角。 蚀刻回电绝缘区域的步骤包括蚀刻电绝缘区域以暴露第一和第二浮栅电极的侧壁，其高度范围为约至约200。 将第一和第二浮栅的上角暴露于蚀刻剂的步骤之后是蚀刻电绝缘区以暴露第一和第二浮栅的整个侧壁的步骤。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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