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51. 发明授权

US5587329A Method for fabricating a switching transistor having a capacitive network proximate a drift region 失效
标题翻译：一种用于制造具有靠近漂移区域的电容网络的开关晶体管的方法
公开(公告)号：US5587329A
公开(公告)日：1996-12-24
申请号：US295374
申请日：1994-08-24
申请人： Fu-Lung Hseuh , Alfred C. Ipri , Gary M. Dolny , Roger G. Stewart
发明人： Fu-Lung Hseuh , Alfred C. Ipri , Gary M. Dolny , Roger G. Stewart
IPC分类号： H01L29/786 , G09G3/30 , H01L27/088 , H01L27/12 , H01L21/786
CPC分类号： H01L27/1203 , G09G3/30 , H01L27/088 , H01L27/12 , G09G2300/0842
摘要： In an active matrix electroluminescent display, a pixel containing a grounded conductive electric field shield between an EL cell and the switching electronics for the EL cell. In a method of fabricating the pixel, first, an EL cell switching circuit is formed, then an insulating layer is formed over the switching circuit and a conductive layer (the field shield) is formed over the insulating layer. A through hole is provided in the field shield such that an electrical connection can be made between the switching circuit and an EL cell. The EL cell is then conventionally formed on top of the shield layer. Consequently, the shield isolates the switching circuit from the EL cell and ensures that any electric fields produced in the EL cell do not interfere with the operation of the switching electronics. Furthermore, the switching circuitry for each cell contains two transistors; a low voltage MOS transistor and a high voltage MOS transistor. The low voltage transistor is controlled by signals on a data and a select line. When activated, the low voltage transistor activates the high voltage transistor by charging the gate of the high voltage transistor. This gate charge is stored between the gate electrode of the high voltage transistor and the electric field shield. Additionally, to improve the breakdown voltage of the high voltage transistor, a capacitive divider network is fabricated proximate the drift region of that transistor. As such, the network uniformly distributes an electric field over the drift region.
摘要翻译：在有源矩阵电致发光显示器中，包含EL单元和用于EL单元的开关电子器件之间的接地导电电场屏蔽的像素。在制造像素的方法中，首先，形成EL单元切换电路，然后在开关电路上形成绝缘层，并且在绝缘层上形成导电层（场屏蔽）。在屏蔽层中设置通孔，使得可以在开关电路和EL单元之间形成电连接。然后通常将EL电池形成在屏蔽层的顶部。因此，屏蔽将开关电路与EL单元隔离，并确保在EL单元中产生的任何电场不会干扰开关电子器件的操作。此外，每个单元的开关电路包含两个晶体管; 低压MOS晶体管和高压MOS晶体管。低电压晶体管由数据和选择线上的信号控制。当激活时，低压晶体管通过对高电压晶体管的栅极充电来激活高电压晶体管。该栅极电荷存储在高电压晶体管的栅电极和电场屏蔽之间。另外，为了提高高压晶体管的击穿电压，在该晶体管的漂移区附近制造电容分压网络。这样，网络在漂移区域上均匀地分布电场。

52. 发明授权

US5496749A Method of manufacturing thin film transistors in a liquid crystal display apparatus 失效
标题翻译：在液晶显示装置中制造薄膜晶体管的方法
公开(公告)号：US5496749A
公开(公告)日：1996-03-05
申请号：US456836
申请日：1995-06-01
申请人： Yasuhiro Nasu , Teruhiko Ichimura , Tomotaka Matsumoto
发明人： Yasuhiro Nasu , Teruhiko Ichimura , Tomotaka Matsumoto
IPC分类号： G02F1/1343 , G02F1/136 , G02F1/1368 , H01L21/22 , H01L21/223 , H01L21/336 , H01L21/77 , H01L21/84 , H01L29/78 , H01L29/786 , H01L21/786
CPC分类号： H01L29/78696 , H01L21/2236 , H01L27/1214 , H01L29/66757 , G02F1/1368 , Y10S148/15
摘要： A first sheet of photomask is used when a gate electrode and a gate bus line are formed, a second sheet of photomask is used when patterning is applied to a semiconductor film which becomes an active layer of a transistor on the gate electrode, a third sheet of photomask is used when a pixel electrode, a source electrode, a drain electrode, a drain bus line and a drain bus terminal portion are formed, and a fourth sheet of photomask is used when a film on the drain bus terminal portion, the gate bus terminal .portion and pixel portion is removed, thereby to form thin film transistors arranged in a matrix form.
摘要翻译：当形成栅电极和栅极总线时，使用第一片光掩模，当在栅电极上成为晶体管的有源层的半导体膜上进行构图时，使用第二片光掩模，第三片当形成像素电极，源电极，漏电极，漏极总线和漏极总线端子部分时使用光掩模，并且当漏极总线端子部分上的膜，栅极总线端子部分和像素部分被去除，从而形成以矩阵形式布置的薄膜晶体管。

53. 发明授权

US5424230A Method of manufacturing a polysilicon thin film transistor 失效
标题翻译：制造多晶硅薄膜晶体管的方法
公开(公告)号：US5424230A
公开(公告)日：1995-06-13
申请号：US283250
申请日：1994-07-29
申请人： Haruo Wakai
发明人： Haruo Wakai
IPC分类号： H01L21/20 , H01L21/336 , H01L29/786 , H01L21/786
CPC分类号： H01L29/66765 , H01L21/2022 , H01L29/78618 , H01L29/78621 , Y10S148/09 , Y10S148/15
摘要： An amorphous silicon hydride thin film is deposited on an insulating body by a plasma CVD method, and is then heated for dehydrogenating the amorphous silicon thin film so that a dehydrogenated amorphous silicon thin film containing hydrogen of 3 atomic % or less is formed. The insulating body may be an insulating substrate (such as a glass substrate) alone, or a combination of an insulating substrate with an intermediate insulating base layer thereon. Impurity ions are injected into the dehydrogenated amorphous silicon hydride thin film to form source and drain regions. Excimer laser beams are applied to the dehydrogenated amorphous silicon thin film, thereby polycrystallizing the amorphous silicon thin film into a polysilicon thin film and activating the injected impurity ions.
摘要翻译：通过等离子体CVD法将非晶硅氢化物薄膜沉积在绝缘体上，然后被加热以使非晶硅薄膜脱氢，从而形成含有3原子％以下的氢的脱氢非晶硅薄膜。绝缘体可以是单独的绝缘基板（例如玻璃基板），也可以是其上具有中间绝缘基底层的绝缘基板的组合。将杂质离子注入到脱氢的非晶硅氢化物薄膜中以形成源区和漏区。将准分子激光束施加到脱氢的非晶硅薄膜上，从而将非晶硅薄膜多晶化为多晶硅薄膜并激活注入的杂质离子。

54. 发明公开

US20240266221A1 PROCESSING METHOD OF WORKPIECE 审中-公开
公开(公告)号：US20240266221A1
公开(公告)日：2024-08-08
申请号：US18426513
申请日：2024-01-30
申请人： DISCO CORPORATION
发明人： Jinyan ZHAO , Shigenori HARADA
IPC分类号： H01L21/786 , H01L21/67
CPC分类号： H01L21/786 , H01L21/67092 , H01L2221/68309
摘要： A processing method of a workpiece includes a division step of dividing into a plurality of chips the workpiece held on a first surface of a sheet, a tightly bonding step of, after the division step, heating at least either the sheet or the workpiece to soften the sheet and tightly bonding the sheet to the chips, and a cleaning step of, after the tightly bonding step, cleaning the workpiece.

55. 发明申请

US20230115122A1 METHOD OF BONDING THIN SUBSTRATES 有权
公开(公告)号：US20230115122A1
公开(公告)日：2023-04-13
申请号：US17931826
申请日：2022-09-13
申请人： ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
发明人： Cyprian Emeka Uzoh , Thomas Workman , Gabriel Z. Guevara , Dominik Suwito , Guilian Gao
IPC分类号： H01L21/762 , H01L21/786 , H01L21/321 , H01L21/02
摘要： Methods of bonding thin dies to substrates. In one such method, a wafer is attached to a support layer. The wafer and support layer are attached to a dicing structure and then singulated to form a plurality of semiconductor die components. Each semiconductor die component comprises a thinned die and a support layer section attached to the thinned die where each support layer section is disposed between the corresponding thinned die and the dicing structure. At least one of the semiconductor die components is then bonded to a substrate without an intervening adhesive such that the thinned die is disposed between the substrate and the support layer section. The support layer section is then removed from the thinned die.

56. 发明授权

US11515212B2 Method of manufacturing semiconductor devices having controlled S/D epitaxial shape 有权
公开(公告)号：US11515212B2
公开(公告)日：2022-11-29
申请号：US16938875
申请日：2020-07-24
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Te-An Chen , Meng-Han Lin
IPC分类号： H01L21/8234 , H01L27/092 , H01L29/08 , H01L29/78 , H01L29/423 , H01L29/06 , H01L29/66 , H01L29/775 , H01L21/8238 , H01L21/786 , H01L21/28 , H01L27/088
摘要： In a method of manufacturing a semiconductor device, an isolation structure is formed in a substrate defining an active region, a first gate structure is formed over the isolation structure and a second gate structure over the active region adjacent to the first gate structure, a cover layer is formed to cover the first gate structure and a part of the active region between the first gate structure and the second gate structure, the active region between the first gate structure and the second gate structure not covered by the cover layer is etched to form a recess, and an epitaxial semiconductor layer is formed in the recess.

57. 发明授权

US11495529B2 SOI substrate and related methods 有权
公开(公告)号：US11495529B2
公开(公告)日：2022-11-08
申请号：US16929378
申请日：2020-07-15
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Mark Griswold , Michael J. Seddon
IPC分类号： H01L21/78 , H01L23/522 , H01L23/34 , H01L21/786 , H01L21/02 , H01L23/12
摘要： Implementations of a silicon-on-insulator (SOI) die may include a silicon layer including a first side and a second side, and an insulative layer coupled directly to the second side of the silicon layer. The insulative layer may not be coupled to any other silicon layer.

58. 发明申请

US20220270925A1 FLEXING SEMICONDUCTOR STRUCTURES AND RELATED TECHNIQUES 有权
公开(公告)号：US20220270925A1
公开(公告)日：2022-08-25
申请号：US17628374
申请日：2020-07-22
申请人： Massachusetts Institute of Technology
发明人： Vladimir BULOVIC , Ryan ZIMMERMAN
IPC分类号： H01L21/786 , B23K26/364 , H01L21/56 , H01L21/67 , H01L23/31
摘要： Aspects include a method of fabricating a semiconductor structure including providing a semiconductor layer, scribing the semiconductor layer to provide one or more scribe lines, disposing a flexible support layer on the semiconductor layer, and applying a force to the scribed semiconductor layer so as to induce cracks along the scribe lines.

59. 发明授权

US11201386B2 Semiconductor device package and method for manufacturing the same 有权
公开(公告)号：US11201386B2
公开(公告)日：2021-12-14
申请号：US16670487
申请日：2019-10-31
申请人： Advanced Semiconductor Engineering, Inc.
发明人： Cheng-Lin Ho , Chih-Cheng Lee , Chun Chen Chen , Yuanhao Yu
IPC分类号： H01L23/495 , H01L21/786 , H01Q1/22 , H01L23/28 , H01L21/768 , H01L23/66
摘要： A semiconductor device package and a method for manufacturing the same are provided. The semiconductor device package includes a circuit layer and an antenna module. The circuit layer has a first surface, a second surface opposite to the first surface and a lateral surface. The lateral surface extends between the first surface and the second surface. The circuit layer has an interconnection structure. The antenna module has an antenna pattern layer and is disposed on the first surface of the circuit layer. The lateral surface of the circuit layer is substantially coplanar with a lateral surface of the antenna module.

60. 发明申请

US20200335478A1 Semiconductor Device and Method of Forming Embedded Wafer Level Chip Scale Packages 审中-公开
公开(公告)号：US20200335478A1
公开(公告)日：2020-10-22
申请号：US16918281
申请日：2020-07-01
申请人： STATS ChipPAC Pte. Ltd.
发明人： Yaojian Lin , Pandi C. Marimuthu , Il Kwon Shim , Byung Joon Han
IPC分类号： H01L23/00 , H01L23/31 , H01L21/56 , H01L21/786 , H01L21/784 , H01L21/782 , H01L21/82 , H01L21/78
摘要： A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (μm) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 μm or less.

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