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51. 发明授权

US08891966B2 Optical communication device and signal adjusting method 有权
标题翻译：光通信设备和信号调节方法
公开(公告)号：US08891966B2
公开(公告)日：2014-11-18
申请号：US13448902
申请日：2012-04-17
申请人： Tatsuya Toyozumi , Koji Matsunaga , Yasuo Tanaka , Hironobu Fukuura , Wataru Kawasaki , Shota Mori
发明人： Tatsuya Toyozumi , Koji Matsunaga , Yasuo Tanaka , Hironobu Fukuura , Wataru Kawasaki , Shota Mori
IPC分类号： H04J14/00 , H04Q11/08
CPC分类号： H04Q11/08 , H04Q11/0005 , H04Q2011/002 , H04Q2011/0039 , H04Q2011/0045 , H04Q2213/1301
摘要： An optical packet switching device causes branching of an optical packet that is input to an optical switch and detects a synchronization pattern having a predetermined number of bits from the branched optical packet. Then, the optical packet switching device calculates a synchronization point indicating a location of the synchronization pattern with respect to a detection timing and controls, in accordance with the calculated synchronization point, a delay amount of a delay element that delays an optical packet ON signal that is output to the optical switch.
摘要翻译：光分组交换装置使得输入到光开关的光分组的分支，从分支的光分组中检测出具有预定比特数的同步模式。然后，光分组交换装置计算表示相对于检测定时的同步模式的位置的同步点，并根据计算出的同步点，控制延迟光分组开启信号的延迟元件的延迟量，被输出到光开关。

52. 发明授权

US07023844B2 Scalable switching fabric 失效
公开(公告)号：US07023844B2
公开(公告)日：2006-04-04
申请号：US10423101
申请日：2003-04-25
申请人： Gilbert Wolrich , Matthew J. Adiletta , John Cyr
发明人： Gilbert Wolrich , Matthew J. Adiletta , John Cyr
IPC分类号： H04L12/50 , H04L12/56 , H04Q11/08
CPC分类号： H04L49/10 , H04L49/101 , H04L49/254 , H04L49/3045 , H04L49/45
摘要： A switch fabric includes a first plurality of data switches each having a plurality of input ports and a plurality of output ports the plurality of switches capable of switching any of its input ports to any of its output ports with the plurality of data switches having inputs coupled to a plurality of input buses so that a first byte of a first one of the input buses is coupled to a first one of the plurality of switches, and a succeeding byte of the first input bus is coupled to a succeeding one of the plurality of switches.

53. 发明授权

US06898199B1 Architecture for providing flexible, programmable supplementary services in an expandable telecommunications system 失效
标题翻译：用于在可扩展电信系统中提供灵活，可编程的补充业务的架构
公开(公告)号：US06898199B1
公开(公告)日：2005-05-24
申请号：US09272636
申请日：1999-03-18
申请人： Michael C. Silva , Mark P. Hebert
发明人： Michael C. Silva , Mark P. Hebert
IPC分类号： H04Q3/00 , H04Q3/545 , H04L12/56 , H04Q11/08
CPC分类号： H04Q3/0054 , H04Q3/54525 , H04Q2213/1305 , H04Q2213/13103 , H04Q2213/13109 , H04Q2213/13349 , H04Q2213/1338
摘要： This invention relates to a supplementary services layer (SSL) application in the switching node for the development and execution of subscriber-based supplementary services. The SSL communicates with the L4 application through an L4-L5 interface. Therefore, a system operator may configure the switching node to execute supplementary services without intervention from a host application and without modification to the current L4 application. The SSL also communicates with the L5 application in order for that application to integrate supplementary services without further modifications. The SSL comprises a Database Interface Service, a Service Object Manager (SOM) and one or more instances of a Supplementary Service Object (SSO). The database interface service provides connection to an external database which stores each subscriber's profile. Each SSO instance implements one or more supplementary services for a call. The SOM exercises overall control over these SSO instances.
摘要翻译：本发明涉及用于开发和执行基于用户的补充业务的交换节点中的补充业务层（SSL）应用。 SSL通过L4-L5接口与L4应用程序进行通信。因此，系统操作者可以将交换节点配置为执行辅助服务，而无需来自主机应用的干预，而不修改当前的L4应用。 SSL还与L5应用程序通信，以便该应用程序集成补充服务，无需进一步修改。 SSL包括数据库接口服务，服务对象管理器（SOM）和辅助服务对象（SSO）的一个或多个实例。数据库接口服务提供与存储每个用户简档的外部数据库的连接。每个SSO实例都实现一个或多个用于呼叫的补充业务。 SOM对这些SSO实例进行整体控制。

54. 发明授权

US06879603B1 Processor-based voice and data time slot interchange system 有权
标题翻译：基于处理器的语音和数据时隙交换系统
公开(公告)号：US06879603B1
公开(公告)日：2005-04-12
申请号：US09493312
申请日：2000-01-28
申请人： Roger L. Koenig , Tim P. Groth , Matthew D. Morris , James Michael Dougherty , Gordon K. Francis
发明人： Roger L. Koenig , Tim P. Groth , Matthew D. Morris , James Michael Dougherty , Gordon K. Francis
IPC分类号： H04Q11/08 , H04J3/02 , H04L12/50 , H04Q11/00
CPC分类号： H04Q11/08 , H04Q2213/1305 , H04Q2213/13106 , H04Q2213/13107 , H04Q2213/13216 , H04Q2213/13292 , H04Q2213/13299 , H04Q2213/1332 , H04Q2213/13322 , H04Q2213/1334 , H04Q2213/1336 , H04Q2213/13361 , H04Q2213/13362 , H04Q2213/13393 , H04Q2213/13396
摘要： A technique for performing a time slot interchange in a processor. The TSI process is surrounded by a multiplexing/demultiplexing circuit for converting a plurality of PCM highways into a single input serial data stream. The mux/demux circuit includes elastic stores to align frames and shift resisters to mux/demux with a minimum of delay. The TSI processor includes an input and an output buffered series port, a pair of input buffers, one to receive even-numbered frames from the PCM highways and one to receive odd-numbered frames, and an output buffer. Data is read from the appropriate input buffer in a non-sequential fashion as commanded by the processor in accordance with information stored in connection arrays (address buffers). The data is then written to the output buffer sequentially. The timing of the reading and writing steps is optimized relative to free running buffered serial port pointers for each BSP to reduce the frame delay.
摘要翻译：一种用于在处理器中执行时隙交换的技术。 TSI处理被用于将多个PCM高速公路转换成单个输入串行数据流的复用/解复用电路包围。多路复用/解复用电路包括弹性存储器，用于对准框架并且以最小的延迟将移位寄存器复用到多路复用器/解复用器。 TSI处理器包括输入和输出缓冲串行端口，一对输入缓冲器，一个从PCM高速公路接收偶数帧，一个接收奇数帧，一个输出缓冲器。根据存储在连接阵列（地址缓冲器）中的信息，处理器按照非顺序方式从适当的输入缓冲器读取数据。然后将数据顺序写入输出缓冲器。阅读和写入步骤的时序相对于每个BSP的免费运行缓冲串行端口指针进行优化，以减少帧延迟。

55. 发明授权

US5592479A Time switching device having identical frame delay and a method thereof in a full-electronic exchange 失效
标题翻译：具有相同帧延迟的时间切换装置及其全电子交换中的方法
公开(公告)号：US5592479A
公开(公告)日：1997-01-07
申请号：US454864
申请日：1995-05-31
申请人： Jung S. Jung , Bae H. Kim
发明人： Jung S. Jung , Bae H. Kim
IPC分类号： H04Q11/08
CPC分类号： H04Q11/08 , H01L2924/1423
摘要： A time switching device and method having identical frame delay in a full-electronic exchange allows respective channels to have identical frame delay after switching multichannel in the full-electronic exchange by using only one time memory within the time switching device for providing data service of channel capacity larger than 64[Kbps], in which a time memory having a capacity four times larger than time switch capacity is divided into four areas to maintain a difference between the memory write and read operations by at least one frame period (125 .mu.s), thereby simplifying the structure of the time switching device and occupying a small area of a printed circuit board to accomplish small-sized system while decreasing the number of components required for constructing the system, thereby reducing system construction cost.
摘要翻译：在全电子交换中具有相同帧延迟的时间切换装置和方法允许相应的信道在全电子交换中切换多信道之后具有相同的帧延迟，只在时间切换装置内仅使用一个时间存储器来提供信道的数据业务具有大于64 [Kbps]的容量，其中具有四倍于时间开关容量的容量的时间存储器被分成四个区域，以将存储器写入和读取操作之间的差异保持至少一个帧周期（125μs）从而简化了时间切换装置的结构，占据了印刷电路板的小面积以实现小型系统，同时减少了构建系统所需的部件数量，从而降低了系统构造成本。

56. 发明授权

US5521920A Time-division multiplexer with reduced delay time 失效
标题翻译：时分多路复用器具有延迟时间缩短
公开(公告)号：US5521920A
公开(公告)日：1996-05-28
申请号：US354782
申请日：1994-12-12
申请人： Yoshiaki Nagase
发明人： Yoshiaki Nagase
IPC分类号： H04J3/08 , H04J3/06 , H04J3/16 , H04Q11/08 , H04J3/02
CPC分类号： H04J3/1641 , H04J3/0626 , H04Q11/08
摘要： A multiplexer having the capability of multiplexing/demultiplexing data with reduced delay caused by exchanging data. The time-division multiplexer of the invention includes a plurality of time-slot-conversion memories which can write/read the data consisting of specific multi-frames with a specific frame unit, a write-timing pulse generator which generates write/read timing to a multi-frame alignment memory with a specific frame unit. The multiplexer transmits/receives the data to/from the transmission interface or the terminal interface with the specific frame unit. Another kind of multiplexer of the invention includes a distributed time-slot-conversion memory which can write/read the data with a specific frame unit and a selector. The multiplexer transmits/receives the data to/from the transmission interface, the terminal interface, the transmission line, or the terminal with a specific frame unit.
摘要翻译：一种多路复用器具有通过交换数据导致的具有减少的延迟的数据的复用/解复用能力的能力。本发明的时分多路复用器包括多个时隙转换存储器，其可以用特定帧单元写入/读取由特定多帧组成的数据;写定时脉冲发生器，其产生写入/读取定时具有特定帧单元的多帧对准存储器。多路复用器发送/接收来自传输接口或具有特定帧单元的终端接口的数据。本发明的另一种多路复用器包括可以用特定帧单元和选择器来写入/读取数据的分布式时隙转换存储器。多路复用器向传输接口，终端接口，传输线或具有特定帧单元的终端发送/接收数据。

57. 发明授权

US5521919A Method and apparatus for providing switch-based features 失效
标题翻译：用于提供基于开关的特征的方法和装置
公开(公告)号：US5521919A
公开(公告)日：1996-05-28
申请号：US334308
申请日：1994-11-04
申请人： Thomas W. Anderson , Thomas E. Bowers , Charles C. Byers
发明人： Thomas W. Anderson , Thomas E. Bowers , Charles C. Byers
IPC分类号： H04M3/00 , H04M3/40 , H04Q11/04 , H04Q11/08
CPC分类号： H04M3/002 , H04M3/40 , H04Q11/04
摘要： A system and method to provide voice enhancement circuits on a voice path on an individual basis, without having in-line circuits inserted into the lines or trunks. The enhancement circuit is inserted within one or more of the switches. This system comprises a switching system having a switching fabric and a central control, wherein the switching fabric includes several extended time slot interchange (XTSI) units connected to a time multiplex switch. The extended time slot interchange unit has approximately twice the capacity of a standard time slot interchange unit. Such XTSI is connected to voice enhancing circuits, which the TSI may then switch enhancement circuits into a call path. A method of setting up a call according to this invention includes routing the call to a switch, routing the call in the switch into an XTSI, which routes a call through the enhancement circuit, and then back through the XTSI.
摘要翻译：在单独的语音路径上提供语音增强电路的系统和方法，而不会将线内电路插入到线路或中继线中。增强电路插入在一个或多个开关内。该系统包括具有交换结构和中央控制的交换系统，其中交换结构包括连接到时间复用交换机的几个扩展时隙交换（XTSI）单元。扩展时隙交换单元具有标准时隙交换单元容量的大约两倍。这样的XTSI连接到语音增强电路，TSI然后可以将增强电路切换成呼叫路径。根据本发明的建立呼叫的方法包括将呼叫路由到交换机，将交换机中的呼叫路由到XTSI，其通过增强电路路由呼叫，然后通过XTSI返回。

58. 发明授权

US5509005A Power saving time slot interchanger with random read/write cycles 失效
标题翻译：省电时隙交换器，具有随机读/写周期
公开(公告)号：US5509005A
公开(公告)日：1996-04-16
申请号：US315484
申请日：1994-09-30
申请人： Mamoru Nagamoto
发明人： Mamoru Nagamoto
IPC分类号： H04Q11/04 , H04Q11/08 , H04L12/52
CPC分类号： H04Q11/08
摘要： In a switching system of multiple time slot interchangers associated with outlet ports, each interchanger includes multiple data memories respectively connected to inlet ports and connected to the outlet port with which the interchanger is associated. A set of commands is established for each incoming data signal. The command set includes an inlet port number (IPN), an incoming slot number (ISN), an outlet port number (OPN), and an outgoing slot number (OSN). During a write cycle, one of the inlet ports is selected in accordance with the IPN command and one of the data memories which are associated with the selected inlet port is selected in accordance with the OPN command. The selected data memory is caused to store the data signal of an incoming time slot identified by the stored ISN command into one of its storage locations identified by the stored ISN command. During a subsequent read cycle, one of the outlet ports is selected in accordance with the OPN command and one of the data memories which are associated with the selected outlet port is selected in accordance with the stored IPN command. The selected data memory is caused to read a data signal from one of its storage locations identified by the ISN command onto an outgoing time slot identified by the OSN command.
摘要翻译：在与出口相关联的多个时隙交换器的交换系统中，每个交换器包括分别连接到入口端口并连接到与交换器相关联的出口的多个数据存储器。为每个输入数据信号建立一组命令。命令集包括入口端口号（IPN），输入插槽号（ISN），插座端口号（OPN）和输出插槽号（OSN）。在写周期期间，根据IPN命令选择一个入口端口，并且根据OPN命令选择与所选入口端口相关联的一个数据存储器。使选择的数据存储器将由存储的ISN命令识别的进入时隙的数据信号存储到由存储的ISN命令标识的其中一个存储位置。在随后的读取周期期间，根据OPN命令选择一个出口端口，并且根据所存储的IPN命令来选择与所选出口相关联的一个数据存储器。使选择的数据存储器从由ISN命令识别的其中一个存储位置读取到由OSN命令标识的输出时隙上的数据信号。

59. 发明授权

US5467340A Time division switch 失效
标题翻译：时分开关
公开(公告)号：US5467340A
公开(公告)日：1995-11-14
申请号：US180913
申请日：1994-01-12
申请人： Akira Umezu
发明人： Akira Umezu
IPC分类号： H04Q3/52 , H04Q11/04 , H04Q11/08 , H04L12/26
CPC分类号： H04M3/303 , H04Q11/08
摘要： A time division switch for digital exchange systems that includes speech data storage device to store digitally coded speech data transmitted on the data highway, control data storage device to store control data for control of input/output of speech data at the speech data storage device, address generation device to generate sequential addresses to read/write data for said speech data storage device and said control data storage device, write device to write data to said speech data storage device according to the sequential addresses generated by said address generation device, read device to read data from said speech data storage device according to the control data stored in said control data storage device and test execution device to switch between normal mode for processing of said speech data and test mode to check for any failure in said speech data storage device and said control data storage device.
摘要翻译：一种用于数字交换系统的时分交换机，包括用于存储在数据高速公路上发送的数字编码语音数据的语音数据存储装置，控制数据存储装置，用于存储用于在语音数据存储装置处控制语音数据的输入/输出的控制数据，地址产生装置，用于产生用于所述语音数据存储装置和所述控制数据存储装置的读/写数据的顺序地址，写装置，以根据由所述地址产生装置生成的顺序地址将数据写入所述语音数据存储装置，读装置根据存储在所述控制数据存储装置中的控制数据和测试执行装置从所述语音数据存储装置读取数据，以便在用于处理所述语音数据的正常模式和测试模式之间切换以检查所述语音数据存储装置中的任何故障和所述控制数据存储装置。

60. 发明授权

US5420855A Multi-port time switch element 失效
标题翻译：多端口时间开关元件
公开(公告)号：US5420855A
公开(公告)日：1995-05-30
申请号：US185753
申请日：1994-01-21
申请人： Akio Morimoto , Hiroshi Nakaide
发明人： Akio Morimoto , Hiroshi Nakaide
IPC分类号： H03K17/00 , H04Q3/52 , H04Q11/08 , H04Q11/04
CPC分类号： H04Q11/08
摘要： A multi-port time switch element for cross-connecting an n-channel multiplexed data includes m input ports for receiving m n-channel multiplexed data, a memory part for alternately writing and reading the n-channel multiplexed data, m selectors for writing and reading the n-channel multiplexed data so that each of the m selectors receives m.times.n data read from the memory part and selects one of the m.times.n data n times in an arbitrary sequence to output an n-channel multiplexed data, and m output ports for outputting the m n-channel multiplexed data read from the m selectors.
摘要翻译：用于交叉连接n信道复用数据的多端口时间切换元件包括用于接收m n信道复用数据的m个输入端口，用于交替写入和读取n信道复用数据的存储器部分，用于写入的m个选择器和读取n信道多路复用数据，使得m个选择器中的每一个接收从存储器部分读取的m×n数据，并以任意顺序选择m×n个数据n次，以输出n信道复用数据，并输出m个输出端口从m个选择器读取的m个信道复用数据。

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