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51. 发明申请

US20130091339A1 SIMD Memory Circuit And Methodology To Support Upsampling, Downsampling And Transposition 有权
标题翻译： SIMD存储器电路和方法来支持采样，下采样和转置
公开(公告)号：US20130091339A1
公开(公告)日：2013-04-11
申请号：US13253754
申请日：2011-10-05
申请人： David Van Kampen , Kees Van Berkel , Sven Goossens , Wim Kloosterhuis , Claudiu Zissulescu-Ianculescu
发明人： David Van Kampen , Kees Van Berkel , Sven Goossens , Wim Kloosterhuis , Claudiu Zissulescu-Ianculescu
IPC分类号： G06F9/312 , G06F9/315 , G06F9/302 , G06F9/38 , G06F15/76 , G06F9/305
CPC分类号： G06F7/785 , H03H17/0261 , H03H17/0621 , H03H2017/0298
摘要： An apparatus and method for creation of reordered vectors from sequential input data for block based decimation, filtering, interpolation and matrix transposition using a memory circuit for a Single Instruction, Multiple Data (SIMD) Digital Signal Processor (DSP). This memory circuit includes a two-dimensional storage array, a rotate-and-distribute unit, a read-controller and a write to controller, to map input vectors containing sequential data elements in columns of the two-dimensional array and extract reordered target vectors from this array. The data elements and memory configuration are received from the SIMD DSP.
摘要翻译：一种用于使用用于单指令，多数据（SIMD）数字信号处理器（DSP）的存储器电路的基于块的抽取，滤波，插值和矩阵转置的顺序输入数据创建重新排序的向量的装置和方法。该存储器电路包括二维存储阵列，旋转分配单元，读取控制器和写入控制器，以在二维阵列的列中映射包含顺序数据元素的输入向量，并提取重新排序的目标矢量从这个数组。从SIMD DSP接收数据元素和存储器配置。

52. 发明授权

US07714750B2 Audio processing circuit and method 有权
标题翻译：音频处理电路及方法
公开(公告)号：US07714750B2
公开(公告)日：2010-05-11
申请号：US11612113
申请日：2006-12-18
申请人： Zhi-Ren Chang , Shin-Ing Hsieh , Kuo-Feng Hsu , Chi-Han Lan , Horng-Der Chang
发明人： Zhi-Ren Chang , Shin-Ing Hsieh , Kuo-Feng Hsu , Chi-Han Lan , Horng-Der Chang
IPC分类号： H03M7/00
CPC分类号： H03H17/0621
摘要： An audio processing circuit includes a clock synthesizer, a clock divider, a digital interpolator module, a sampling rate converter and a digital-to-analog converter. The clock synthesizer generates a base clock signal according to a sampling clock signal and a first reference clock signal. The clock divider generates a multiple frequency clock signal according to the base clock signal. The digital interpolator module interpolates a digital audio data according to the multiple frequency clock signal. The sampling rate converter processes the interpolated digital audio data into a re-sampled digital audio data according to the multiple frequency clock signal and a second reference clock signal. The digital-to-analog converter is coupled to the sampling rate converter for converting the re-sampled digital audio data into an analog audio signal according to the second reference clock signal.
摘要翻译：音频处理电路包括时钟合成器，时钟分频器，数字内插器模块，采样率转换器和数模转换器。时钟合成器根据采样时钟信号和第一参考时钟信号产生基本时钟信号。时钟分频器根据基本时钟信号产生多频时钟信号。数字插值器模块根据多频时钟信号内插数字音频数据。采样率转换器根据多频时钟信号和第二参考时钟信号将内插的数字音频数据处理成重新采样的数字音频数据。数模转换器耦合到采样率转换器，用于根据第二参考时钟信号将重新采样的数字音频数据转换为模拟音频信号。

53. 发明授权

US07688923B2 Enhanced data rate receiver 有权
标题翻译：增强数据速率接收机
公开(公告)号：US07688923B2
公开(公告)日：2010-03-30
申请号：US11503415
申请日：2006-08-11
申请人： Pietro Capretta
发明人： Pietro Capretta
IPC分类号： H04B1/10
CPC分类号： H03H17/0621 , H03H17/0685
摘要： A receiver having circuitry for generating first digitized samples from a received analog signal at a first sampling rate, e.g. an ADC. An interpolating filter is used to generate second digitized samples which are estimates of samples obtainable by sampling the received analog signal at a second sample rate lower than the first sampling rate, second digitized samples being output at the first sampling rate and including at least one unusable sample. A circuit is provided for generating a signal for controlling components of the receive path downstream of the interpolation filter to prevent processing of the unusable second digitized samples.
摘要翻译：一种接收机，具有用于以第一采样率从接收的模拟信号产生第一数字化采样的电路，例如，一个ADC。内插滤波器用于产生第二数字化采样，其是通过以低于第一采样率的第二采样率对接收的模拟信号进行采样而获得的采样的估计，第二数字化样本以第一采样率输出并且包括至少一个不可用样品。提供电路，用于产生用于控制内插滤波器下游的接收路径的分量的信号，以防止不可用的第二数字化采样的处理。

54. 发明申请

US20090070395A1 INTERPOLATION FUNCTION GENERATION CIRCUIT 审中-公开
标题翻译：插值函数生成电路
公开(公告)号：US20090070395A1
公开(公告)日：2009-03-12
申请号：US12281722
申请日：2007-03-05
申请人： Yukio Koyanagi
发明人： Yukio Koyanagi
IPC分类号： G06F17/17
CPC分类号： H03H17/0621 , G06F17/17 , G06T3/4007
摘要： An interpolation function generation circuit is formed by cascade connecting a first FIR filter (10) having a numerical value string composed of a ratio “−α, α, β, β, α, −α” (α is an emphasis coefficient and β is a fixed value) as a filter coefficient and a second FIR filter (20) having a numerical value string composed of a ratio “1, 3, 5, . . . , m−1, m−1, . . . , 5, 3, 1” when the tap length is an odd number and “1, 3, 5, . . . , n−2, n−1, n−2, . . . , 5, 3, 1” if the tap length is an odd number (m and n are multiples of the oversampling). With only the two FIR filter (10, 20), it is possible to easily realize an interpolation function having a variable emphasis.
摘要翻译：通过级联连接具有由“α，α，β，β，α，α”组成的数值串的第一FIR滤波器（10）形成插值函数产生电路（α是强调系数，β是作为滤波器系数的固定值）和具有由比例“1,3,5 ...，m-1，m-1，...，5”组成的数值串的第二FIR滤波器（20） 3,1“，当抽头长度为奇数时，如果抽头长度为1，3，5，...，n-2，n-1，n-2，...，5，3，1 是奇数（m和n是过采样的倍数）。仅使用两个FIR滤波器（10,20），可以容易地实现具有可变强调的插值功能。

55. 发明申请

US20080288094A1 Auto Signal Output Device 有权
标题翻译：自动信号输出设备
公开(公告)号：US20080288094A1
公开(公告)日：2008-11-20
申请号：US11658183
申请日：2005-03-10
申请人： Mitsugi Fukushima
发明人： Mitsugi Fukushima
IPC分类号： G06F17/00
CPC分类号： H03H17/0621 , G10L21/038 , G11B20/10009 , G11B20/10527 , G11B2020/10546 , G11B2020/10564 , G11B2020/10583 , H03H17/028 , H03H17/0294 , H03M1/661
摘要： The present invention relates to an audio signal output device for outputting based on a digital audio signal. A judging unit judges the frequency of reversals in polarity of the digital audio signal. A selecting unit switches an output of the audio signal output device between an output based on a first interpolated digital audio signal obtained by interpolating the digital audio signal by way of a first interpolation processing and another output based on a second interpolated digital audio signal obtained by interpolating the digital audio signal by way of a second interpolation processing in response to a judgment result made by the judging unit.
摘要翻译：本发明涉及一种用于基于数字音频信号输出的音频信号输出装置。判断单元判断数字音频信号的极性反转频率。选择单元基于通过第一内插处理内插数字音频信号而获得的第一内插数字音频信号和基于由第二内插数字音频信号获得的第二内插数字音频信号的另一输出而在输出之间切换音频信号输出装置的输出响应于由判断单元作出的判断结果，通过第二内插处理内插数字音频信号。

56. 发明申请

US20080240220A1 DIGITAL FILTER AND METHOD FOR FILTERING 审中-公开
标题翻译：数字滤波器和滤波方法
公开(公告)号：US20080240220A1
公开(公告)日：2008-10-02
申请号：US12023377
申请日：2008-01-31
申请人： Bjoern ELLERMEYER
发明人： Bjoern ELLERMEYER
IPC分类号： H03D1/00 , H04L27/06
CPC分类号： H03H17/0292 , H03H17/0275 , H03H17/0621 , H03H17/0664 , H03H2218/085
摘要： Digital filter, comprising a multiplier configured to generate an intermediate signal, wherein said intermediate signal is generated by multiplying an input signal with a filter coefficient signal, wherein said multiplier is operated at a clock rate and said input signal has a sampling rate, wherein said clock rate is higher than said sampling rate; a first buffer configured to supply said filter coefficient signal to said multiplier at said clock rate, wherein said filter coefficient signal represents N filter coefficients in a periodic order, wherein N denotes the order of said digital filter; a second buffer configured to buffer N/2 samples of an intermediate output signal and to generate a respective time delayed intermediate output signal; and an adder configured to generate said intermediate output signal or an output signal of said digital filter based on an addition of said time delayed intermediate output signal and said intermediate signal.
摘要翻译：数字滤波器，包括被配置为产生中间信号的乘法器，其中所述中间信号通过将输入信号与滤波器系数信号相乘而产生，其中所述乘法器以时钟速率操作，并且所述输入信号具有采样率，其中所述时钟频率高于所述采样率; 第一缓冲器，被配置为以所述时钟速率将所述滤波器系数信号提供给所述乘法器，其中所述滤波器系数信号以周期顺序表示N个滤波器系数，其中N表示所述数字滤波器的阶数; 第二缓冲器，被配置为缓冲中间输出信号的N / 2采样并产生相应的时间延迟的中间输出信号; 以及加法器，被配置为基于所述延时中间输出信号和所述中间信号的相加来产生所述中间输出信号或所述数字滤波器的输出信号。

57. 发明申请

US20080208941A1 Interpolation Process Circuit 审中-公开
标题翻译：插值过程电路
公开(公告)号：US20080208941A1
公开(公告)日：2008-08-28
申请号：US11915085
申请日：2006-02-08
申请人： Yukio Koyanagi
发明人： Yukio Koyanagi
IPC分类号： G06F17/17
CPC分类号： H03H17/0621 , G06T3/4007 , H03H17/0223 , H03H17/026 , H03H17/0294 , H03H17/0657 , H04N7/0135
摘要： There are included a three-tap FIR calculating part (2) that multiples data outputted from three taps on a tapped delay line by respective filter factors comprising a ratio value sequence of “−1, m, −1”; and an n-tap FIR calculating part (3) that multiples data outputted from n taps on a tapped delay line by respective filter factors comprising a predetermined value sequence. Interpolation values can be determined by use of sum-of-products calculations using various factor sequences comprising various values of m and n. The three-tap FIR calculating part (2) is adapted to determine interpolation values by use of the sum-of-products calculations that always use only three values. In this way, the circuit scale can be reduced and further the calculation process can be simplified, thereby achieving a high-rate interpolation process.
摘要翻译：包括三抽头FIR计算部分（2），其通过包括比率值序列“-1，m，-1”的各个滤波器因数对从抽头延迟线上的三个抽头输出的数据进行倍数; 以及n抽头FIR计算部分（3），其通过包括预定值序列的各个滤波器因数对抽头延迟线上的n个抽头输出的数据进行倍数。插值可以通过使用包含各种m和n值的各种因子序列的乘积求和计算来确定。三抽头FIR计算部分（2）适于通过使用总是仅使用三个值的积和积计算来确定内插值。以这种方式，可以减小电路规模，进一步简化计算处理，从而实现高速率插值处理。

58. 发明授权

US07327288B2 Variable interpolator for non-uniformly sampled signals and method 失效
标题翻译：用于非均匀采样信号的可变内插器和方法
公开(公告)号：US07327288B2
公开(公告)日：2008-02-05
申请号：US11394254
申请日：2006-03-30
申请人： Luciano Zoso , Allan P. Chin , David P. Lester
发明人： Luciano Zoso , Allan P. Chin , David P. Lester
IPC分类号： H03M7/00
CPC分类号： H03H17/0671 , H03H17/0621 , H03H17/0657 , H03H2218/14
摘要： A variable interpolator (110) has an interpolation factor L for performing an interpolation of an input signal (124), where L is variable and includes a minimum value. The variable interpolator includes a differentiator (110-1), a chopper (112), and an integrator (110-2). The differentiator (110-1) is responsive to a signal on the differentiator input for performing a differentiator portion of the interpolation and for providing a differentiator result signal (134). The chopper is coupled with the differentiator for chopping the differentiator result signal as a function of the minimum value of L, wherein for an interpolator input signal that contains non-uniformly sampled signals in which there exists at least one sample of a shortest duration and at least one sample of a duration that extends beyond the shortest duration, the minimum value of L corresponds to the duration of the sample of shortest duration, and wherein for an interpolator input signal that contains uniformly sampled signals in which the samples are of a fixed duration, the minimum value of L corresponds to the fixed duration. The integrator is responsive to the chopped differentiator result signal for performing an integrator portion of the interpolation and for providing an integrator result signal, corresponding to an output (142) of the variable interpolator.
摘要翻译：可变内插器（110）具有用于执行输入信号（124）的内插的内插因子L，其中L是可变的并且包括最小值。可变内插器包括微分器（110-1），斩波器（112）和积分器（110-2）。微分器（110-1）响应微分器输入上的信号，以执行插值的微分器部分并提供微分器结果信号（134）。斩波器与微分器耦合，作为L的最小值的函数斩波微分器结果信号，其中对于包含非均匀采样信号的内插器输入信号，其中存在至少一个具有最短持续时间的样本和持续时间超过最短持续时间的至少一个样本，L的最小值对应于最短持续时间的样本的持续时间，并且其中对于包含均匀采样的信号的内插器输入信号，其中采样具有固定持续时间，L的最小值对应于固定持续时间。积分器响应于斩波微分器结果信号，以执行内插的积分器部分，并提供对应于可变内插器的输出（142）的积分器结果信号。

59. 发明申请

US20070299552A1 AUDIO PROCESSING CIRCUIT AND METHOD 有权
标题翻译：音频处理电路和方法
公开(公告)号：US20070299552A1
公开(公告)日：2007-12-27
申请号：US11612113
申请日：2006-12-18
申请人： Zhi-Ren Chang , Shin-Ing Hsieh , Kuo-Feng Hsu , Chi-Han Lan , Horng-Der Chang
发明人： Zhi-Ren Chang , Shin-Ing Hsieh , Kuo-Feng Hsu , Chi-Han Lan , Horng-Der Chang
IPC分类号： G06F17/00
CPC分类号： H03H17/0621
摘要： An audio processing circuit includes a clock synthesizer, a clock divider, a digital interpolator module, a sampling rate converter and a digital-to-analog converter. The clock synthesizer generates a base clock signal according to a sampling clock signal and a first reference clock signal. The clock divider generates a multiple frequency clock signal according to the base clock signal. The digital interpolator module interpolates a digital audio data according to the multiple frequency clock signal. The sampling rate converter processes the interpolated digital audio data into a re-sampled digital audio data according to the multiple frequency clock signal and a second reference clock signal. The digital-to-analog converter is coupled to the sampling rate converter for converting the re-sampled digital audio data into an analog audio signal according to the second reference clock signal.
摘要翻译：音频处理电路包括时钟合成器，时钟分频器，数字内插器模块，采样率转换器和数模转换器。时钟合成器根据采样时钟信号和第一参考时钟信号产生基本时钟信号。时钟分频器根据基本时钟信号产生多频时钟信号。数字插值器模块根据多频时钟信号内插数字音频数据。采样率转换器根据多频时钟信号和第二参考时钟信号将内插的数字音频数据处理成重新采样的数字音频数据。数模转换器耦合到采样率转换器，用于根据第二参考时钟信号将重新采样的数字音频数据转换为模拟音频信号。

60. 发明申请

US20070096964A1 SYSTEM AND METHOD FOR EFFICIENT UPSAMPLED SIGNAL PROCESSING 有权
标题翻译：用于有效的UPS管理信号处理的系统和方法
公开(公告)号：US20070096964A1
公开(公告)日：2007-05-03
申请号：US11262424
申请日：2005-10-28
申请人： Dusan Veselinovic , Daniela Radakovic
发明人： Dusan Veselinovic , Daniela Radakovic
IPC分类号： H03M1/66
CPC分类号： H03H17/0294 , H03H17/0621
摘要： A system and method for efficiently upsampling and filtering a signal is provided. The system includes a controller 216 and an upsampler 202 capable of upsampling a digitized signal. The upsampler 202 converts a digitized signal having a first sampled frequency into a digitized signal having a second sampled frequency by inserting, for example, at least one zero between the samples of the digitized signal. A plurality of filters 205-208 is coupled to the upsampler. These filters, which may be band-pass filters, would be suitable for front end encoding in audio-based applications. The controller 216 adjusts at least one output of the plurality of the filters to zero, either by deactivation or forcing the filter to zero, based upon a predetermined characteristic of the digitized signal. One example of a predetermined characteristic is a maximum frequency of interest.
摘要翻译：提供了一种有效地对信号进行上采样和滤波的系统和方法。该系统包括能够对数字化信号进行上采样的控制器216和上采样器202。上采样器202通过在数字化信号的样本之间插入例如至少一个零点，将具有第一采样频率的数字化信号转换为具有第二采样频率的数字化信号。多个滤波器205-208耦合到上采样器。这些可以是带通滤波器的滤波器将适用于基于音频的应用中的前端编码。控制器216基于数字化信号的预定特性，将多个滤波器的至少一个输出调整为零，或者通过去激活或迫使滤波器为零。预定特性的一个例子是感兴趣的最大频率。

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