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51. 发明申请

US20150061736A1 SPREAD-SPECTRUM PHASE LOCKED LOOP CIRCUIT AND METHOD 有权
标题翻译：扩展频谱相位锁定环路和方法
公开(公告)号：US20150061736A1
公开(公告)日：2015-03-05
申请号：US14080987
申请日：2013-11-15
申请人： CAPITAL MICROELECTRONICS CO., LTD.
发明人： Rifeng MAI
IPC分类号： H03L7/08
CPC分类号： H03L7/0802 , H03B23/00 , H03C3/095 , H03L7/093 , H03L7/18 , H04B1/7087
摘要： A phase locked loop (PLL) circuit and a method thereof are provided. In an embodiment, the PLL circuit includes: a switched capacitor circuit, in which the switched capacitor circuit generates a modulation waveform, and the modulation waveform is injected into the PLL circuit in a current form, so that a PLL output frequency is modulated. Compared with the spread spectrum phase locked loop (SS-PLL) in the prior art, the SS-PLL in embodiments of the present invention is simple in structure, low in power consumption, low in silicon overhead, and flexible both in spreading factor and modulation frequency.
摘要翻译：提供了一种锁相环（PLL）电路及其方法。在一个实施例中，PLL电路包括：开关电容器电路，其中开关电容器电路产生调制波形，并且将调制波形以当前形式注入到PLL电路中，从而调制PLL输出频率。与现有技术中的扩频锁相环（SS-PLL）相比，本发明实施例中的SS-PLL结构简单，功耗低，硅开销低，扩频因子和调制频率。

52. 发明授权

US08736388B2 Oscillators having arbitrary frequencies and related systems and methods 有权
公开(公告)号：US08736388B2
公开(公告)日：2014-05-27
申请号：US12721484
申请日：2010-03-10
申请人： Klaus Juergen Schoepf , Reimund Rebel , Jan H. Kuypers
发明人： Klaus Juergen Schoepf , Reimund Rebel , Jan H. Kuypers
IPC分类号： H03B5/30 , H03L7/099 , H03B19/00
CPC分类号： H03B5/30 , H03B5/32 , H03B19/00 , H03C3/095 , H03J7/065 , H03L7/0991 , H03L7/18 , H03L7/197 , H04B1/40
摘要： Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal.

53. 发明授权

US08576948B2 Angle modulator, transmission device, and wireless communication device 有权
标题翻译：角度调制器，传输设备和无线通信设备
公开(公告)号：US08576948B2
公开(公告)日：2013-11-05
申请号：US13256894
申请日：2010-12-17
申请人： Toru Matsuura , Kenji Miyanaga
发明人： Toru Matsuura , Kenji Miyanaga
IPC分类号： H04B1/38 , H04B7/00 , H03C1/50 , H03C3/02
CPC分类号： H04L27/20 , H03C3/095
摘要： Disclosed are an angle modulator, a transmission apparatus, and a radio communication apparatus that can compensate phase discontinuity when an operational mode of a voltage controlled oscillator is switched. Angle modulator (100) includes phase difference detection section (150) that detects a difference of phases between an input signal of subtractor (141) and an angle modulated signal, using the result of subtraction by subtractor (141) of frequency locked loop circuit (140); correction control section (160) that generates a control signal for compensating that difference of phases based on that difference of phases; correction section (120) that corrects the phase of the angle modulated signal by adding the control signal to an input signal of angle modulator (100), an input signal of loop filter (142), or an input signal of VCO (143) during a predetermined period after VCO (143) switches the operational mode (from time t3 to time t4).
摘要翻译：公开了一种角度调制器，发送装置和无线电通信装置，其可以在切换压控振荡器的操作模式时补偿相位不连续性。角度调制器（100）包括相位差检测部分（150），其使用锁相环电路的减法器（141）减法的结果来检测减法器（141）的输入信号与角度调制信号之间的相位差 140）; 校正控制部分（160），其基于所述相位差产生用于补偿所述相位差的控制信号; 校正部分（120），其通过将控制信号与角度调制器（100）的输入信号，环路滤波器（142）的输入信号或VCO（143）的输入信号相加来校正角度调制信号的相位，在VCO（143）切换操作模式（从时间t3到时间t4）之后的预定时间段。

54. 发明授权

US08433026B2 Multi-rate digital phase locked loop 有权
标题翻译：多速数字锁相环
公开(公告)号：US08433026B2
公开(公告)日：2013-04-30
申请号：US12478506
申请日：2009-06-04
申请人： Gary John Ballantyne , Jifeng Geng , Daniel F. Filipovic
发明人： Gary John Ballantyne , Jifeng Geng , Daniel F. Filipovic
IPC分类号： H03D3/24
CPC分类号： H03L7/08 , H03C3/0941 , H03C3/095 , H03C3/0966 , H03L2207/50
摘要： A Digital Phase-Locked Loop (DPLL) involves a Time-to-Digital Converter (TDC) that receives a Digitally Controlled Oscillator (DCO) output signal and a reference clock and outputs a first stream of digital values. The TDC is clocked at a high rate. Downsampling circuitry converts the first stream into a second stream. The second stream is supplied to a phase detecting summer of the DPLL such that a control portion of the DPLL can switch at a lower rate to reduce power consumption. The DPLL is therefore referred to as a multi-rate DPLL. A third stream of digital tuning words output by the control portion is upsampled before being supplied to the DCO so that the DCO can be clocked at the higher rate. In a receiver application, no upsampling is performed and the DCO is clocked at the lower rate.
摘要翻译：数字锁相环（DPLL）涉及一个时间数字转换器（TDC），它接收数字控制振荡器（DCO）输出信号和参考时钟并输出第一个数字值。贸发局的拨款率很高。下采样电路将第一流转换为第二流。第二流被提供给DPLL的相位检测加法器，使得DPLL的控制部分可以以较低的速率切换以降低功耗。因此，DPLL被称为多速率DPLL。由控制部分输出的第三个数字调谐字流在被提供给DCO之前被上采样，使得DCO可以以更高的速率被计时。在接收机应用中，不执行上采样，并且DCO以较低速率被计时。

55. 发明授权

US08416461B2 Spread spectrum clock generator, spread spectrum clock generating method, and circuit, image reading device and image forming apparatus using the spread spectrum clock generator 有权
标题翻译：扩频时钟发生器，扩频时钟产生方法，电路，图像读取装置和使用扩频时钟发生器的图像形成装置
公开(公告)号：US08416461B2
公开(公告)日：2013-04-09
申请号：US12796107
申请日：2010-06-08
申请人： Masamoto Nakazawa
发明人： Masamoto Nakazawa
IPC分类号： H04N1/407 , H04N1/36 , H03L7/06 , H04B1/00 , H03D3/24 , G06F1/00
CPC分类号： H03L7/18 , H03C3/0916 , H03C3/095 , H04N1/00994 , H04N2201/0081
摘要： The spread spectrum clock generator (SSCG) includes a phase comparator detecting phase difference between input clock and feedback clock; a charge pump supplying current depending on the phase difference; a loop filter converting the current to smoothed voltage; a voltage controlled oscillator generating a spread spectrum clock signal depending on the smoothed voltage; and a modulation signal generator generating modulation signal having amplitude depending on a modulation width set value. The SSCG further includes a modulation width detector detecting modulation width of the spread spectrum clock signal while comparing the modulation width with a modulation width target value to update the modulation width set value to narrow difference between the detected modulation width and the modulation width target value, followed by feeding back the updated modulation width set value to the modulation signal generator.
摘要翻译：扩频时钟发生器（SSCG）包括检测输入时钟和反馈时钟之间的相位差的相位比较器; 电荷泵根据相位差提供电流; 将电流转换成平滑电压的环路滤波器; 产生根据平滑电压的扩频时钟信号的压控振荡器; 产生具有取决于调制宽度设定值的振幅的调制信号的调制信号发生器。 SSCG还包括调制宽度检测器，用于检测扩频时钟信号的调制宽度，同时将调制宽度与调制宽度目标值进行比较，以将调制宽度设置值更新为检测调制宽度与调制宽度目标值之间的差异，然后将更新的调制宽度设置值反馈给调制信号发生器。

56. 发明申请

US20120133403A1 TWO-POINT MODULATION DEVICE USING VOLTAGE CONTROLLED OSCILLATOR, AND CALIBRATION METHOD 有权
标题翻译：使用电压控制振荡器的两点调制装置和校准方法
公开(公告)号：US20120133403A1
公开(公告)日：2012-05-31
申请号：US13389290
申请日：2010-06-16
申请人： Kenji Miyanaga , Takayuki Tsukizawa
发明人： Kenji Miyanaga , Takayuki Tsukizawa
IPC分类号： H03L7/08
CPC分类号： H03C3/0941 , H03C3/095 , H03C3/0966 , H03L7/083 , H03L2207/05 , H03L2207/06
摘要： Included are: a modulation section including a feedback circuit configured to conduct feedback control of an output signal from a voltage controlled oscillator based on an inputted modulation signal, and a feed-forward circuit configured to calibrate the modulation signal and outputting the calibrated modulation signal to the voltage controlled oscillator; a signal output section configured to output, to the modulation section, a predetermined reference signal instead of the modulation signal when a calibration is conducted; and a gain correction section configured to, in a state where the feedback circuit is forming an open loop, calculate a frequency transition amount of the reference signal outputted by the voltage controlled oscillator, and correct a gain used for calibrating the modulation signal at the feed-forward circuit based on the calculated frequency transition amount.
摘要翻译：包括：调制部，其包括反馈电路，其被配置为基于输入的调制信号对来自压控振荡器的输出信号进行反馈控制;以及前馈电路，被配置为校准调制信号并将校准的调制信号输出到压控振荡器; 信号输出部，被配置为当进行校准时，将调制部分代替预定的参考信号，而不是调制信号; 以及增益校正部，被配置为在所述反馈电路形成开路的状态下，计算由所述压控振荡器输出的所述参考信号的频率变化量，并且校正用于校准所述馈送时的所述调制信号的增益基于计算的频率转换量的前馈电路。

57. 发明授权

US08170171B2 Communication semiconductor integrated circuit 有权
标题翻译：通信半导体集成电路
公开(公告)号：US08170171B2
公开(公告)日：2012-05-01
申请号：US12356870
申请日：2009-01-21
申请人： Hiroyuki Kobayashi
发明人： Hiroyuki Kobayashi
IPC分类号： H03D3/24
CPC分类号： H03C3/0941 , H03C3/095 , H03C3/0975
摘要： A communication semiconductor integrated circuit, has: a first computing element which adds the count value and the phase difference value and outputs a first computed value as an addition result; a second computing element which adds set frequency data obtained by dividing a carrier frequency by a reference frequency of the reference signal and modulation frequency data obtained by dividing a modulation frequency by the reference frequency, and outputs a second computed value as an addition result; a third computing element which subtracts the second computed value from the first computed value and outputs a third computed value as a subtraction result, the third computed value being a phase error; and a fourth computing element which adds the carrier frequency control value and the modulation frequency control value, and outputs the oscillator tuning word as an addition result.
摘要翻译：通信半导体集成电路具有：第一计算单元，其将计数值和相位差值相加，并输出第一计算值作为相加结果; 将通过将载波频率除以参考信号的参考频率而获得的设置频率数据和通过将调制频率除以参考频率获得的调制频率数据的第二计算元件，并输出第二计算值作为相加结果; 第三计算元件，其从所述第一计算值中减去所述第二计算值，并输出第三计算值作为减法结果，所述第三计算值是相位误差; 以及第四计算单元，其添加载波频率控制值和调制频率控制值，并输出振荡器调谐字作为相加结果。

58. 发明授权

US07979038B2 PLL modulation circuit, radio transmission device, and radio communication device 有权
标题翻译： PLL调制电路，无线电传输设备和无线电通信设备
公开(公告)号：US07979038B2
公开(公告)日：2011-07-12
申请号：US12160874
申请日：2007-01-16
申请人： Yosuke Mitani , Shunsuke Hirano , Kaoru Ishida
发明人： Yosuke Mitani , Shunsuke Hirano , Kaoru Ishida
IPC分类号： H04B1/04
CPC分类号： H03L7/1976 , H03C3/0908 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0966
摘要： Provided are a PLL modulation circuit, a radio transmission device, and a radio communication device capable of maintaining a modulation accuracy for modulation of a wide band. The PLL modulation circuit (100) includes: a PLL unit (110), first modulation signal input means for inputting a first modulation signal to a divider (112) or a phase comparator (113) of the PLL unit (110); second modulation signal input means for DA converting the digital modulation signal in a DA converter (116) to generate an analog second modulation signal and inputting it to a voltage control oscillator (111) of the PLL unit (110); a second divider for dividing the output signal of the voltage control oscillator (111); and control means for generating a center frequency control signal, a gain control signal, and a second division ration control signal according to the channel selection signal and the control voltage inputted to the voltage control oscillator (111) and supplying them to the divider (112), the DA converter (116), and the second divider (114), respectively.
摘要翻译：提供了能够维持宽带调制的调制精度的PLL调制电路，无线发送装置以及无线通信装置。 PLL调制电路（100）包括：PLL单元（110），用于将第一调制信号输入到PLL单元（110）的分频器（112）或相位比较器（113）的第一调制信号输入装置; 第二调制信号输入装置，用于在DA转换器（116）中转换数字调制信号，以产生模拟第二调制信号并将其输入到PLL单元（110）的电压控制振荡器（111）; 用于分压电压控制振荡器（111）的输出信号的第二分频器; 以及控制装置，用于根据输入到电压控制振荡器（111）的通道选择信号和控制电压产生中心频率控制信号，增益控制信号和第二分频控制信号，并将其提供给分频器（112）），DA转换器（116）和第二分频器（114）。

59. 发明授权

US07940142B2 Two-point modulation polar transmitter architecture and method for performance enhancement 有权
标题翻译：两点调制极性发射机架构和方法进行性能提升
公开(公告)号：US07940142B2
公开(公告)日：2011-05-10
申请号：US12506997
申请日：2009-07-21
申请人： Henrik T. Jensen , Brima B. Ibrahim
发明人： Henrik T. Jensen , Brima B. Ibrahim
IPC分类号： H03C3/20 , H03C3/06
CPC分类号： H03L7/1976 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0991 , H03L7/093
摘要： A polar transmitter includes a two-point modulation phase-locked loop (PLL) for producing an RF signal with a wide bandwidth. The PLL includes a first input for receiving a phase signal of a variable-envelope modulated signal and providing the phase signal along a first signal path to produce a first frequency modulation signal and a second input for receiving the phase signal and providing the phase signal along a second signal path to produce a second frequency modulation signal. The PLL further includes a voltage controlled oscillator (VCO) having two modulation points, one for receiving the first frequency modulation signal and the other for receiving the second frequency modulation signal. The VCO is controlled by an aggregate of the first frequency modulation signal and the second frequency modulation signal to up-convert the phase signal from an IF to an RF to produce the RF signal with a wide bandwidth.
摘要翻译：极性发射机包括用于产生宽带宽的RF信号的两点调制锁相环（PLL）。 PLL包括用于接收可变包络调制信号的相位信号并沿着第一信号路径提供相位信号以产生第一频率调制信号的第一输入端和用于接收相位信号并提供相位信号的第二输入端用于产生第二频率调制信号的第二信号路径。 PLL还包括具有两个调制点的压控振荡器（VCO），一个用于接收第一频率调制信号，另一个用于接收第二频率调制信号。 VCO由第一频率调制信号和第二频率调制信号的集合控制，以将来自IF的相位信号上变频到RF以产生具有宽带宽的RF信号。

60. 发明申请

US20110032040A1 WIDE SPECTRUM RADIO TRANSMIT ARCHITECTURE 有权
标题翻译：宽频无线电发射架构
公开(公告)号：US20110032040A1
公开(公告)日：2011-02-10
申请号：US12535753
申请日：2009-08-05
申请人： Kenneth Beghini
发明人： Kenneth Beghini
IPC分类号： H03L7/00
CPC分类号： H04B1/0075 , H03C3/0941 , H03C3/095 , H03C3/0966 , H03L7/099 , H03L7/183 , H03L7/23 , H04L27/12 , H04L27/206 , H04L27/362
摘要： A communications device (100) includes a frequency divider circuit (106) having a plurality of frequency division ratios. The device also includes at least one phase-lock loop (PLL) circuit (101, 102, 103, 104, 110, 112) coupled to at least a signal input of the frequency divider circuit. The PLL circuit includes a local oscillator (LO) circuit (104) including a plurality of voltage controlled oscillators (VCOs) having different frequency tuning ranges. The device further includes at least one control input (105) coupled to at least the frequency divider circuit and the PLL circuit for specifying one of the plurality of VCOs and one of the plurality of frequency division ratios of the frequency divider circuit.
摘要翻译：通信设备（100）包括具有多个分频比的分频器电路（106）。该装置还包括耦合到分频器电路的至少一个信号输入的至少一个锁相环（PLL）电路（101,102,103,104,110,112）。 PLL电路包括包括具有不同频率调谐范围的多个压控振荡器（VCO）的本地振荡器（LO）电路（104）。该装置还包括耦合到至少分频器电路和PLL电路的至少一个控制输入（105），用于指定多个VCO中的一个并且分频器电路的多个分频比之一。

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