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51. 发明申请

US20070252731A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20070252731A1
公开(公告)日：2007-11-01
申请号：US11785673
申请日：2007-04-19
申请人： Yi-Sun Chung
发明人： Yi-Sun Chung
IPC分类号： H03M7/00
CPC分类号： H01L27/0722 , H01L21/761 , H01L21/823878 , H01L21/823892 , H01L21/8249 , H01L27/0928
摘要： A semiconductor integrated circuit including digital circuits and analog circuits integrated over a single substrate includes the substrate including portions where the digital circuits and the analog circuits are to be formed, and a plurality of deep-wells formed to a certain thickness inside the substrate to surround portions where devices of the digital circuits and devices of the analog circuits are to be formed to reduce interference between the devices of the analog circuits and the digital circuits.
摘要翻译：包括集成在单个基板上的数字电路和模拟电路的半导体集成电路包括：基板，包括要形成数字电路和模拟电路的部分;以及在基板内形成一定厚度的多个深阱，要形成数字电路的设备和模拟电路的设备的部分，以减少模拟电路的设备与数字电路之间的干扰。

52. 发明申请

US20050242371A1 High current MOS device with avalanche protection and method of operation 审中-公开
标题翻译：大电流MOS器件具有雪崩保护和操作方法
公开(公告)号：US20050242371A1
公开(公告)日：2005-11-03
申请号：US10836730
申请日：2004-04-30
申请人： Vishnu Khemka , Amitava Bose , Vijay Parthasarathy , Ronghua Zhu
发明人： Vishnu Khemka , Amitava Bose , Vijay Parthasarathy , Ronghua Zhu
IPC分类号： H01L27/07 , H01L29/08 , H01L29/423 , H01L29/78 , H01L31/113
CPC分类号： H01L29/0847 , H01L27/0722 , H01L29/42368 , H01L29/7835
摘要： Particularly in high current applications, impact ionization induced electron-hole pairs are generated in the drain of an MOS transistor that can cause a parasitic bipolar transistor to become destructively conductive. The holes pass through the body region of the MOS transistor, which has intrinsic resistance, to the source, which is typically held at a relatively low voltage, such as ground. The hole current causes a voltage to develop in the body region, which acts as the base. This increased base voltage is what can cause the parasitic bipolar transistor to become conductive. The likelihood of this is greatly reduced by developing a voltage between the source, which acts as the emitter, and the body region by passing the channel current through an impedance between the source and the body region. This causes the emitter voltage to increase as the base voltage is increased and thereby prevent the parasitic bipolar transistor from becoming conductive.
摘要翻译：特别是在高电流应用中，在MOS晶体管的漏极中产生电子 - 电子碰撞的碰撞对，这可使寄生双极晶体管变得具有破坏性的导电性。这些孔通过具有固有电阻的MOS晶体管的体区通向保持在较低电压（例如地）的源极。空穴电流导致在作为基底的身体区域中产生电压。这种增加的基极电压可以导致寄生双极晶体管导通。通过使通道电流通过源极和体区之间的阻抗，在作为发射极的源与体区之间形成电压，大大降低了这种可能性。这导致发射极电压随着基极电压的增加而增加，从而防止寄生双极晶体管导通。

53. 发明授权

US06140683A Efficient NPN turn-on in a high voltage DENMOS transistor for ESD protection 有权
标题翻译：高电压DENMOS晶体管的高效NPN导通，用于ESD保护
公开(公告)号：US06140683A
公开(公告)日：2000-10-31
申请号：US251015
申请日：1999-02-16
申请人： Charvaka Duvvury , David Douglas Briggs , Fernando David Carvajal
发明人： Charvaka Duvvury , David Douglas Briggs , Fernando David Carvajal
IPC分类号： H01L27/02 , H01L27/07 , H01L23/62
CPC分类号： H01L27/0259 , H01L27/0722
摘要： A high voltage DENMOS transistor (10) having improved ESD protection. The transistor (10) is optimized to provide maximum substrate current in order to turn on the inherent lateral npn transistor during an ESD event so that the lateral npn can dissipate the ESD event without damage to the transistor (10). This is accomplished by optimizing the overlap (A) of the drain extended region (16) and the gate electrode (28) to control the gate coupling to achieve maximum substrate current.
摘要翻译：具有改进的ESD保护的高电压DENMOS晶体管（10）。晶体管（10）被优化以提供最大衬底电流，以便在ESD事件期间导通固有横向npn晶体管，使得横向npn可以耗散ESD事件而不损坏晶体管（10）。这通过优化漏极扩展区域（16）和栅电极（28）的重叠（A）来实现，以控制栅极耦合以实现最大衬底电流。

54. 发明授权

US6015982A Lateral bipolar field effect mode hybrid transistor and method for operating the same 失效
标题翻译：侧面双极场效应模式混合晶体管及其操作方法
公开(公告)号：US6015982A
公开(公告)日：2000-01-18
申请号：US968213
申请日：1997-11-12
申请人： Anders Soderbarg
发明人： Anders Soderbarg
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L27/07 , H01L27/095 , H01L29/772 , H01L27/085
CPC分类号： H01L27/0722
摘要： The invention relates to a semiconductor device and a method in this device, wherein the semiconductor device operates completely or partly in lateral extension. The semiconductor device comprises at least two high-voltage lateral bipolar transistors with at least two mutually opposite emitter/base regions, which are placed at the surface of the epi-taxial layer at a mutual distance such that an intermediate common collector region is formed. The common collector region can be completely depleted when the device has a voltage applied and by using a lateral depletion of said collector region, the voltage durability of the semiconductor device can be determined lithographically by the distance between the doped regions comprised in the device. Furthermore, undesired parasitic components, which are dependent on the quality of the active layer of the device, resistivity and substrate potential, can be eliminated or suppressed.
摘要翻译：本发明涉及这种器件中的半导体器件和方法，其中半导体器件完全或部分地横向延伸。半导体器件包括至少两个具有至少两个彼此相对的发射极/基极区域的高电压横向双极晶体管，它们以相互间隔放置在外围层的表面，使得形成中间共同集电极区域。当器件具有施加的电压并且通过使用所述集电极区域的横向耗尽时，公共集电极区域可以完全耗尽，可以通过包括在器件中的掺杂区域之间的距离光刻地确定半导体器件的电压耐久性。此外，可以消除或抑制依赖于器件的有源层的质量，电阻率和衬底电位的不期望的寄生成分。

55. 发明授权

US5789790A Semiconductor device 失效
公开(公告)号：US5789790A
公开(公告)日：1998-08-04
申请号：US549517
申请日：1995-10-27
申请人： Masakazu Morishita , Shigetoshi Sugawa , Toru Koizumi
发明人： Masakazu Morishita , Shigetoshi Sugawa , Toru Koizumi
IPC分类号： H01L21/331 , H01L21/8249 , H01L27/06 , H01L27/07 , H01L29/10 , H01L29/73 , H01L29/739 , H01L29/78 , H01L29/786 , H01L29/76 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/78696 , H01L27/0623 , H01L27/0722 , H01L29/1087 , H01L29/7317 , H01L29/739 , H01L29/7838 , H01L29/78654
摘要： A semiconductor device has a transistor made of a semiconductor which has a source and drain regions, a channel region, a gate insulative film, and a gate electrode. The gate electrode is connected to a part of the channel region. The channel region has the same conductivity type as that of the source and drain regions and has an impurity concentration lower than that of the source and drain regions.

56. 发明授权

US5670396A Method of forming a DMOS-controlled lateral bipolar transistor 失效
标题翻译：形成DMOS控制横向双极晶体管的方法
公开(公告)号：US5670396A
公开(公告)日：1997-09-23
申请号：US561473
申请日：1995-11-21
申请人： Muhammed Ayman Shibib
发明人： Muhammed Ayman Shibib
IPC分类号： H01L21/331 , H01L27/07 , H01L29/78 , H01L21/265
CPC分类号： H01L29/7816 , H01L27/0722 , H01L29/66325 , H01L29/7801
摘要： DMOS-controlled lateral bipolar transistor comprises a first region of a first conductivity type for providing a collector, a second region of a second conductivity type opposite the first conductivity type for providing a base, a third region of the first conductivity type for providing an emitter, a dielectric on the second region, and an electrode on the dielectric wherein the electrode provides a gate for a DMOS transistor, the first region provides a drain for the DMOS transistor, the second region provides a channel region for the DMOS transistor, and the third region provides a source for the DMOS transistor.
摘要翻译： DMOS控制的横向双极晶体管包括用于提供集电极的第一导电类型的第一区域，与用于提供基极的第一导电类型相反的第二导电类型的第二区域，用于提供发射极的第一导电类型的第三区域，第二区域上的电介质和电介质上的电极，其中电极为DMOS晶体管提供栅极，第一区域为DMOS晶体管提供漏极，第二区域为DMOS晶体管提供沟道区域，并且第三区域为DMOS晶体管提供源。

57. 发明授权

US5552624A Multi-function electronic component, especially negative dynamic resistance element, and corresponding method of fabrication 失效
标题翻译：多功能电子元件，特别是负动态电阻元件，以及相应的制造方法
公开(公告)号：US5552624A
公开(公告)日：1996-09-03
申请号：US86979
申请日：1993-07-02
申请人： Tomasz Skotnicki , Gerard Merckel
发明人： Tomasz Skotnicki , Gerard Merckel
IPC分类号： H01L47/00 , H01L27/07 , H01L27/12 , H01L29/66 , H01L29/786 , H01L27/01
CPC分类号： H01L29/78621 , H01L27/0722 , H01L27/12
摘要： The electronic component comprises, topologically integrated within the same semiconductor structure (1), a first semiconductor area (12, 13, 3, 4, 20) capable of forming an insulated-gate field-effect transistor, and a second semiconductor area (12, 20, 18, 19, 11) capable of forming a lateral bipolar transistor, the two areas having a common semiconductor layer (20) in which the channel of the field-effect transistor is capable of being formed and/or the base current of the bipolar transistor is capable of flowing, the two areas being capable together of forming a structure capable of negative dynamic resistance.
摘要翻译：电子部件包括拓扑结合在相同的半导体结构（1）内的能够形成绝缘栅场效应晶体管的第一半导体区域（12,13,3，4，20）和第二半导体区域（12 ，20,18,19,11），所述两个区域具有共同的半导体层（20），其中能够形成场效应晶体管的沟道和/或基极电流双极晶体管能够流动，两个区域能够一起形成能够产生负动态电阻的结构。

58. 发明授权

US4506282A Normally-off semiconductor device with low on resistance and circuit analogue 失效
标题翻译：具有低导通电阻和电路模拟的常关半导体器件
公开(公告)号：US4506282A
公开(公告)日：1985-03-19
申请号：US455174
申请日：1983-01-03
申请人： Bantval J. Baliga
发明人： Bantval J. Baliga
IPC分类号： H01L29/80 , H01L21/331 , H01L21/8222 , H01L21/8248 , H01L27/06 , H01L27/07 , H01L29/73 , H03K17/567 , H01L29/72
CPC分类号： H03K17/567 , H01L27/0722
摘要： A semiconductor device incorporates a JFET serially connected to a bipolar transistor to achieve normally-off operation. An impedance element is connected between the base of the bipolar transistor and the gate of the JFET, which serves as a single control electrode for the entire device. When a current is supplied to the control electrode, the bipolar transistor and JFET are both switched to the on state. In the JFET, the p-N junction between the gate region and the channel region is sufficiently forward-biased so as to inject current carriers into its channel region and markedly reduce the device on-resistance. An electrical circuit analogue of the device achieves the advantage of low on-resistance and normally-off operation.
摘要翻译：半导体器件包括串联连接到双极晶体管的JFET以实现常关断操作。阻抗元件连接在双极晶体管的基极和JFET的栅极之间，JFET用作整个器件的单个控制电极。当电流被提供给控制电极时，双极晶体管和JFET都被切换到导通状态。在JFET中，栅极区域和沟道区域之间的p-N结被充分正向偏置，以便将电流载流子注入其沟道区域并显着地减小器件导通电阻。器件的电路模拟实现了低导通电阻和常闭操作的优点。

59. 发明授权

US4131908A Semiconductor protection device having a bipolar lateral transistor 失效
标题翻译：具有双极横向晶体管的半导体保护器件
公开(公告)号：US4131908A
公开(公告)日：1978-12-26
申请号：US767569
申请日：1977-02-10
申请人： Dirk Daub , Olof E. H. Klaver
发明人： Dirk Daub , Olof E. H. Klaver
IPC分类号： H02H7/20 , H01L21/822 , H01L27/00 , H01L27/02 , H01L27/04 , H01L27/06 , H01L27/07 , H03F1/52 , H03K17/0812
CPC分类号： H03K17/08122 , H01L27/00 , H01L27/0248 , H01L27/0251 , H01L27/0722 , H03F1/523
摘要： A safeguarded integrated circuit includes two supply electrodes, an output electrode and an input electrode. Between two of the electrodes there is provided a protection circuit having a lateral bipolar transistor, the emitter and collector zones of which are connected respectively to the said electrodes. The bipolar transistor is provided in a region which is surrounded by the substrate which region serves as a base zone and has a conductivity type opposite to that of the substrate. A connection contact connected to the emitter is provided on this region and a modulatable resistance is formed between the connection contact and the active base zone by the region.
摘要翻译：保护的集成电路包括两个供电电极，输出电极和输入电极。在两个电极之间提供了一种具有横向双极晶体管的保护电路，其发射极和集电极区分别连接到所述电极。双极晶体管设置在由衬底围绕的区域中，该区域用作基极区并且具有与衬底相反的导电类型。在该区域上设置连接到发射器的连接触点，并且在该区域之间在连接触点和活性基区之间形成可调制电阻。

60. 发明授权

US3766446A Integrated circuits comprising lateral transistors and process for fabrication thereof 失效
标题翻译：包含横向晶体管的集成电路及其制造方法
公开(公告)号：US3766446A
公开(公告)日：1973-10-16
申请号：US3766446D
申请日：1970-11-18
申请人： KOGYO GIJUTSUIN
发明人： TARUI T , KOMIYA Y
IPC分类号： H01L21/00 , H01L27/00 , H01L27/07 , H01L19/00
CPC分类号： H01L27/0722 , H01L21/00 , H01L27/00 , Y10S148/037 , Y10S148/053 , Y10S148/085 , Y10S148/096 , Y10S148/106 , Y10S148/136 , Y10S148/145 , Y10S148/151
摘要： A ''''lateral'''' transistor for use in integrated circuits may have its base region formed by a technique of ''''ion implantation'''' with or without a step of impurity diffusion or, alternatively, by two steps of impurity diffusion including the formation of the so-called ''''buried'''' layer. In either case an emitter region is double-diffused into the base region simultaneously with collector diffusion, in such a manner that the base width of the lateral transistor is defined by a difference between the lengths of the double diffusion. The aforesaid ion implantation and buried layer techniques are utilized in the fabrication of integrated circuits incorporating such lateral transistors, in which base regions and isolation regions are formed at the same time. In other integrated circuits also disclosed herein, the lateral transistors together with or without field-effect transistors are isolated by means of substrate having higher resistivity than the base regions of the transistors.
摘要翻译：用于集成电路的“横向”晶体管可以通过具有或不具有杂质扩散步骤的或具有杂质扩散步骤的“离子注入”技术形成其基极区域，或者可选地，通过两个步骤的杂质扩散，包括形成所谓的 “埋”层。在任一情况下，发射极区域与集电极扩散同时扩散到基极区域中，使得横向晶体管的基极宽度由双扩散长度之间的差定义。上述离子注入和掩埋层技术用于结合这样的横向晶体管的集成电路的制造，其中同时形成基极区域和隔离区域。在本文也公开的其他集成电路中，通过具有比晶体管的基极区更高的电阻率的衬底来隔离与场效应晶体管一起或不与场效应晶体管连接的横向晶体管。

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