专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US06552564B1 Technique to reduce reflections and ringing on CMOS interconnections 失效
标题翻译：减少CMOS互连反射和振铃的技术
公开(公告)号：US06552564B1
公开(公告)日：2003-04-22
申请号：US09385383
申请日：1999-08-30
申请人： Leonard Forbes , Kie Y. Ahn
发明人： Leonard Forbes , Kie Y. Ahn
IPC分类号： H03K19092
CPC分类号： H05K1/025 , H01L23/5222 , H01L23/647 , H01L2924/0002 , H01L2924/3011 , H05K1/0216 , H05K3/107 , H05K2201/09036 , H01L2924/00
摘要： The present invention provides a method and apparatus, for integrated circuit or printed circuit board interconnections, which is able to minimize the reflections and ringing with minimal delay of signals which are propagated through transmission lines to destination points within the circuit or board. The invention utilizes interconnection lines which are designed to have a resistivity, line length, and line cross sectional area which produces a resistance of the interconnection line which will minimize the ringing and reflections with minimal delay of the signal propagated to the destination points to insure signal quality.
摘要翻译：本发明提供了一种用于集成电路或印刷电路板互连的方法和装置，其能够以通过传输线传播到电路或电路板内的目标点的信号的最小延迟来最小化反射和振铃。本发明利用被设计为具有电阻率，线路长度和线路横截面积的互连线路，其产生互连线路的电阻，这将使传播到目的地点的信号的最小延迟最小化振铃和反射以确保信号质量。

52. 发明申请

US20030072140A1 Resistive element apparatus and method 有权
标题翻译：电阻元件装置及方法
公开(公告)号：US20030072140A1
公开(公告)日：2003-04-17
申请号：US09977124
申请日：2001-10-12
申请人： Intel Corporation
发明人： Chee-Yee Chung , Robert L. Sankman , Alex Waizman
IPC分类号： H05K007/06 , H05K003/30
CPC分类号： H05K1/167 , H01L23/50 , H01L23/647 , H01L2924/0002 , H01L2924/3011 , H05K1/0231 , H05K1/095 , H05K1/115 , H05K3/429 , H05K2201/0317 , H05K2201/09309 , H05K2201/0949 , H05K2201/0979 , H05K2201/10636 , Y02P70/611 , Y10T29/4913 , Y10T29/49155 , H01L2924/00
摘要： A resistive element, a circuit board, and a circuit package, as well as a method of adding a resistive element to a circuit board are described. The resistive element includes a first contact point connected to a capacitor terminal, a second contact point connected to a circuit board plane, and resistive material connected to the first and second contact points. The invention may also include a circuit board with one or more resistive elements, as well as a circuit package, such as an integrated circuit or a discrete bypass capacitor, including one or more resistive elements, applied to an outside surface. The value of resistance for the resistive element can be selected by design to have a predetermined relationship with the equivalent resistance of an associated circuit board and connecting circuitry.
摘要翻译：描述了电阻元件，电路板和电路封装以及将电阻元件添加到电路板的方法。电阻元件包括连接到电容器端子的第一接触点，连接到电路板平面的第二接触点和连接到第一和第二接触点的电阻材料。本发明还可以包括具有一个或多个电阻元件的电路板，以及包括施加到外表面的一个或多个电阻元件的电路封装，例如集成电路或分立旁路电容器。可以通过设计来选择电阻元件的电阻值以与相关联的电路板和连接电路的等效电阻具有预定的关系。

53. 发明授权

US06351391B1 Signal busses on printed board structures mounting ASIC chips with signal termination resistor devices using planar signal terminating devices 有权
标题翻译：在印刷电路板结构上的信号总线，使用平面信号端接装置安装具有信号终端电阻器件的ASIC芯片
公开(公告)号：US06351391B1
公开(公告)日：2002-02-26
申请号：US09571956
申请日：2000-05-15
申请人： Clint A. Beliveau , Wallace D. Doeling
发明人： Clint A. Beliveau , Wallace D. Doeling
IPC分类号： H05K710
CPC分类号： H05K1/167 , H01L23/647 , H01L24/48 , H01L2224/05599 , H01L2224/16225 , H01L2224/16235 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/15174 , H01L2924/15184 , H01L2924/15311 , H05K1/023 , H05K1/0246 , H05K1/0298 , H05K1/141 , H05K2201/049 , H05K2201/10734 , H01L2224/45015 , H01L2924/207 , H01L2924/00
摘要： A printed circuit board structure is provided where there is a circuitized dielectric substrate having a plurality of signal traces thereon. The circuitized substrate has first and second opposite faces. An ASIC chip assembly is mounted on the first face and connected to the surface by solder connections. Preferably, the ASIC chip assembly is mounted on the substrate as an IC chip mounted on a chip carrier with the chip carrier being mounted to the circuit board by solder connections, preferably in the form of a ball grid array. In one embodiment, a discrete signal termination device is provided which is disposed on the second face of the circuitized substrate directly opposite the ASIC chip assembly. In another embodiment, a discrete signal termination device is disposed between the ASIC chip assembly and the printed circuit board. The signal termination device includes a plurality of planar resistors embedded in a dielectric material with the resistors being electrically connected to the signal lines on the circuitized substrate, preferably by solder connections, again in the form of a ball grid array. In yet another embodiment, the signal termination device is formed as a part of the ASIC chip assembly by being incorporated in the chip carrier In all cases, the signal termination device need not be formed as a part of the circuit board but can be formed in discrete individual segments for attachment to either the circuit board or formed as part of the chip carrier, thus utilizing the entire structure of the termination device to form resistors.
摘要翻译：提供了一种印刷电路板结构，其中存在其上具有多个信号迹线的电路化电介质基板。电路化基板具有第一和第二相对面。 ASIC芯片组件安装在第一面上，并通过焊接连接连接到表面。优选地，ASIC芯片组件作为安装在芯片载体上的IC芯片安装在基板上，其中芯片载体通过焊接连接安装到电路板，优选地以球栅阵列的形式。在一个实施例中，离散提供信号终端装置，其设置在与ASIC芯片组件正对的电路化基板的第二面上。在另一个实施例中，离散信号终端装置设置在ASIC芯片组件和印刷电路板之间。信号终端装置包括嵌入电介质材料中的多个平面电阻器，其中电阻器电连接到电路化的衬底，优选地通过焊料连接，再次以球栅阵列的形式。在另一个实施例中，信号终端装置通过结合在芯片载体中而形成为ASIC芯片组件的一部分。在所有情况下，信号终端装置不需要形成为电路板的一部分，而是可以形成在离散的各个片段中，用于附接到电路板或形成为芯片载体的一部分，从而利用终端装置的整个结构来形成电阻器。

54. 发明授权

US06150615A Economical package with built-in end resistor used for semiconductor device and process of fabrication 失效
标题翻译：具有内置终端电阻器的经济封装，用于半导体器件和制造工艺
公开(公告)号：US06150615A
公开(公告)日：2000-11-21
申请号：US71194
申请日：1998-05-04
申请人： Katsunobu Suzuki
发明人： Katsunobu Suzuki
IPC分类号： H01L23/12 , H01L23/31 , H01L23/498 , H01L23/64 , H05K1/16 , H01L23/02
CPC分类号： H01L23/49827 , H01L23/3121 , H01L23/647 , H01L2224/05553 , H01L2224/05554 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48465 , H01L2224/49171 , H01L2224/49433 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/01004 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01037 , H01L2924/01078 , H01L2924/01079 , H01L2924/12044 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/3011 , H01L2924/30111
摘要： A lead frame used for a semiconductor chip has built-in end resistors accurately patterned through lithographic techniques and an etching from a conductive bonding layer between an insulating film and a conductive metallic foil, the conductive metallic foil is patterned into a conductive island for a semiconductor chip and conductive strips for electric signals, and the built-in end resistors achieve impedance matching for the electric signals.
摘要翻译：用于半导体芯片的引线框架具有通过光刻技术精确地图案化的内置末端电阻和从绝缘膜和导电金属箔之间的导电接合层的蚀刻，将导电金属箔图案化成用于半导体的导电岛用于电信号的芯片和导电条，并且内置端电阻器实现电信号的阻抗匹配。

55. 发明授权

US6037654A Semiconductor device, tape carrier package, and display panel module 失效
标题翻译：半导体器件，载带封装和显示面板模块
公开(公告)号：US6037654A
公开(公告)日：2000-03-14
申请号：US704513
申请日：1996-11-27
申请人： Tsuyoshi Tamura
发明人： Tsuyoshi Tamura
IPC分类号： G02F1/1345 , G02F1/1362 , H01L23/495 , H01L23/498 , H01L23/60 , H01L23/64 , H01L23/48 , H01L23/52 , H01L29/04
CPC分类号： H01L23/49572 , H01L23/4985 , H01L23/60 , H01L23/647 , H01L24/50 , G02F1/1345 , G02F1/136204 , H01L2224/16 , H01L2924/01078 , H01L2924/01079 , H01L2924/181
摘要： Electrodes for electrically connecting to the outside are formed along one long side of a rectangular semiconductor chip 20. The electrodes are arranged in two rows, one of output terminals 21 and the other of input terminals 22 and power supply terminals 23, or are arranged in one row of the output terminals, input terminals and power supply terminals. Input protective resistors and static electricity protective diodes 28 for the input terminals are located outside the output terminals to be separated from the output system by at least the size of the output terminals. The external circuit connected to the output terminals 21 of the semiconductor device, for example the wiring 35 extending from the inner leads 33 of a tape carrier 29 are routed inside the electrodes toward the opposite long side of the semiconductor device, so that the wiring area overlaps the top of the semiconductor device in a plan view. Therefore, the mounting area of the semiconductor device can be largely reduced, the package density can be increased, and the longitudinal dimension of a TCP can be minimized.
摘要翻译： PCT No.PCT / JP96 / 00040 Sec。 371日期：1996年11月27日 102（e）1996年11月27日PCT PCT 1996年1月12日PCT公布。公开号WO96 / 21948 日期1996年7月18日沿着矩形半导体芯片20的一个长边形成电连接到外部的电极。电极排列成两行，一个输出端子21，另一个输入端子22和电源端子23 或者排列在一排输出端子，输入端子和电源端子中。输入端子的输入保护电阻和静电保护二极管28位于输出端外部，至少与输出端的大小分离。连接到半导体器件的输出端子21的外部电路，例如从带载体29的内部引线33延伸的布线35，在电极内部被引导到半导体器件的相对的长边，使得布线区域在平面图中与半导体器件的顶部重叠。因此，半导体器件的安装面积可以大大降低，可以提高封装密度，并且可以使TCP的纵向尺寸最小化。

56. 发明授权

US5841584A Dielectric multilayered reflector 失效
标题翻译：介电多层反射器
公开(公告)号：US5841584A
公开(公告)日：1998-11-24
申请号：US639989
申请日：1996-04-26
申请人： Kunihiro Takatani , Toshiyuki Okumura
发明人： Kunihiro Takatani , Toshiyuki Okumura
IPC分类号： H01S5/00 , H01L23/64 , H01S5/028 , G02B1/10
CPC分类号： G02B5/0833 , H01L23/647 , H01S5/028 , H01L2924/0002 , H01S5/0281 , H01S5/0282
摘要： The dielectric multilayered reflector of the invention is formed on at least one of two emitting surfaces of a semiconductor laser device. The dielectric multilayered reflector includes: a multilayered structure formed by stacking a plurality of layers; and a layer made of magnesium difluoride. In this dielectric multilayered reflector, the multilayered structure includes at least one layer made of an oxide dielectric material and the layer made of magnesium difluoride is formed on a surface of an outermost layer of the multilayered structure.
摘要翻译：本发明的电介质多层反射器形成在半导体激光器件的两个发射表面中的至少一个上。电介质多层反射器包括：通过堆叠多个层而形成的多层结构; 和由二氟化镁制成的层。在该电介质多层反射器中，多层结构包括由氧化物介电材料制成的至少一层，并且在多层结构的最外层的表面上形成由二氟化镁制成的层。

57. 发明授权

US5530270A Substrate for semiconductr device 失效
标题翻译：半导体器件基板
公开(公告)号：US5530270A
公开(公告)日：1996-06-25
申请号：US799247
申请日：1991-11-27
申请人： Yoshiharu Takahashi , Eitaro Nagai
发明人： Yoshiharu Takahashi , Eitaro Nagai
IPC分类号： H01C7/00 , H01L21/02 , H01L23/31 , H01L23/64 , H01L27/01 , H01L27/08 , H01L29/74 , H01L23/62 , H01L27/11 , H01L31/111
CPC分类号： H01L28/20 , H01L23/3171 , H01L23/647 , H01L27/0802 , H01L2924/0002 , Y10S257/904
摘要： A semiconductor substrate includes a plurality of parallel resistor films connected between a pair of conductor strips. The resistor films and conductor strips are coated with a protective coat. The resistor films are cut one by one by laser trimming to adjust the total resistance value of the plurality of parallel resistor films. The protective coat on the uncut resistors remains unremoved.
摘要翻译：半导体衬底包括连接在一对导体条之间的多个并联电阻膜。电阻膜和导体条涂有防护层。通过激光修整逐个切割电阻膜，以调整多个并联电阻膜的总电阻值。未切割电阻器上的保护层保持不动。

58. 发明授权

US5394008A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5394008A
公开(公告)日：1995-02-28
申请号：US84520
申请日：1993-06-30
申请人： Yutaka Ito , Toshiyuki Sakuta , Takumi Nasu
发明人： Yutaka Ito , Toshiyuki Sakuta , Takumi Nasu
IPC分类号： H01L23/12 , H01L23/495 , H01L23/50 , H01L23/64 , H01L23/48 , H01L25/52 , H01L29/44 , H01L29/60
CPC分类号： H01L24/06 , H01L23/4951 , H01L23/647 , H01L24/49 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/06136 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48253 , H01L2224/48624 , H01L2224/49113 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01004 , H01L2924/01013 , H01L2924/01015 , H01L2924/01033 , H01L2924/01041 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025
摘要： A semiconductor integrated circuit device with high power noise immunity and high substrate surge immunity. An LOC lead frame to be connected to a power wiring for supplying a source voltage and a ground potential to input circuits of a semiconductor chip is isolated from another LOC lead frame for supplying the source voltage and the ground potential to other circuits. The source voltage and the ground potential for the circuit are supplied by way of external terminals formed by the respective lead frames. Further, the isolated LOC lead frames are connected to each other through a resistive impedance component formed on the semiconductor chip.
摘要翻译：一种半导体集成电路器件，具有高功率噪声抗扰度和高衬底浪涌抗扰度。要连接到用于向半导体芯片的输入电路提供源极电压和接地电位的电源线的LOC引线框架与用于向其他电路提供源极电压和接地电位的另一个LOC引线框架隔离。电路的源极电压和接地电位通过由各个引线框构成的外部端子来提供。此外，隔离的LOC引线框架通过形成在半导体芯片上的电阻阻抗部件彼此连接。

59. 发明授权

US5382827A Functional substrates for packaging semiconductor chips 失效
标题翻译：用于封装半导体芯片的功能基板
公开(公告)号：US5382827A
公开(公告)日：1995-01-17
申请号：US927151
申请日：1992-08-07
申请人： Wen-chou V. Wang , William T. Chou
发明人： Wen-chou V. Wang , William T. Chou
IPC分类号： H01L23/538 , H01L23/58 , H01L23/64 , H01L27/02 , H01L23/16 , H01L23/48 , H01L29/41
CPC分类号： H01L23/647 , H01L23/5385 , H01L23/585 , H01L2224/16 , H01L2924/01078 , H01L2924/01079
摘要： A semiconductor chip carrier has a first substrate and at least one second substrate. The first substrate is for carrying at least one semiconductor chip of integrated circuits. The first substrate has predetermined functional elements for connection to the integrated circuits of the at least one semiconductor chip. Such a second substrate is directly coupled to the first substrate. The second substrate is capable of being independently created and has predetermined electrical functional elements for connection to the integrated circuits of the semiconductor chip. The electrical functional elements of each second substrate are of one type and are different than the electrical functional elements of the other second substrates and the first substrate.The second substrate has a top interconnect layer, a bottom interconnect layer, and a plurality of intra-substrate connectors (or through-hole connectors), where the top interconnect layer and the bottom interconnect layer have substantially identical patterns of electrical contacts. The electrical contacts may be deformable bumps, solder bumps, elastomer bumps, or gold bumps.The electrical functional elements are electrically passive circuits, such as capacitors, resistors, or electrical signal conductors. Such a second substrate may include power supply circuits.
摘要翻译：半导体芯片载体具有第一基板和至少一个第二基板。第一衬底用于承载集成电路的至少一个半导体芯片。第一衬底具有用于连接至少一个半导体芯片的集成电路的预定功能元件。这样的第二衬底直接耦合到第一衬底。第二基板能够独立地形成并且具有用于连接到半导体芯片的集成电路的预定的电功能元件。每个第二基板的电功能元件是一种类型的并且不同于其它第二基板和第一基板的电功能元件。第二衬底具有顶部互连层，底部互连层和多个衬底内连接器（或通孔连接器），其中顶部互连层和底部互连层具有基本相同的电触点图案。电触头可以是可变形的凸块，焊料凸块，弹性体凸块或金凸块。电功能元件是诸如电容器，电阻器或电信号导体的无源电路。这样的第二基板可以包括电源电路。

60. 发明授权

US5212403A Integrated circuit device having an ic chip mounted on the wiring substrate and having suitable mutual connections between internal circuits 失效
标题翻译：具有安装在接线基板上并具有内部电路之间的适当互连的IC芯片的集成电路设备
公开(公告)号：US5212403A
公开(公告)日：1993-05-18
申请号：US755652
申请日：1991-09-06
申请人： Keiichirou Nakanishi , Minoru Yamada , Tatsuya Saitoh , Kazumichi Yamamoto
发明人： Keiichirou Nakanishi , Minoru Yamada , Tatsuya Saitoh , Kazumichi Yamamoto
IPC分类号： H01L21/3205 , H01L23/498 , H01L23/52 , H01L23/538 , H01L23/64
CPC分类号： H01L23/498 , H01L23/49822 , H01L23/647 , H01L2224/16 , H01L2924/15312
摘要： This invention discloses an integrated circuit device including an integrated circuit chip having logic circuits formed therein and a wiring substrate for mounting thereon the integrated circuit chip. The wiring substrate has signal wirings for connecting mutually input terminals and output terminals of the integrated circuit chip. The integrated circuit device includes signal wirings for effecting connections of the input terminals and output terminals of the same integrated circuit chip inside the wiring substrate. The logic circuits inside the same integrated circuit chip are mutually connected by signal wirings formed inside the integrated circuit chip when a wiring length is small, and are mutually connected by signal wirings formed inside the wiring substrate when the wiring length is great.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式