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51. 发明授权

US5206826A Floating-point division cell 失效
标题翻译：浮点分割单元格
公开(公告)号：US5206826A
公开(公告)日：1993-04-27
申请号：US787926
申请日：1991-11-06
申请人： Junji Mori , Masato Nagamatsu , Itaru Yamazaki , Yoshihisa Kondo , Nobuhiro Ide , Takeshi Yoshida
发明人： Junji Mori , Masato Nagamatsu , Itaru Yamazaki , Yoshihisa Kondo , Nobuhiro Ide , Takeshi Yoshida
IPC分类号： G06F7/537 , G06F7/483 , G06F7/506 , G06F7/52 , G06F7/535
CPC分类号： G06F7/535 , G06F2207/382 , G06F2207/5352 , G06F7/4873
摘要： A floating-point division cell consisting of partial remainder data register for storing parallel-partial-remainder data or third partial remainder data, divisor data register for storing parallel-divisor data or third divisor data, low-order divisor data generator for receiving the low-order portion of the divisor data and generating low-order divisor data, low-order partial remainder calculator for obtaining low-order multi-divisor data by multiplying the low-order divisor data and a multiple of 2 together and calculating new low-order partial remainder data by subtracting or adding the low-order multi-divisor data from/to the low-order portion of the partial remainder data, high-order divisor data generator for receiving the high-order portion of the divisor data and generating high-order divisor data, and high-order partial remainder calculator for obtaining high-order multi-divisor data by multiplying the high-order divisor data and a multiple of 2 together and calculating new high-order partial remainder data by subtracting or adding the high-order multi-divisor data from/to the high-order portion of the partial remainder data.
摘要翻译：由部分余数数据寄存器组成的浮点分割单元，用于存储并行余数数据或第三部分余数数据，用于存储并行除数数据或第三除数数据的除数数据寄存器，用于接收低电平的低位除数数据发生器除数数据的低阶部分和低阶除数数据，低阶部分余数计算器，用于通过将低阶除数数据和2的倍数相乘并计算新的低阶数来获得低阶多因子数据通过从部分余数数据的低位部分中减去或添加低阶多因子数据的部分余数数据，高阶除数数据发生器，用于接收除数数据的高阶部分，高阶除数数据和高阶部分余数计算器，用于通过将高阶除数数据和2的倍数相乘在一起来获得高阶多因子数据，并计算新的高除数数据通过从/部分余数数据的高阶部分中减去或添加高阶多因数数据，来获得h阶部分余数数据。

52. 发明授权

US5151993A Data processor performing operation on data having length shorter than one-word length 失效
标题翻译：数据处理器对长度比一字长的数据进行操作
公开(公告)号：US5151993A
公开(公告)日：1992-09-29
申请号：US321399
申请日：1989-03-10
申请人： Hitoshi Yamahata
发明人： Hitoshi Yamahata
IPC分类号： G06F12/04 , G06F7/00 , G06F7/57 , G06F9/30 , G06F9/302 , G06F9/318
CPC分类号： G06F7/57 , G06F9/30014 , G06F9/30192 , G06F2207/382
摘要： A data processor for executing an instruction designating a half-word length operation or a quarter-word length operation in addition to one-word length operation is disclosed. This processor includes an operation unit performing an operation on data applied thereto and producing result data, a blocking register temporarily storing more significant bits data of a destination register, a first output circuit outputting less significant bits data of the result data when the half-word length operation or the quarter-word length operation is designated, and a second output circuit operatively outputting the data of the blocking register. The ouputs of the first and second circuits are then combined and written into the destination area.

53. 发明授权

US5047973A High speed numerical processor for performing a plurality of numeric functions 失效
标题翻译：用于执行多个数字功能的高速数字处理器
公开(公告)号：US5047973A
公开(公告)日：1991-09-10
申请号：US343465
申请日：1989-04-26
申请人： Donald E. Steiss , Maria B. Hipona , Henry M. Darley
发明人： Donald E. Steiss , Maria B. Hipona , Henry M. Darley
IPC分类号： G06F7/537 , G06F7/52 , G06F7/53 , G06F7/535 , G06F7/552 , G06F7/57
CPC分类号： G06F7/5324 , G06F7/535 , G06F7/5525 , G06F7/57 , G06F2207/382 , G06F2207/5355
摘要： Division and square root calculations are performed using an operand routing circuit (16) for receiving an operand N, and operand D and a seed value S and directing the operands and seed value to a multiplier (38). Single multiplier (38) is configured into two arrays for calculating partial products of N and S and D and S. The results of multiplier (38) are transmitted through switching circuitry (20) or registers (48) (50) either to operand routing circuitry (16) or adder (44) depending on a convergence algorithm. The final result is rounded.

54. 发明授权

US4901267A Floating point circuit with configurable number of multiplier cycles and variable divide cycle ratio 失效
标题翻译：浮点电路，具有可配置的乘法器周期数和可分的分频周期比
公开(公告)号：US4901267A
公开(公告)日：1990-02-13
申请号：US167802
申请日：1988-03-14
申请人： Mark Birman , George K. Chu , Fred A. Ware , Selfia Halim
发明人： Mark Birman , George K. Chu , Fred A. Ware , Selfia Halim
IPC分类号： G06F7/487 , G06F1/12 , G06F7/527 , G06F7/53 , G06F7/535 , G06F7/537 , G06F7/552 , G06F7/57 , G06F9/302 , G06F9/38
CPC分类号： G06F9/3885 , G06F1/12 , G06F7/483 , G06F7/57 , G06F9/30014 , G06F2207/382 , G06F2207/3884
摘要： The present invention optimizes the number and ratio of cycles required among the divide/square root unit, multiplier unit and ALU. An intermediate latch with its own clock is provided at the output of the multiplier half-array in the intermediate stage to feed back data for a second pass for double-precision numbers. The multiplier can then be adjusted for either two-cycle latency mode (for optimizing double-precision multiplies) or three-cycle latency mode (for optimizing single-precision multiplies). A separate divide clock is used for the divide/square root unit, and is synchronized with the multiplier cycle clock on input and output. This allows the divide time to be optimized so that it requires fewer clock cycles when a longer multiplier clock cycle time is used.
摘要翻译：本发明优化了除法/平方根单元，乘法器单元和ALU之间所需的周期数和比率。在中间级的乘法器半阵列的输出处提供具有其自己的时钟的中间锁存器，以反馈用于双精度数字的第二遍的数据。然后可以针对两周期延迟模式（优化双精度乘法）或三周期延迟模式（用于优化单精度乘数）来调整乘数。分频/平方根单位使用单独的分频时钟，并与输入和输出的乘法器周期时钟同步。这样可以优化分频时间，以便在使用较长的乘法器时钟周期时，需要较少的时钟周期。

55. 发明授权

US4815021A Multifunction arithmetic logic unit circuit 失效
标题翻译：多功能运算逻辑单元电路
公开(公告)号：US4815021A
公开(公告)日：1989-03-21
申请号：US824053
申请日：1986-01-30
申请人： Walter R. Steiner , Paul A. Simoncic
发明人： Walter R. Steiner , Paul A. Simoncic
IPC分类号： G06F7/38 , G06F7/483 , G06F7/508 , G06F7/57 , G06T15/40 , H03M7/24
CPC分类号： G06F7/483 , G06F7/57 , G06T15/405 , H03M7/24 , G06F2207/382 , G06F2207/3884 , G06F7/4991
摘要： A multifunction arithmetic logic circuit having comparison and numeric conversion circuitry, particularly adapted for use in graphics processing. The inventive architecture comprises a modular arithmetic logic unit in a pipelined architecture circuit. Functions performed are conversion of floating point numbers to fixed point numbers, and vise versa, arithmetic and logical operations, and numeric comparison operations. A visibility logic subcircuit is included for rapidly tracking numeric comparisons to indicate whether a graphics object is to be considered visible, partially visible, or invisible.
摘要翻译：具有比较和数字转换电路的多功能运算逻辑电路，特别适用于图形处理。本发明的架构包括流水线架构电路中的模块化算术逻辑单元。执行的功能是将浮点数转换为固定点数，反之亦然，算术和逻辑运算以及数值比较运算。包括可见性逻辑子电路，用于快速跟踪数字比较，以指示是否将图形对象视为可见，部分可见或不可见。

56. 发明授权

US3956620A Adder with carry enable for bit operations in an electric digital calculator 失效
标题翻译：具有进位使能的加法器用于电子数字计算器中的位操作
公开(公告)号：US3956620A
公开(公告)日：1976-05-11
申请号：US527506
申请日：1974-11-26
申请人： George L. Brantingham , Larry T. Novak
发明人： George L. Brantingham , Larry T. Novak
IPC分类号： G06F7/50 , G06F7/505 , G06F15/02
CPC分类号： G06F7/505 , G06F15/02 , G06F7/50 , G06F2207/382
摘要： A greatly simplified calculator circuit implemented, for example, utilizing I.sup.2 L technology is fabricated on a relatively small semiconductor chip resulting in high yield. A unique feature of such calculator is a dual adder which selectively functions as a multibit word adder and also as a plurality of single bit adders. This dual functioning adder cooperates with the calculator system in such a manner as to reduce the total amount of circuitry required to implement the calculator function thereby permitting fabrication on the smaller chip. The dual adder is utilized, for example, to perform bit operations for use in flagging and 2's complement addition for subtraction operations as well as normal multibit word addition.
摘要翻译：例如利用I2L技术实现的大大简化的计算器电路被制造在相对较小的半导体芯片上，导致高产率。这种计算器的独特特征是双加法器，其选择性地用作多位字加法器，并且还用作多个单位加法器。这种双功能加法器以这样的方式与计算器系统配合，以减少实现计算器功能从而允许在较小芯片上制造所需的电路的总量。例如，双加法器用于执行用于标记的位操作和用于减法运算以及正常多位字相加的2补数相加。

57. 发明授权

US3331954A Computer performing serial arithmetic operations having a parallel-type static memory 失效
标题翻译：执行具有并行型静态存储器的串行算术运算的计算机
公开(公告)号：US3331954A
公开(公告)日：1967-07-18
申请号：US39270864
申请日：1964-08-28
申请人： GEN PRECISION INC
发明人： KINZIE JAMES E , PROSS JR JOHN W , STEVES ROBERT B , TROSTRUD ARVILLE T
IPC分类号： G06F5/01 , G06F7/57 , G06F15/78
CPC分类号： G06F7/57 , G06F5/01 , G06F15/78 , G06F2207/382

58. 发明授权

US3234370A Segmented arithmetic device 失效
标题翻译：分段算术装置
公开(公告)号：US3234370A
公开(公告)日：1966-02-08
申请号：US18346262
申请日：1962-03-29
申请人： ERICKSON GERALD J
发明人： ERICKSON GERALD J
IPC分类号： G06F7/50 , G06F7/505
CPC分类号： G06F7/505 , G06F2207/382 , G06F2207/3836

59. 发明申请

US20180321909A1 VARIABLE PRECISION FLOATING-POINT MULTIPLIER 审中-公开
公开(公告)号：US20180321909A1
公开(公告)日：2018-11-08
申请号：US16039029
申请日：2018-07-18
申请人： Altera Corporation
发明人： Martin Langhammer
IPC分类号： G06F7/487 , G06F7/485
CPC分类号： G06F7/4876 , G06F7/485 , G06F2207/3816 , G06F2207/382 , G06F2207/483
摘要： Integrated circuits with specialized processing blocks are provided. The specialized processing blocks may include floating-point multiplier circuits that can be configured to support variable precision. A multiplier circuit may include a first carry-propagate adder (CPA), a second carry-propagate adder (CPA), and an associated rounding circuit. The first CPA may be wide enough to handle the required precision of the mantissa. In a bridged mode, the first CPA may borrow an additional bit from the second CPA while the rounding circuit will monitor the appropriate bits to select the proper multiplier output. A parallel prefix tree operable in a non-bridged mode or the bridged mode may be used to compute multiple multiplier outputs. The multiplier circuit may also include exponent and exception handling circuitry using various masks corresponding to the desired precision width.

60. 发明申请

US20180278250A1 ON-THE-FLY PROCESSING OF DATA IN AN ACQUISITION SYSTEM 审中-公开
公开(公告)号：US20180278250A1
公开(公告)日：2018-09-27
申请号：US15927027
申请日：2018-03-20
申请人： Commissariat à I'Energie Atomique et aux Energies Alternatives
发明人： Daniele JAHIER PAGLIARI , Edith BEIGNE , Yves DURAND , Massimo PONCINO
IPC分类号： H03K19/00 , H03K3/011
CPC分类号： H03K19/0016 , G06F7/38 , G06F2207/382 , H03K3/011 , H03K2217/0018
摘要： The invention concerns a circuit comprising: a processing circuit (102) comprising a plurality of circuit domains (103), each circuit domain (103) comprising a plurality of transistors and being configured to apply one or more corresponding transistor biasing voltages to said transistors; and a control circuit (104) configured to determine, based on at least a selected accuracy setting of the processing circuit, the level of said one or more transistor biasing voltages to be applied in each of said circuit domains, the control circuit (104) being further configured to cause said transistor biasing voltages to be applied to the circuit domains.

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