专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US3956620A Adder with carry enable for bit operations in an electric digital calculator 失效
标题翻译：具有进位使能的加法器用于电子数字计算器中的位操作
公开(公告)号：US3956620A
公开(公告)日：1976-05-11
申请号：US527506
申请日：1974-11-26
申请人： George L. Brantingham , Larry T. Novak
发明人： George L. Brantingham , Larry T. Novak
IPC分类号： G06F7/50 , G06F7/505 , G06F15/02
CPC分类号： G06F7/505 , G06F15/02 , G06F7/50 , G06F2207/382
摘要： A greatly simplified calculator circuit implemented, for example, utilizing I.sup.2 L technology is fabricated on a relatively small semiconductor chip resulting in high yield. A unique feature of such calculator is a dual adder which selectively functions as a multibit word adder and also as a plurality of single bit adders. This dual functioning adder cooperates with the calculator system in such a manner as to reduce the total amount of circuitry required to implement the calculator function thereby permitting fabrication on the smaller chip. The dual adder is utilized, for example, to perform bit operations for use in flagging and 2's complement addition for subtraction operations as well as normal multibit word addition.
摘要翻译：例如利用I2L技术实现的大大简化的计算器电路被制造在相对较小的半导体芯片上，导致高产率。这种计算器的独特特征是双加法器，其选择性地用作多位字加法器，并且还用作多个单位加法器。这种双功能加法器以这样的方式与计算器系统配合，以减少实现计算器功能从而允许在较小芯片上制造所需的电路的总量。例如，双加法器用于执行用于标记的位操作和用于减法运算以及正常多位字相加的2补数相加。

2. 发明授权

US3939335A Universal condition latch in an electronic digital calculator 失效
标题翻译：通用条件锁定在电子数字计算器
公开(公告)号：US3939335A
公开(公告)日：1976-02-17
申请号：US527510
申请日：1974-11-26
申请人： George L. Brantingham , Louis H. Phillips , Larry T. Novak
发明人： George L. Brantingham , Louis H. Phillips , Larry T. Novak
IPC分类号： G06F7/50 , G06F9/32 , G06F15/02
CPC分类号： G06F9/30094 , G06F7/50
摘要： A greatly simplified calculator circuit implemented, for example, utilizing I.sup.2 L technology, is fabricated on a relatively small semiconductor chip resulting in high yield. A unique feature of such calculator is a universal condition latch which is so connected as to permit the state thereof to be determined by multiple sources while reducing the number of ROM instructions required and hence the size of the ROM to permit fabrication on the smaller chip. The condition latch state is determined, for example, by the logical OR of up to four flags after a test flag instruction, by the logical OR of up to four keyboard inputs after a test key instruction, by the carry output of the adder after any add instruction, or by the results of an adder compare after any compare instruction.
摘要翻译：例如利用I2L技术实现的大大简化的计算器电路被制造在相对小的半导体芯片上，导致高产量。这种计算器的独特特征是通用条件锁存器，其被连接以允许其状态由多个源确定，同时减少所需的ROM指令的数量，并因此减小ROM的大小以允许在较小的芯片上制造。条件锁存状态例如通过在测试标志指令之后的最多四个标志的逻辑或由测试键指令之后的多达四个键盘输入的逻辑或由任何加法器的进位输出之后确定在任何比较指令之后，加法指令，或加法器比较结果。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式