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51. 发明授权

US07630309B1 Systems and methods for limiting the rates of data to/from a buffer 有权
标题翻译：用于限制缓冲区数据的速率的系统和方法
公开(公告)号：US07630309B1
公开(公告)日：2009-12-08
申请号：US11462215
申请日：2006-08-03
申请人： Raymond Marcelino Manese Lim , Song Zhang , Anurag P. Gupta , Brian Gaudet
发明人： Raymond Marcelino Manese Lim , Song Zhang , Anurag P. Gupta , Brian Gaudet
IPC分类号： G06F11/00 , H04L12/43
CPC分类号： G06F5/06 , G06F2205/061
摘要： A system controls the transfer of data. The system receives a request to transfer data and determines whether a counter value equals or exceeds a threshold. The counter value represents an amount of time since a previous data transfer. When the counter value equals or exceeds the threshold, the system transmits the data. In another implementation, the system tracks the amount of data read from a buffer. The system reduces the speed at which data is read when the amount of data read from the buffer exceeds a threshold.
摘要翻译：系统控制数据传输。系统接收传送数据的请求，并确定计数器值是否等于或超过阈值。计数器值表示自先前数据传输以来的时间量。当计数器值等于或超过阈值时，系统发送数据。在另一个实现中，系统跟踪从缓冲器读取的数据量。当从缓冲区读取的数据量超过阈值时，系统会降低读取数据的速度。

52. 发明申请

US20090024864A1 AUDIO PROCESSOR HAVING DYNAMIC AUTOMATIC CONTROL FUNCTION OF OPERATING FREQUENCY 审中-公开
标题翻译：具有动态频率动态自动控制功能的音频处理器
公开(公告)号：US20090024864A1
公开(公告)日：2009-01-22
申请号：US12170521
申请日：2008-07-10
申请人： Hiroki SUGIMOTO
发明人： Hiroki SUGIMOTO
IPC分类号： G06F1/06 , G06F12/00
CPC分类号： G06F5/06 , G06F2205/061
摘要： A data processing system includes a processor for writing data processed based on a clock signal in a buffer for storing and outputting written data, and the processor changes a frequency of the clock signal supplied to the processor in accordance with an amount of data stored in the buffer.
摘要翻译：数据处理系统包括：处理器，用于将基于时钟信号处理的数据写入用于存储和输出写入数据的缓冲器中，并且处理器根据存储在存储器中的数据量改变提供给处理器的时钟信号的频率缓冲。

53. 发明申请

US20080034170A1 Method for Reading Out Sensor Data 有权
标题翻译：读出传感器数据的方法
公开(公告)号：US20080034170A1
公开(公告)日：2008-02-07
申请号：US11664379
申请日：2005-08-03
申请人： Christian Ohl , Andreas Fink , Maike Moldenhauer
发明人： Christian Ohl , Andreas Fink , Maike Moldenhauer
IPC分类号： G06F12/00
CPC分类号： G06F5/12 , B60R2021/01068 , G06F5/14 , G06F2205/061
摘要： A method is described for reading out sensor data from an intermediate memory written by at least one sensor to the intermediate memory at a data-transfer rate (Tpas). A sampling rate (Tsg) is selected in such a way as to avoid an overflow of the intermediate memory and all buffered sensor data is read into a control unit memory at the predetermined sampling rate (Tsg), the intermediate memory generating a message (RBE) if no new sensor data is present in the intermediate memory at the time of sampling.
摘要翻译：描述了一种用于以由数据传送速率（Tpas）从中间存储器读出由至少一个传感器写入的中间存储器的传感器数据的方法。选择采样率（Tsg）以避免中间存储器的溢出，并且所有缓冲的传感器数据以预定采样率（Tsg）被读入控制单元存储器，中间存储器产生消息（RBE ）如果在采样时没有新的传感器数据存在于中间存储器中。

54. 发明申请

US20070296617A1 Serial Interface Device and Image Forming Apparatus 失效
标题翻译：串行接口设备和图像形成设备
公开(公告)号：US20070296617A1
公开(公告)日：2007-12-27
申请号：US11751796
申请日：2007-05-22
申请人： Tatsuhiko Murata , Masayu Fujiwara , Tomoki Yamamoto , Takeshi Matsuzaki
发明人： Tatsuhiko Murata , Masayu Fujiwara , Tomoki Yamamoto , Takeshi Matsuzaki
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , G06F5/06 , G06F2205/061
摘要： A serial I/F has: a FIFO portion to which m- or n-bit (m
摘要翻译：串行I / F具有：基于PCLK写入m位或n位（m

55. 发明申请

US20070011327A1 Event buffering model for instrumentation providers 有权
标题翻译：仪表供应商的事件缓冲模型
公开(公告)号：US20070011327A1
公开(公告)日：2007-01-11
申请号：US11114310
申请日：2005-04-25
申请人： Michael Volodarsky , Patrick Ng
发明人： Michael Volodarsky , Patrick Ng
IPC分类号： G06F15/173
CPC分类号： G06F5/06 , G06F2205/061
摘要： Systems and methods for intermediate buffering of data for the purpose of controlling its delivery to the consumer. The systems and methods for buffering data can arbitrate between the incoming data flow from the generating component and the outgoing data flow to the consumer. In doing so, the systems and methods for buffering of data seek to honor the delivery demands and/or constraints of the consumer, while avoiding the loss of the data generated by the producer. The delivery demands of the consumer may include requirements pertaining to maximum acceptable incoming data rate, the desired incoming data rate, incoming data aggregation, the desired freshness of the data, and tolerance for event loss. The generation component constraints may include the space limitations on buffering data within the data buffer.
摘要翻译：用于中间缓冲数据的系统和方法，用于控制其传送给消费者。用于缓冲数据的系统和方法可以在来自生成组件的输入数据流和到消费者的输出数据流之间进行仲裁。在这样做时，用于缓冲数据的系统和方法旨在满足消费者的传递需求和/或限制，同时避免生产者生成的数据的丢失。消费者的传送需求可以包括关于最大可接受的输入数据速率，期望的输入数据速率，输入数据聚合，期望的数据新鲜度和事件丢失容限的要求。生成组件约束可以包括对数据缓冲器内的缓冲数据的空间限制。

56. 发明授权

US06993102B2 System and method for clock synchronization for USB sink device 失效
公开(公告)号：US06993102B2
公开(公告)日：2006-01-31
申请号：US09908979
申请日：2001-07-20
申请人： Steven Donald Spence , Nikolai Nikolov , Rudolf Ladyzhenski
发明人： Steven Donald Spence , Nikolai Nikolov , Rudolf Ladyzhenski
IPC分类号： H04L7/00
CPC分类号： G06F5/06 , G06F2205/061 , H04J3/0632
摘要： In a method for adaptive synchronization of a data sink device to a data source device coupled by a USB, data is received and stored in a buffer of the sink device at an average data rate representative of the data rate of the source device. A data level for the buffer is determined based on input packet size and output packet size. An accumulated data level for the buffer is compared with a threshold level. A clock frequency for the sink device is corrected when the accumulated data level exceeds the threshold level.

57. 发明授权

US06915399B1 Cross-clock domain data transfer method and apparatus 失效
标题翻译：跨时钟域数据传输方法和装置
公开(公告)号：US06915399B1
公开(公告)日：2005-07-05
申请号：US09524942
申请日：2000-03-14
申请人： David J. McDonnell , Andrew M. Volk , Michael W. Williams
发明人： David J. McDonnell , Andrew M. Volk , Michael W. Williams
IPC分类号： G06F1/04 , G06F12/00 , G06F13/00 , H04L12/403 , H04L12/54
CPC分类号： G06F5/06 , G06F13/1689 , G06F2205/061
摘要： An apparatus and method for transferring units of information between clock domains. A respective set of N units of information is loaded from an output circuit in a first clock domain into a storage circuit in a second clock domain during each cycle of the first clock domain. Each set of N units is selected by the output circuit to include (1) units of information that have previously loaded into the storage circuit and that will not be output from the storage output from the storage circuit prior to the storage circuit being loaded with a subsequent set of N units of information, and (2) a complement number of units of information that have not previously been loaded into the storage circuit.
摘要翻译：一种用于在时钟域之间传送信息单元的装置和方法。在第一时钟域的每个周期期间，将相应的N个信息单元从第一时钟域中的输出电路加载到第二时钟域中的存储电路中。每一组N个单元由输出电路选择，以包括（1）先前已经加载到存储电路中的信息单元，并且在存储电路被加载之前不会从存储电路的存储输出输出随后的一组N个信息，以及（2）补充数量的先前未被加载到存储电路中的信息单元。

58. 发明授权

US06836854B2 DS3 Desynchronizer with a module for providing uniformly gapped data signal to a PLL module for providing a smooth output data signal 有权
标题翻译： DS3 Desynchronizer带有一个模块，用于向PLL模块提供均匀的间隙数据信号，以提供平滑的输出数据信号
公开(公告)号：US06836854B2
公开(公告)日：2004-12-28
申请号：US09825102
申请日：2001-04-03
申请人： Balaji Ranganath , Jahangir Nakra
发明人： Balaji Ranganath , Jahangir Nakra
IPC分类号： G06F112
CPC分类号： G06F5/12 , G06F2205/061 , H03L7/08 , H04J3/076
摘要： A desynchronizer for smoothing gapped data signal and a gap clock signal extracted from a synchronous message is disclosed. A gap regulator module first re-maps the gapped data signal into a B-frame format and distributes the gaps in the data uniformly throughout the gapped data signal. A pointer leak logic module determines the bit leak rate as a function of received increment and decrement pointer adjustment signals. The pointer leak logic module determines the bit leak rate using separate algorithms. If the increment and decrement pointer adjustment signals are periodic in nature the bit leak rate is determined by dividing the periodic rate interval between two successive pointer adjustment signals by eight (8) and form a leak rate lookup table to account for any additional or missed pointer movements by looking up the incremental leak rate as a result. If the pointer adjustment signals are not periodic in nature, an exponential bit leak rate is used that is a function of the number of pointer adjustment signals that have been received. The pointer leak logic module provides a bit leak adjusted uniformly gapped data signal to a phase locked loop that provides a smooth output data signal and extracts a smooth output clock signal therefrom.
摘要翻译：公开了一种用于平滑间隙数据信号的去同步器和从同步消息提取的间隙时钟信号。间隙调节器模块首先将有间隙数据信号重新映射为B帧格式，并将数据中的间隙均匀地分布在整个间隙数据信号中。指针泄漏逻辑模块将位泄漏率确定为接收到的递增和递减指针调整信号的函数。指针泄漏逻辑模块使用单独的算法确定位泄漏率。如果增量和减量指针调整信号本质上是周期性的，则通过将两个连续的指针调整信号之间的周期速率间隔除以八（8）来确定位泄漏率，并形成泄漏率查找表以考虑任何附加或错过的指针因此，通过查看增量泄漏率来进行运动。如果指针调整信号本质上不是周期性的，则使用指数位泄漏率，其是已经接收到的指针调整信号的数量的函数。指针泄漏逻辑模块提供了一个位泄漏调整的均匀间隙数据信号到锁相环，提供平滑的输出数据信号，并从中提取平稳的输出时钟信号。

59. 发明申请

US20040165690A1 Synchronizing method and apparatus 有权
标题翻译：同步方法和装置
公开(公告)号：US20040165690A1
公开(公告)日：2004-08-26
申请号：US10789546
申请日：2004-02-27
申请人： Broadcom Corporation
发明人： Tarek Kaylani , Fang Lu , Henry Samueli
IPC分类号： H04K001/00 , H04L025/00
CPC分类号： G06F5/14 , G06F1/025 , G06F5/12 , G06F2205/061 , G06F2205/126 , H03L7/07 , H03L7/081 , H03L7/085 , H03L7/0996 , H03L7/23 , H04J3/062
摘要： To synchronize a regularly occurring pulse train to the average of a bunched pulse train, an oscillator generates a plurality of differently phase shifted signals at a given frequency. One of the phase shifted signals is selected as an output signal. The output signal is compared with the bunched pulse train. The selected phase shifted signal is changed responsive to the comparison so the output signal occurs at the average frequency of the bunched pulse train. The oscillator is formed as a plurality of differential amplifier stages having equal controllable delays. The stages are connected together to form a ring oscillator. The output signal is compared with the bunched pulse train through a FIFO. A signal representative of the state of the FIFO is used as an error signal to control the selection of the phase shifted signal to be used as the output signal. A phase locked loop that synchronizes the phase shifted signal generating oscillator to a frequency reference is nested in the control loop that selects one of the phase shifted signals as the output signal.
摘要翻译：为了使定期发生的脉冲串与聚束脉冲串的平均值同步，振荡器以给定频率产生多个不同的相移信号。选择一个相移信号作为输出信号。将输出信号与聚束脉冲串进行比较。所选择的相移信号响应于比较而改变，因此输出信号以聚束脉冲串的平均频率发生。振荡器形成为具有相同可控延迟的多个差分放大器级。这些级连接在一起以形成环形振荡器。输出信号通过FIFO与聚束脉冲序列进行比较。代表FIFO状态的信号被用作误差信号，以控制用作输出信号的相移信号的选择。将相移信号产生振荡器与频率基准同步的锁相环嵌套在选择相移信号之一作为输出信号的控制回路中。

60. 发明授权

US06775724B2 Method and apparatus for synchronization control for various frequencies 失效
标题翻译：用于各种频率的同步控制的方法和装置
公开(公告)号：US06775724B2
公开(公告)日：2004-08-10
申请号：US09793909
申请日：2001-02-28
申请人： Masafumi Toshitani , Hitoshi Koseki
发明人： Masafumi Toshitani , Hitoshi Koseki
IPC分类号： G06F300
CPC分类号： H03L7/0992 , G06F5/06 , G06F2205/061 , H03L7/091
摘要： A synchronization control apparatus and method enables synchronization control which can flexibly accommodate various frequencies using a simple circuit construction. A storage device that has a predetermined capacity, such as a FIFO, stores externally input data. A CPU controls an output frequency at which data stored in the storage device are output, based on an average frequency which is an average of the output frequency and on a coefficient for setting the average frequency at a fixed value, the first frequency controlling device calculating the average of the output frequency whenever a timing signal is input in accordance with a predetermined cycle and determining the coefficient depending on a free capacity of the storage device at a time of inputting of the timing signal. The CPU operates if the calculated average frequency continuously exhibits a fixed value for a predetermined time period, to decrease the output frequency when the free capacity of the storage device is larger than a predetermined upper threshold value, while increasing the output frequency when the free capacity of the storage device is smaller than a predetermined lower threshold value. The upper threshold value and the lower threshold value each comprise two different values.
摘要翻译：同步控制装置和方法能够使用简单的电路结构灵活地适应各种频率的同步控制。具有预定容量（诸如FIFO）的存储装置存储外部输入数据。基于作为输出频率的平均值的平均频率和将平均频率设定为固定值的系数，CPU控制输出存储在存储装置中的数据的输出频率，第一频率控制装置计算每当按照预定周期输入定时信号时的输出频率的平均值，并且在输入定时信号时根据存储装置的可用容量确定系数。如果所计算的平均频率在预定时间段内连续地呈现固定值，则CPU操作，以便当存储装置的可用容量大于预定的上限阈值时降低输出频率，同时在可用容量的存储设备小于预定的下限阈值。上阈值和下阈值各自包含两个不同的值。

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