专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US09483437B2 Addressing multi-core advanced memory buffers 有权
标题翻译：寻址多核高级内存缓冲区
公开(公告)号：US09483437B2
公开(公告)日：2016-11-01
申请号：US11864781
申请日：2007-09-28
申请人： Shiva Aditham , Steven C. Yang
发明人： Shiva Aditham , Steven C. Yang
IPC分类号： G06F12/02 , G06F13/42
CPC分类号： G06F13/4243 , G06F13/4256 , Y02D10/14 , Y02D10/151
摘要： In some embodiments a method of addressing advanced memory buffers identifies whether a dual inline memory module includes more than one advanced memory buffer. If the dual inline memory module includes more than one advanced memory buffer, then each of the advanced memory buffers of the dual inline memory module is addressed separately, and an address is computed for a next dual inline memory module. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，寻址高级存储器缓冲器的方法识别双列直插式存储器模块是否包括多于一个的高级存储器缓冲器。如果双列直插式存储器模块包括多个高级存储器缓冲器，则双列直插存储器模块的每个高级存储器缓冲器被单独寻址，并为下一个双列直插存储器模块计算一个地址。描述和要求保护其他实施例。

52. 发明申请

US20160217090A1 METHOD AND APPARATUS TO ENABLE MULTIPLE MASTERS TO OPERATE IN A SINGLE MASTER BUS ARCHITECTURE 审中-公开
标题翻译：使用多个主机在单个主总线架构中运行的方法和装置
公开(公告)号：US20160217090A1
公开(公告)日：2016-07-28
申请号：US15087535
申请日：2016-03-31
申请人： QUALCOMM Incorporated
发明人： Shoichiro Sengoku , Richard Dominic Wietfeldt , George Alan Wiley
IPC分类号： G06F13/364 , G06F13/42 , G06F13/26
CPC分类号： G06F13/364 , G06F13/24 , G06F13/26 , G06F13/362 , G06F13/4256 , G06F13/426
摘要： To accommodate multiple masters over bus architectures supporting a single master device, a mechanism is provided for an inactive master device to assert an in-band IRQ. A current master then polls the other inactive master devices over a shared data bus to ascertain which inactive master device is asserting the IRQ. Upon identifying the asserting inactive master device, the current master device grants control of the data bus to the new master device, thereby making the inactive master the new active master device.
摘要翻译：为了通过支持单个主设备的总线架构来容纳多个主机，为非活动主设备提供了一种机制来断言带内IRQ。然后当前主机通过共享数据总线轮询其他无效的主设备，以确定哪个非活动主设备正在断言IRQ。当识别出断言无效的主设备时，当前的主设备将数据总线的控制权授予新的主设备，从而使非活动主设备成为新的主主设备。

53. 发明申请

US20160210381A1 Arbiter Verification 有权
标题翻译：仲裁者验证
公开(公告)号：US20160210381A1
公开(公告)日：2016-07-21
申请号：US14920445
申请日：2015-10-22
申请人： Imagination Technologies Limited
发明人： Iain Singleton , Ashish Darbari , John Alexander Osborne Netterville
IPC分类号： G06F17/50
CPC分类号： G06F13/364 , G06F13/1621 , G06F13/3625 , G06F13/4252 , G06F13/4256 , G06F17/5009 , G06F17/5022 , G06F17/5045
摘要： Operation of an arbiter in a hardware design is verified. The arbiter receives a plurality of requests over a plurality of clock cycles, including a monitored request and outputs the requests in priority order. The requests received by and output from the arbiter in each clock cycle are identified. The priority of the watched request relative to other pending requests in the arbiter is then tracked using a counter that is updated based on the requests input to and output from the arbiter in each clock cycle and a mask identifying the relative priority of requests received by the arbiter in the same clock cycle. The operation of the arbiter is verified using an assertion which establishes a relationship between the counter and the clock cycle in which the watched request is output from the arbiter.
摘要翻译：验证硬件设计中仲裁器的操作。仲裁器在多个时钟周期内接收多个请求，包括被监视的请求，并以优先顺序输出请求。识别在每个时钟周期中由仲裁器接收和输出的请求。然后，使用基于在每个时钟周期中输入到仲裁器并从仲裁器输出的请求而更新的计数器跟踪观察请求相对于仲裁器中的其他未决请求的优先级，以及识别由所述仲裁器接收的请求的相对优先级的掩码仲裁者在同一个时钟周期。使用断言来确认仲裁器的操作，该断言建立从仲裁器输出监视请求的计数器与时钟周期之间的关系。

54. 发明授权

US09396148B2 System method for connecting USB Type-C devices by measuring predetermined test patterns between a plurality of connected accessories 有权
标题翻译：通过测量多个连接的附件之间的预定测试图案来连接USB C型设备的系统方法
公开(公告)号：US09396148B2
公开(公告)日：2016-07-19
申请号：US14223860
申请日：2014-03-24
申请人： Nokia Corporation
发明人： Kai Inha , Juha Reinhold Backman , Pekka Talmola , Timo J. Toivanen
IPC分类号： G06F13/00 , G06F13/38 , G06F13/40 , G06F13/42
CPC分类号： G06F13/385 , G06F13/4022 , G06F13/4256
摘要： In some example embodiments, there may be provided a method, which may include sending, by a user equipment, a first predetermined test pattern to a first accessory including a first connector, when the first accessory is in a first mode of operation; determining, by the user equipment, a configuration of the first accessory in the first mode by at least measuring a first time for the first predetermined test pattern to return from the first connector and a data loop at the first accessory; sending, by the user equipment, a second predetermined test pattern via at least the first connector; and determining, by the user equipment, a presence of a data loop extension, by at least measuring a second time for the second predetermined test pattern to return from the first connector and at least one of the data loop at the first accessory or the data loop extension.
摘要翻译：在一些示例实施例中，可以提供一种方法，其可以包括当第一附件处于第一操作模式时，由用户设备将第一预定测试图案发送到包括第一连接器的第一附件; 由用户设备通过至少测量第一预定测试图案从第一连接器返回的第一时间和第一附件的数据循环来确定第一模式中的第一附件的配置; 通过所述用户设备经由至少所述第一连接器发送第二预定测试图案; 以及由所述用户设备确定数据环路扩展的存在，至少测量所述第二预定测试模式的第二时间以从所述第一连接器返回并且在所述第一附件处返回数据循环中的至少一个或所述数据循环扩展。

55. 发明申请

US20160182047A1 METHOD FOR COMMUNICATION ACROSS VOLTAGE DOMAINS 有权
标题翻译：交流电压域通信方法
公开(公告)号：US20160182047A1
公开(公告)日：2016-06-23
申请号：US14705479
申请日：2015-05-06
申请人： Apple Inc.
发明人： Gary L. Stirk , Karthik Kadirvel
IPC分类号： H03K19/0175
CPC分类号： H03K19/017509 , G01R31/3655 , G01R31/3675 , G06F13/4256 , H02J7/0021 , H02J7/0026 , H02J7/0052 , H02J7/0068 , H02J7/007 , H02J2007/0059 , H03L7/00 , Y02D10/14 , Y02D10/151
摘要： A system may include a plurality of units, wherein each unit has a respective common mode voltage terminal, communication up terminal, and communication down terminal. A first unit of the plurality of units may be configured to generate a first plurality of currents on its communication up terminal, wherein the first plurality of currents corresponds to a first plurality of bits. A second unit of the plurality of units may be configured to receive the first plurality of currents on its respective communication down terminal, and maintain a voltage level at its respective communication down terminal during reception of the first plurality of currents. The voltage level may be equal to a common mode voltage of the respective common mode voltage terminal of the second unit.
摘要翻译：系统可以包括多个单元，其中每个单元具有相应的共模电压端子，通信上行端子和通信下降端子。多个单元中的第一单元可以被配置为在其通信上行终端上产生第一多个电流，其中第一多个电流对应于第一多个位。多个单元中的第二单元可以被配置为在其各自的通信下行终端接收第一多个电流，并且在接收第一多个电流期间在其各自的通信下行端子处保持电压电平。电压电平可以等于第二单元的各个共模电压端子的共模电压。

56. 发明申请

US20150095541A1 METHOD AND SYSTEM FOR ENUMERATING DIGITAL CIRCUITS IN A SYSTEM-ON-A-CHIP (SOC) 有权
标题翻译：在系统中的数字电路（SOC）中实现数字电路的方法和系统
公开(公告)号：US20150095541A1
公开(公告)日：2015-04-02
申请号：US14040165
申请日：2013-09-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Thomas B. CHADWICK, Jr. , Michael R. OUELLETTE , Nancy H. PRATT
IPC分类号： G06F13/42
CPC分类号： G06F15/7817 , G06F13/4068 , G06F13/4247 , G06F13/4256 , G11C19/00
摘要： Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.
摘要翻译：公开了一种在片上系统（SOC）中枚举数字电路的方法和系统。该方法包括增加从先前可枚举实例接收到的枚举值，以唯一地标识菊花链配置中的多个可枚举实例的紧邻的可枚举实例。

57. 发明申请

US20140325104A1 COMMUNICATIONS ASSEMBLY HAVING LOGIC MULTICHANNEL COMMUNICATION VIA A PHYSICAL TRANSMISSION PATH FOR SERIAL INTERCHIP DATA TRANSMISSION 有权
标题翻译：具有串行数据传输的物理传输路径的通信组装通过逻辑多通道通信
公开(公告)号：US20140325104A1
公开(公告)日：2014-10-30
申请号：US14346943
申请日：2012-08-06
申请人： Andreas-Juergen Rohatschek , Dieter Thoss , Thorsten Huck , Stoyan Todorov
发明人： Andreas-Juergen Rohatschek , Dieter Thoss , Thorsten Huck , Stoyan Todorov
IPC分类号： G06F13/42 , G06F13/24
CPC分类号： G06F13/4256 , G06F13/24 , G06F13/4247 , G06F13/4282
摘要： In a communications assembly having multiple users, one user is designated as a master and additional users are designated as peripheral modules, at least two of the peripheral modules as well as at least two interface modules are integrated into a shared physical implementation unit, and at least one interface module, which is designated as a slave, is unambiguously assigned to each of the at least two peripheral modules.
摘要翻译：在具有多个用户的通信组件中，一个用户被指定为主机，另外的用户被指定为外围模块，至少两个外围模块以及至少两个接口模块被集成到共享的物理实现单元中，并且在被指定为从机的至少一个接口模块被明确地分配给至少两个外围模块中的每一个。

58. 发明申请

US20140281198A1 DATA INTERFACE CIRCUIT FOR CAPTURING RECEIVED DATA BITS INCLUDING CONTINUOUS CALIBRATION 有权
标题翻译：用于接收接收数据位的数据接口电路，包括连续校准
公开(公告)号：US20140281198A1
公开(公告)日：2014-09-18
申请号：US14205239
申请日：2014-03-11
申请人： Uniquify, Inc.
发明人： Venkat Iyer , Prashant Joshi , Jung LEE
IPC分类号： G11C8/18
CPC分类号： G06F13/3625 , G06F13/1689 , G06F13/4256 , G11C8/18 , G11C29/022 , G11C29/023 , G11C29/028 , H03K5/133 , H03K5/14 , H03K2005/00019 , H03L7/08 , H03L7/0812 , H03L7/10
摘要： Circuits and methods for implementing a continuously adaptive timing calibration training function in an integrated circuit interface are disclosed. A mission data path is established where a data bit is sampled by a strobe. A similar reference data path is established for calibration purposes only. At an initialization time both paths are calibrated and a delta value between them is established. During operation of the mission path, the calibration path continuously performs calibration operations to determine if its optimal delay has changed by more than a threshold value. If so, the new delay setting for the reference path is used to change the delay setting for the mission path after adjustment by the delta value. Circuits and methods are also disclosed for performing multiple parallel calibrations for the reference path to speed up the training process.
摘要翻译：公开了用于在集成电路接口中实现连续自适应定时校准训练功能的电路和方法。建立通过闪光灯对数据位进行采样的任务数据通路。建立类似的参考数据路径用于校准目的。在初始化时间，两个路径被校准，并且它们之间的增量值被建立。在任务路径的操作期间，校准路径连续执行校准操作，以确定其最佳延迟是否已经改变超过阈值。如果是这样，则使用参考路径的新延迟设置，将调整后的任务路径的延迟设置改变为delta值。还公开了用于对参考路径执行多个并行校准以加速训练过程的电路和方法。

59. 发明申请

US20130275628A1 HIGH SPEED INTERFACE FOR DAISY-CHAINED DEVICES 审中-公开
标题翻译：用于家庭装置的高速接口
公开(公告)号：US20130275628A1
公开(公告)日：2013-10-17
申请号：US13914126
申请日：2013-06-10
申请人： MOSAID TECHNOLOGIES INCORPORATED
发明人： Byoung Jin CHOI
IPC分类号： G06F3/06
CPC分类号： G06F3/061 , G06F13/4234 , G06F13/4243 , G06F13/4256
摘要： A plurality of devices are operated by storing at a device a first ID number received at a first port of the device and a second ID number received at a second port of the device. The device receives a data command through at least one of the first and second ports. The data command has a command ID number. The device executes the data command when at least one of the command ID number is equal to the first ID number when the data command is received at the first port and the command ID number is equal to the second ID number when the data command is received at the second port.
摘要翻译：通过在设备处存储在设备的第一端口处接收到的第一ID号码和在设备的第二端口处接收到的第二ID号码来操作多个设备。设备通过第一和第二端口中的至少一个接收数据命令。 data命令有一个命令ID号。当在第一端口接收到数据命令时，当至少一个命令ID号码等于第一ID号码并且当接收到数据命令时命令ID号码等于第二ID号码时，设备执行数据命令在第二个港口

60. 发明授权

US08510612B2 Disabling outbound drivers for a last memory buffer on a memory channel 有权
公开(公告)号：US08510612B2
公开(公告)日：2013-08-13
申请号：US13606339
申请日：2012-09-07
申请人： Pete D. Vogt , Dennis W. Brzezinski , Warren R. Morrow
发明人： Pete D. Vogt , Dennis W. Brzezinski , Warren R. Morrow
IPC分类号： G11C29/00
CPC分类号： G06F12/00 , G06F13/4243 , G06F13/4256 , Y02D10/14 , Y02D10/151
摘要： Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式