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51. 发明申请

US20030137002A1 Split gate flash memory cell structure and method of manufacturing the same 有权
公开(公告)号：US20030137002A1
公开(公告)日：2003-07-24
申请号：US10383527
申请日：2003-03-10
申请人： Winbond Electronics Corporation
发明人： Ching-Hsiang Hsu , Evans Ching-Song Yang , Lein-Yi Leu , Bin-Shing Chen
IPC分类号： H01L021/336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： A non-volatile memory cell that includes a semiconductor substrate, a well region implanted with a first-type dopant formed in the semiconductor substrate, a first doped region implanted with a second-type dopant formed in the semiconductor substrate, a second doped region, formed spaced-apart from the first doped region, implanted with a second-type dopant formed in the semiconductor substrate, the second doped region further including a third region implanted with the first-type dopant, a first dielectric layer disposed over the semiconductor substrate, a floating gate disposed over the first dielectric layer and extending over the well region and a portion of the second doped region, a second dielectric layer disposed over the floating gate, and a control gate disposed over the first dielectric layer and the second dielectric layer.

52. 发明申请

US20030107078A1 Self-aligned dual-floating gate memory cell . 审中-公开
标题翻译：自对准双浮栅存储单元。
公开(公告)号：US20030107078A1
公开(公告)日：2003-06-12
申请号：US10067889
申请日：2002-02-08
申请人： Winbond Electronics Corporation
发明人： James Juen Hsu
IPC分类号： H01L029/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/7887
摘要： An integrated circuit that includes a first dual-floating gate memory cell having a first floating gate isolated from a second floating gate for storing at least one bit of datum, and a second dual-floating gate memory cell having a third floating gate isolated from a fourth floating gate for storing at least one bit of datum, wherein the first dual-floating gate memory cell and the second dual-floating gate memory cell share a control gate, wherein the second floating gate of the first dual-floating gate memory cell shares an oxide layer with the third floating gate of the second dual-floating gate memory cell, and wherein the oxide layer electrically insulates the second and third floating gates from the control gate.
摘要翻译：一种集成电路，其包括具有与第二浮动栅极隔离的第一浮动栅极的第一双浮置栅极存储单元，用于存储至少一个基准点;以及第二双浮置栅极存储单元，具有与第一浮置栅极隔离的第三浮置栅极用于存储至少一位数据的第四浮动栅极，其中所述第一双浮置栅极存储器单元和所述第二双浮置栅极存储器单元共享控制栅极，其中所述第一双浮置栅极存储单元的第二浮置栅极共享具有第二双浮置栅极存储单元的第三浮置栅极的氧化物层，并且其中氧化物层使第二和第三浮置栅极与控制栅极电绝缘。

53. 发明申请

US20030076138A1 POWER-ON CIRCUIT OF A PERIPHERAL COMPONENT 失效
标题翻译：外围组件的上电电路
公开(公告)号：US20030076138A1
公开(公告)日：2003-04-24
申请号：US10125139
申请日：2002-04-18
申请人： WINBOND ELECTRONICS CORPORATION
发明人： Bar-Chung Hwang
IPC分类号： H03L007/00
CPC分类号： G06F1/26 , H03K17/284
摘要： The present invention discloses a power-on circuit of a peripheral component, which comprises a switch control circuit for controlling the enabling time of a P-type or N-type transistor. For a P-type transistor, the switch control circuit includes a pull-high element, a current source and a current switch. For a N-type transistor, the switch control circuit includes a pull-down element, a current source and a current switch. The enabling time of the P-type or N-type transistors are controlled by the switch control circuit and the capacitor shunt with the switch control circuit so as to slowly enable the transistor switch. In other words, the present invention uses the slowly increasing or decreasing characteristic caused by charging the capacitor with the current source to control the P-type or N-type transistor switch so as to obtain the purpose of slowly enabling the power supply. For designing an IC, it is easy to design a constant current source, which occupies only little area, and the disadvantage of the prior art is thereby resolved.
摘要翻译：本发明公开了一种周边部件的通电电路，其包括用于控制P型或N型晶体管的使能时间的开关控制电路。对于P型晶体管，开关控制电路包括上拉元件，电流源和电流开关。对于N型晶体管，开关控制电路包括下拉元件，电流源和电流开关。 P型或N型晶体管的使能时间由开关控制电路和电容器与开关控制电路分流控制，以便缓慢启用晶体管开关。换句话说，本发明使用由电流源对电容器充电引起的缓慢增加或减小的特性来控制P型或N型晶体管开关，从而达到缓慢地实现电源的目的。为了设计IC，可以容易地设计仅占用少量面积的恒流源，从而解决了现有技术的缺点。

54. 发明申请

US20020135010A1 Memory-storage node and the method of fabricating the same 有权
标题翻译：存储器节点及其制造方法
公开(公告)号：US20020135010A1
公开(公告)日：2002-09-26
申请号：US09813993
申请日：2001-03-22
申请人： Winbond Electronics Corporation
发明人： Bor-Ru Sheu , Ming-Chung Chiang , Chung-Ming Chu , In-Chieh Yang
IPC分类号： H01L027/108 , H01L029/76 , H01L029/94 , H01L031/119 , H01G004/008
CPC分类号： H01L21/7687 , H01L21/76897 , H01L27/10855 , H01L28/75 , H01L28/90
摘要： The memory-storage node of the present invention includes a semiconductor substrate, a first insulating layer over the substrate, a conductive layer formed within the first insulating layer, and a barrier layer formed over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. The memory-storage node further includes a first electrode over the barrier layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The method for fabricating the memory storage-node of the present invention provides a semiconductor substrate and forms a first insulating layer on the substrate. A first opening is formed in the first insulating layer and a conductive layer is provided in the first opening. A barrier layer is then formed in the first opening and over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. A second insulating layer is formed over the first insulating layer and the barrier layer. A second opening is formed in the second insulating layer to expose a portion of the underlying barrier layer. A first electrode is formed in the second opening and a dielectric layer is formed on the second insulating layer and the first electrode. Finally, a second electrode is formed over the dielectric layer.
摘要翻译：本发明的存储器存储节点包括半导体衬底，衬底上的第一绝缘层，形成在第一绝缘层内的导电层，以及形成在导电层上的阻挡层。阻挡层优选含有钌基材料，与导电层导电耦合。存储器存储节点还包括位于阻挡层上的第一电极，位于第一电极上的电介质层，以及介电层上的第二电极。本发明的存储器存储器的制造方法提供半导体衬底，并在衬底上形成第一绝缘层。在第一绝缘层中形成第一开口，并且在第一开口中设置导电层。然后在第一开口中和导电层上方形成阻挡层。阻挡层优选含有钌基材料，与导电层导电耦合。在第一绝缘层和阻挡层之上形成第二绝缘层。在第二绝缘层中形成第二开口以暴露下面的阻挡层的一部分。第一电极形成在第二开口中，并且在第二绝缘层和第一电极上形成电介质层。最后，在电介质层上形成第二电极。

55. 发明申请

US20020074602A1 Electrostatic discharge protection circuit 失效
标题翻译：静电放电保护电路
公开(公告)号：US20020074602A1
公开(公告)日：2002-06-20
申请号：US09740016
申请日：2000-12-20
申请人： Winbond Electronics Corporation
发明人： Shi-Tron Lin , Wei-Fan Chen , Chenhsin Lien , Wan-Yun Lin
IPC分类号： H01L023/62
CPC分类号： H01L27/0259 , H01L27/1203 , H01L29/0653 , H01L29/1087 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protection device includes a semiconductor layer, a source region formed in the layer, a drain region formed in the layer, a channel region in the layer between the source and drain regions, and a gate over the channel region. A plurality of current divider segments are distributed on the drain region and extend between the gate and drain contacts. The segments can be formed of polysilicon or a field oxide.
摘要翻译：静电放电（ESD）保护装置包括半导体层，形成在该层中的源极区，形成在该层中的漏极区，在源极和漏极区之间的层中的沟道区，以及沟道区上的栅极。多个分流器段分布在漏极区域上并在栅极和漏极触点之间延伸。段可以由多晶硅或场氧化物形成。

56. 发明授权

US6147513A Method and circuit for logic input buffer 失效
标题翻译：逻辑输入缓冲器的方法和电路
公开(公告)号：US6147513A
公开(公告)日：2000-11-14
申请号：US71673
申请日：1998-05-01
申请人： John Henry Bui
发明人： John Henry Bui
IPC分类号： H03K19/00 , H03K19/0175
CPC分类号： H03K19/0027
摘要： A novel logic input buffer having independent DC input trip points (e.g., V.sub.IL and V.sub.IH), reduced cross current during signal transitions, shorter propagation delay, and improved noise performance. The input buffer includes a set of input transistors having dynamically adjustable beta(s) that allows for robust control of the transistor(s) operating characteristics. The beta(s) can be adjusted by changing the size(s) of the input transistors through enabling and disabling selected one(s) of additional input transistor(s).
摘要翻译：具有独立DC输入跳变点（例如，VIL和VIH）的新型逻辑输入缓冲器，在信号转换期间减少的交叉电流，较短的传播延迟和改进的噪声性能。输入缓冲器包括一组输入晶体管，其具有动态可调节的β（s），其允许稳定地控制晶体管的工作特性。可以通过使能和禁用所选择的一个或多个附加输入晶体管来改变输入晶体管的尺寸来调整beta（s）。

57. 发明授权

US6137741A Sense amplifier with cascode output 有权
标题翻译：具有共源共栅输出的感应放大器
公开(公告)号：US6137741A
公开(公告)日：2000-10-24
申请号：US397754
申请日：1999-09-16
申请人： Lin-Shih Liu
发明人： Lin-Shih Liu
IPC分类号： G11C7/06 , G11C16/26 , G11C7/02 , G11C16/06
CPC分类号： G11C16/26 , G11C7/067
摘要： A sense amplifier circuit for a memory integrated circuit provides good performance and relatively low power consumption. The circuitry includes a cascode output and a feedback (214) from the cascode output to a transistor (M1) to provide additional pull-up current at a bit line (206).
摘要翻译：用于存储器集成电路的读出放大器电路提供良好的性能和相对低的功耗。电路包括共源共栅输出和从共源共栅输出到晶体管（M1）的反馈（214），以在位线（206）处提供额外的上拉电流。

58. 发明授权

US6122219A Split array semiconductor graphics memory architecture supporting maskable block write operation 失效
标题翻译：分立阵列半导体图形存储器架构支持可屏蔽块写操作
公开(公告)号：US6122219A
公开(公告)日：2000-09-19
申请号：US115377
申请日：1998-07-14
申请人： Hua Zheng , Hui Zhao
发明人： Hua Zheng , Hui Zhao
IPC分类号： G11C7/10 , G11C8/00 , G11C16/04
CPC分类号： G11C7/1006
摘要： A semiconductor memory column decoder has first and second groups of parallel column lines (or column line pairs). The first and second groups of column lines are separated from each other by a gap. One or more groups of fractional I/O lines are provided, wherein each fractional I/O line is collinear with each other fractional I/O line of the same group. One fractional I/O line is provided for, and is connected to, each column line of the first and second groups of column lines. A plurality of multiplexers is provided, including one multiplexer corresponding to each fractional I/O line. Each multiplexer has an input connected to a single data line, a select input connected to a corresponding column select line, and an output connected to the corresponding fractional I/O line. At least some of the multiplexers are disposed in the gap.
摘要翻译：半导体存储器列解码器具有第一和第二组平行列线（或列线对）。第一和第二组列线通过间隙彼此分开。提供了一组或多组分数I / O线，其中每个分数I / O线与相同组的彼此分数I / O线共线。为第一和第二组列线的每条列线提供一个分数I / O线，并连接到每列列线。提供了多个多路复用器，包括对应于每个分数I / O线的一个多路复用器。每个多路复用器具有连接到单个数据线的输入，连接到相应的列选择线的选择输入以及连接到相应的小数I / O线的输出。至少一些多路复用器被布置在间隙中。

59. 发明授权

US6034439A Method and structure for preventing bonding pads from peeling caused by plug process 失效
标题翻译：用于防止由焊接过程引起的接合垫剥落的方法和结构
公开(公告)号：US6034439A
公开(公告)日：2000-03-07
申请号：US41020
申请日：1998-03-12
申请人： Kuo-Shi Teng , Hao-Chieh Yung , Shing-Shing Chiang , Wen-Haw Lu
发明人： Kuo-Shi Teng , Hao-Chieh Yung , Shing-Shing Chiang , Wen-Haw Lu
IPC分类号： H01L21/60 , H01L23/485 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L24/03 , H01L24/11 , H01L2224/02166 , H01L2224/0401 , H01L2224/05093 , H01L2224/05556 , H01L2224/13099 , H01L2924/00014 , H01L2924/01013 , H01L2924/01033 , H01L2924/01074 , H01L2924/014
摘要： A method for preventing bonding pads from peeling caused by plug process comprises the following steps. First, a substrate is prepared, and then a first conductor is formed on the substrate. Next, a dielectric layer is formed on the first conductor. After that, a big contact window and a plurality of small contact windows are formed on the dielectric layer, wherein the plurality of small contact windows are located around the big window, and the sizes of the big contact window and small contact windows are over 3 .mu.m. Subsequently, a metal plug layer is formed on the dielectric layer, big contact window and small contact windows. Thereafter, the metal plug layer is etched back to form metal spacers on the sidewalls of the big contact window and small contact windows. Finally, a second conductor is formed on the dielectric layer, big contact window, small contact windows and metal spacers. Since the second conductor is directly connected to the first conductor in the invention, bonding pads peeling can be thoroughly prevented during connecting between the bonding pads and outside pins.
摘要翻译：用于防止由焊接过程引起的焊盘剥离的方法包括以下步骤。首先，准备基板，然后在基板上形成第一导体。接下来，在第一导体上形成电介质层。之后，在电介质层上形成大的接触窗和多个小接触窗，其中多个小接触窗位于大窗周围，大接触窗和小接触窗的尺寸超过3 亩随后，在电介质层，大接触窗和小接触窗上形成金属塞层。此后，金属插塞层被回蚀以在大接触窗的侧壁和小的接触窗口上形成金属间隔物。最后，在电介质层，大接触窗，小接触窗和金属间隔物上形成第二导体。由于在本发明中第二导体直接连接到第一导体，因此在连接焊盘和外部引脚之间可以彻底地防止焊盘剥离。

60. 发明授权

US6002179A Bonding pad structure for integrated circuit (I) 失效
标题翻译：集成电路接合焊盘结构（I）
公开(公告)号：US6002179A
公开(公告)日：1999-12-14
申请号：US39354
申请日：1998-03-13
申请人： Chin-Jong Chan , Hsiu-Hsin Chung , Rueyway Lin
发明人： Chin-Jong Chan , Hsiu-Hsin Chung , Rueyway Lin
IPC分类号： H01L23/485 , H01L23/48
CPC分类号： H01L24/05 , H01L24/48 , H01L2224/02126 , H01L2224/02166 , H01L2224/04042 , H01L2224/05624 , H01L2224/05666 , H01L2224/45124 , H01L2224/4847 , H01L2224/48724 , H01L2224/48766 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/0105 , H01L2924/01082 , H01L2924/14 , H01L2924/19042
摘要： A bonding pad structure formed on a semiconductor substrate comprises an insulating layer, a conducting pad, a passivation layer, and a buffer layer. The insulating layer is formed on the semiconductor substrate. The conducting pad is formed on the insulating layer, and the passivation layer is formed to cover peripherals of the conducting pad forming an overhang region therebetween. However, the buffer layer is patterned and etched to form a plurality of either islands or openings between the insulating layer and the conducting pad but withon the range of the overhang region. Accordingly, peeling resistance ability can be enhanced via a form of mechanical interlocking. In addition, a portion of the overhang region can be wider than the other portion thereof in order to further intensify the adhesion between the conducting pad and the passivation layer.
摘要翻译：形成在半导体衬底上的焊盘结构包括绝缘层，导电焊盘，钝化层和缓冲层。绝缘层形成在半导体衬底上。导电焊盘形成在绝缘层上，并且形成钝化层以覆盖导电焊盘的外围部分，形成其间的悬垂区域。然而，缓冲层被图案化和蚀刻以在绝缘层和导电焊盘之间形成多个岛或开口，但是在伸出区域的范围内。因此，可以通过机械互锁的形式提高抗剥离能力。此外，突出部分的一部分可以比其他部分更宽，以便进一步增强导电焊盘和钝化层之间的粘附。

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