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    • 56. 发明授权
    • Three-dimensional marquisette style knitted fabric
    • 立体马赛克风格针织面​​料
    • US06477865B1
    • 2002-11-12
    • US09913660
    • 2001-10-09
    • Koichi Matsumoto
    • Koichi Matsumoto
    • D04B2110
    • D04B21/10D10B2403/0114D10B2403/0213D10B2403/0223D10B2505/04D10B2505/08
    • The invention is aimed to provide a three-dimensional marquisette-like knitted fabric, that is good in air retainability, air and water conductibility, light transmittance, as well as dimensional stability and shape retainability in the knitting and knitting-width directions, and in linearity; and has unevenness and slippage preventing property on its surface, thus being suitable in various uses. To this end, a three-dimensional marquisette-like structure is made as follows. A double-web knitted fabric is made by warp knitting, and is preferably comprised of the front and back mesh webs (1, 2) and connecting yarns (3) passed between the mesh webs alternately. At least one of the mesh webs (1, 2) has a marquisette-like construction formed by the rows of chain stitches (11, 21) and inlay yarn (5). In addition, connecting yarns (3) for connecting the mesh webs (1, 2) is shifted knitting-width-wise by at least one wale to be passed as slanted at every required course position corresponding to the marquisette-like construction of at least one of the mesh webs.
    • 本发明的目的在于提供一种三维花纹状针织物,其具有良好的空气保持性,空气和水导电性,透光性以及针织和编织宽度方向上的尺寸稳定性和形状保持性, 线性度 并且在其表面上具有不均匀性和防滑性,因此适用于各种用途。 为此,如下制作三维花键状结构。 双网针织物通过经编制成,优选地由前后网状网(1,2)和连接纱线(3)之间交替布置在网状网之间。 网状网(1,2)中的至少一个具有由排列的线迹(11,21)和嵌入纱线(5)形成的马赛克式结构。 此外,用于连接网状网(1,2)的连接纱线(3)横向逐渐移动至少一个纵行,以便在对应于至少具有类似marquisette的结构的每个所需的路线位置倾斜通过 网格之一。
    • 59. 发明授权
    • CMOS semiconductor device having dual-gate electrode construction and
method of production of the same
    • 具有双栅电极结构的CMOS半导体器件及其制造方法
    • US5837601A
    • 1998-11-17
    • US788191
    • 1997-01-24
    • Koichi Matsumoto
    • Koichi Matsumoto
    • H01L29/78H01L21/28H01L21/336H01L21/8238H01L27/092H01L21/3205H01L21/4763
    • H01L29/665H01L21/28052H01L21/28061H01L21/823842
    • A semiconductor device in which mutual diffusion of doped impurities occurring through an upper silicide electrode layer is prevented. A silicide electrode layer is doped with both the same degree of p-type impurities as the concentration of p-type impurities of the lower gate electrode layer and the same degree of n-type impurities as the concentration of n-type impurities. As a result, the concentration of doped impurities of the gate electrode layer is balanced at the two sides of the interface of the pMOS side and nMOS side. Therefore, heat diffusion caused by subsequent heat treatment is prevented and the problem of mutual diffusion can be solved. The present invention is also suitable for the SALICIDE process. Even when the silicide electrode layer is formed simultaneously on an extremely shallow source or drain regions since the concentration of the impurities of the silicide electrode layer was initially high, the lower impurities will not be drained so the contact resistance will not be made to deteriorate. As a result, it becomes easy for the SALICIDE process to be applied to submicron devices. In the method of production of the present invention, the silicide electrode layer is formed by the CVD method or the sputtering method and the impurities doped during this process, so no special step has to be provided for introducing the impurities.
    • 其中防止了通过上硅化物电极层发生的掺杂杂质的相互扩散的半导体器件。 掺杂了与下部栅电极层的p型杂质浓度相同程度的p型杂质和与n型杂质浓度相同程度的n型杂质的硅化物电极层。 结果,在pMOS侧和nMOS侧的界面的两侧平衡了栅电极层的掺杂杂质的浓度。 因此,防止了后续热处理引起的热扩散,可以解决相互扩散的问题。 本发明也适用于SALICIDE方法。 即使硅化物电极层由于硅化物电极层的杂质的浓度初始高而在极浅的源极或漏极区域同时形成,因此不会排出较低的杂质,因此不会使接触电阻劣化。 因此,将SALICIDE工艺应用于亚微米器件变得容易。 在本发明的制造方法中,通过CVD法或溅射法形成硅化物电极层以及在该工序中掺杂的杂质,因此不得不提供引入杂质的特殊工序。