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51. 发明授权

US08445340B2 Sacrificial offset protection film for a FinFET device 有权
标题翻译：用于FinFET器件的牺牲偏移保护膜
公开(公告)号：US08445340B2
公开(公告)日：2013-05-21
申请号：US12622038
申请日：2009-11-19
申请人： Tsung-Lin Lee , Feng Yuan , Chih Chieh Yeh
发明人： Tsung-Lin Lee , Feng Yuan , Chih Chieh Yeh
IPC分类号： H01L21/8232 , H01L21/84
CPC分类号： H01L29/785 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： A method for fabricating a semiconductor device is disclosed. An exemplary embodiment of the method includes providing a substrate; forming a fin structure over the substrate; forming a gate structure, wherein the gate structure overlies a portion of the fin structure; forming a sacrificial-offset-protection layer over another portion of the fin structure; and thereafter performing an implantation process.
摘要翻译：公开了一种制造半导体器件的方法。该方法的示例性实施例包括提供衬底; 在衬底上形成翅片结构; 形成栅极结构，其中所述栅极结构覆盖所述翅片结构的一部分; 在翅片结构的另一部分上形成牺牲偏移保护层; 然后进行植入处理。

52. 发明申请

US20120091511A1 MULTI-FIN DEVICE BY SELF-ALIGNED CASTLE FIN FORMATION 有权
标题翻译：通过自对准城堡形成的多功能设备
公开(公告)号：US20120091511A1
公开(公告)日：2012-04-19
申请号：US12907272
申请日：2010-10-19
申请人： Hsin-Chih Chen , Tsung-Lin Lee , Feng Yuan
发明人： Hsin-Chih Chen , Tsung-Lin Lee , Feng Yuan
IPC分类号： H01L29/772 , H01L21/302
CPC分类号： H01L29/772 , H01L21/3086 , H01L29/66795 , H01L29/785
摘要： The present disclosure provides a method includes forming a multi-fin device. The method includes forming a patterned mask layer on a semiconductor substrate. The patterned mask layer includes a first opening having a first width W1 and a second opening having a second width W2 less than the first width. The patterned mask layer defines a multi-fin device region and an inter-device region, wherein the inter-device region is aligned with the first opening; and the multi-fin device region includes at least one intra-device region being aligned with the second opening. The method further includes forming a material layer on the semiconductor substrate and the patterned mask layer, wherein the material layer substantially fills in the second opening; performing a first etching process self-aligned to remove the material layer within the first opening such that the semiconductor substrate within the first opening is exposed; performing a second etching process to etch the semiconductor substrate within the first opening, forming a first trench in the inter-device region; and thereafter performing a third etching process to remove the material layer in the second opening.
摘要翻译：本公开提供了一种包括形成多翅片装置的方法。该方法包括在半导体衬底上形成图案化掩模层。图案化掩模层包括具有第一宽度W1的第一开口和具有小于第一宽度的第二宽度W2的第二开口。图案化掩模层限定多鳍器件区域和器件间区域，其中器件间区域与第一开口对准; 并且所述多鳍片器件区域包括与所述第二开口对准的至少一个器件内区域。该方法还包括在半导体衬底和图案化掩模层上形成材料层，其中材料层基本上填充在第二开口中; 执行自对准的第一蚀刻工艺以去除第一开口内的材料层，使得第一开口内的半导体衬底被暴露; 执行第二蚀刻工艺以在所述第一开口内蚀刻所述半导体衬底，在所述器件间区域中形成第一沟槽; 然后执行第三蚀刻处理以去除第二开口中的材料层。

53. 发明授权

US08048795B2 Self-assembly pattern for semiconductor integrated circuit 有权
标题翻译：半导体集成电路的自组装模式
公开(公告)号：US08048795B2
公开(公告)日：2011-11-01
申请号：US12610282
申请日：2009-10-31
申请人： Tsung-Lin Lee , Clement Hsingjen Wann , Ching-Yu Chang
发明人： Tsung-Lin Lee , Clement Hsingjen Wann , Ching-Yu Chang
IPC分类号： H01L21/4763
CPC分类号： H01L21/0337 , H01L21/31144 , H01L21/76816
摘要： A method of fabricating a semiconductor device is provided which includes providing a substrate. A material layer is formed over the substrate. A polymer layer is formed over the material layer. A nano-sized feature is self-assembled using a portion of the polymer layer. The substrate is patterned using the nano-sized feature.
摘要翻译：提供一种制造半导体器件的方法，其包括提供衬底。材料层形成在衬底上。聚合物层形成在材料层上。使用聚合物层的一部分自组装纳米尺寸的特征。使用纳米尺寸的特征对衬底进行图案化。

54. 发明申请

US20110095378A1 FinFET Design with Reduced Current Crowding 有权
标题翻译： FinFET设计，减少电流拥挤
公开(公告)号：US20110095378A1
公开(公告)日：2011-04-28
申请号：US12842281
申请日：2010-07-23
申请人： Tsung-Lin Lee , Chih Chieh Yeh
发明人： Tsung-Lin Lee , Chih Chieh Yeh
IPC分类号： H01L29/78
CPC分类号： H01L27/1211 , H01L29/41791 , H01L29/66795 , H01L29/6681 , H01L29/785 , H01L2029/7858
摘要： An integrated circuit structure includes a substrate and a fin field-effect transistor (FinFET). The FinFET includes a fin over the substrate and having a first fin portion and a second fin portion. A gate stack is formed on a top surface and sidewalls of the first fin portion. An epitaxial semiconductor layer has a first portion formed directly over the second fin portion, and a second portion formed on sidewalls of the second fin portion. A silicide layer is formed on the epitaxial semiconductor layer. A peripheral ratio of a total length of an effective silicide peripheral of the FinFET to a total length of a fin peripheral of the FinFET is greater than 1.
摘要翻译：集成电路结构包括衬底和鳍状场效应晶体管（FinFET）。 FinFET在衬底上包括翅片，并具有第一鳍片部分和第二鳍片部分。栅堆叠形成在第一鳍部的顶表面和侧壁上。外延半导体层具有直接形成在第二鳍部上的第一部分和形成在第二鳍部的侧壁上的第二部分。在外延半导体层上形成硅化物层。 FinFET的有效硅化物周边的总长度与FinFET的鳍状外围的总长度的周长比大于1。

55. 发明申请

US20110068411A1 Block Contact Plugs for MOS Devices 有权
标题翻译： MOS器件的块式触点插头
公开(公告)号：US20110068411A1
公开(公告)日：2011-03-24
申请号：US12789046
申请日：2010-05-27
申请人： Sey-Ping Sun , Chih-Hao Chang , Chao-An Jong , Tsung-Lin Lee , Chung-Ju Lee , Chin-Hsiang Lin
发明人： Sey-Ping Sun , Chih-Hao Chang , Chao-An Jong , Tsung-Lin Lee , Chung-Ju Lee , Chin-Hsiang Lin
IPC分类号： H01L29/78
CPC分类号： H01L21/76897 , H01L21/76804 , H01L21/76816 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor substrate; a gate stack overlying the semiconductor substrate; a gate spacer on a sidewall of the gate stack; a first contact plug having an inner edge contacting a sidewall of the gate spacer, and a top surface level with a top surface of the gate stack; and a second contact plug over and contacting the first contact plug. The second contact plug has a cross-sectional area smaller than a cross-sectional area of the first contact plug.
摘要翻译：集成电路结构包括半导体衬底; 覆盖半导体衬底的栅极堆叠; 在栅极堆叠的侧壁上的栅极间隔物; 具有接触所述栅极隔离物的侧壁的内边缘的第一接触插塞和具有所述栅极堆叠的顶表面的顶表面水平; 以及第二接触插头，并且与第一接触插塞接触。第二接触插塞的横截面积小于第一接触插塞的横截面面积。

56. 发明授权

US07847335B2 Non-volatile memory device having a generally L-shaped cross-section sidewall SONOS 有权
标题翻译：具有大致L形横截面侧壁SONOS的非易失性存储器件
公开(公告)号：US07847335B2
公开(公告)日：2010-12-07
申请号：US11402529
申请日：2006-04-11
申请人： Tzyh-Cheang Lee , Tsung-Lin Lee , Jiunn-Ren Hwang
发明人： Tzyh-Cheang Lee , Tsung-Lin Lee , Jiunn-Ren Hwang
IPC分类号： H01L29/788
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/66833 , H01L29/7923
摘要： A non-volatile semiconductor memory device includes a gate stack formed on a substrate, semiconductor spacers, an oxide-nitride-oxide stack, and a contact pad. The semiconductor spacers are adjacent to sides of the gate stack and over the substrate. The oxide-nitride-oxide stack is located between the spacers and the gate stack, and located between the spacers and the substrate, such that the oxide-nitride-oxide stack has a generally L-shaped cross-section on at least one side of the gate stack. The contact pad is over and in electrical contact with the gate electrode and the semiconductor spacers. The contact pad may be further formed into recessed portions of the oxide-nitride-oxide stack between the gate electrode and the semiconductor spacers. The contact pad may include an epitaxial silicon having a metal silicide formed thereon.
摘要翻译：非易失性半导体存储器件包括形成在衬底，半导体间隔物，氧化物 - 氮化物 - 氧化物堆叠和接触焊盘上的栅堆叠。半导体间隔物邻近栅极堆叠的两侧并在衬底上方。氧化物 - 氧化物 - 氧化物堆叠位于间隔物和栅极堆叠之间，并且位于间隔物和衬底之间，使得氧化物 - 氧化物 - 氧化物堆叠在至少一侧上具有大致L形的横截面门堆叠。接触垫在栅极电极和半导体间隔物之间是电接触的。接触焊盘可以进一步形成在栅电极和半导体间隔物之间的氧化物 - 氮化物 - 氧化物堆叠的凹陷部分。接触焊盘可以包括其上形成有金属硅化物的外延硅。

57. 发明申请

US20070161195A1 Structure and method for a sidewall SONOS memory device 有权
标题翻译：侧壁SONOS存储器件的结构和方法
公开(公告)号：US20070161195A1
公开(公告)日：2007-07-12
申请号：US11327185
申请日：2006-01-06
申请人： Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
发明人： Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , H01L29/4234 , H01L29/66833 , H01L29/7923 , Y10S438/954
摘要： A system and method for a sidewall SONOS memory device is provided. An electronic device includes a non-volatile memory. A substrate includes source/drain regions. A gate stack is directly over the substrate and between the source/drain regions. The gate stack has a sidewall. A nitride spacer is formed adjacent to the gate stack. A first oxide material is formed directly adjacent the spacer. An oxide-nitride-oxide structure is formed between the spacer and the gate stack. The oxide-nitride-oxide structure has a generally L-shaped cross-section on at least one side of the gate stack. The oxide-nitride-oxide structure includes a vertical portion and a horizontal portion. The vertical portion is substantially aligned with the sidewall and located between the first oxide material and the gate sidewall. The horizontal portion is substantially aligned with the substrate and located between the first oxide and the substrate.
摘要翻译：提供了一种用于侧壁SONOS存储器件的系统和方法。电子设备包括非易失性存储器。衬底包括源极/漏极区域。栅极堆叠直接在衬底上并且在源极/漏极区域之间。栅极堆叠具有侧壁。在栅叠层附近形成氮化物间隔物。第一氧化物材料直接邻近间隔物形成。在间隔物和栅极叠层之间形成氧化物 - 氧化物 - 氧化物结构。氧化物 - 氧化物 - 氧化物结构在栅极堆叠的至少一侧具有大致L形的横截面。氧化物 - 氮化物 - 氧化物结构包括垂直部分和水平部分。垂直部分基本上与侧壁对准并且位于第一氧化物材料和栅极侧壁之间。水平部分基本上与衬底对准并位于第一氧化物和衬底之间。

58. 发明申请

US20050002472A1 OFDM receiver and metric generator thereof 有权
标题翻译： OFDM接收机及其度量发生器
公开(公告)号：US20050002472A1
公开(公告)日：2005-01-06
申请号：US10609496
申请日：2003-07-01
申请人： Tsung-Lin Lee , Rong-Liang Chiou
发明人： Tsung-Lin Lee , Rong-Liang Chiou
IPC分类号： H04L25/06 , H04L27/26 , H04L27/38 , H04L27/06
CPC分类号： H04L25/067 , H04L1/0054 , H04L1/0071 , H04L5/0007 , H04L5/006 , H04L5/0091 , H04L27/38
摘要： A metric generation scheme for use in OFDM receivers. In a preferred embodiment, an OFDM receiver of the invention includes a dynamic quantizer to compress a series of channel-state information values. Also, a bit de-interleaver is provided to de-interleave a series of symbol-based data inverse to interleaving operations at a transmitter end. The de-interleaved symbol-based data is further compressed by another dynamic quantizer to yield a complex signal according to a constellation scheme. Then a metric generator calculates a bit metric of a zero group and a bit metric of a one group for each received bit in which the constellation is divided into the one group and the zero group for each bit location.
摘要翻译：用于OFDM接收机的度量生成方案。在优选实施例中，本发明的OFDM接收机包括用于压缩一系列信道状态信息值的动态量化器。此外，提供了一个解交织器，用于将一系列基于符号的数据逆交换到发送器端处的交织操作。解交织的基于符号的数据被另一个动态量化器进一步压缩，以产生根据星座图方案的复信号。然后，度量发生器为每个接收的比特计算零组的比特量度和一组的比特度量，其中星座被划分成一个组，并且对于每个比特位置分配零组。

59. 发明授权

US08946828B2 Semiconductor device having elevated structure and method of manufacturing the same 有权
标题翻译：具有升高的结构的半导体器件及其制造方法
公开(公告)号：US08946828B2
公开(公告)日：2015-02-03
申请号：US12702683
申请日：2010-02-09
申请人： Sey-Ping Sun , Tsung-Lin Lee , Chin-Hsiang Lin , Chih-Hao Chang , Chen-Nan Yeh , Chao-An Jong
发明人： Sey-Ping Sun , Tsung-Lin Lee , Chin-Hsiang Lin , Chih-Hao Chang , Chen-Nan Yeh , Chao-An Jong
IPC分类号： H01L29/78 , H01L21/768 , H01L29/66
CPC分类号： H01L29/4232 , H01L21/76834 , H01L21/76849 , H01L21/76897 , H01L29/495 , H01L29/4966 , H01L29/66545 , H01L29/78
摘要： A semiconductor device includes a semiconductor substrate; a gate stack overlying the substrate, a spacer formed on sidewalls of the gate stack, and a protection layer overlying the gate stack for filling at least a portion of a space surrounded by the spacer and the top surface of the gate stack. A top surface of the spacer is higher than a top surface of the gate stack.
摘要翻译：半导体器件包括半导体衬底; 覆盖衬底的栅极堆叠，形成在栅极堆叠的侧壁上的间隔物，以及覆盖栅极堆叠的保护层，用于填充由间隔物和栅极堆叠的顶表面围绕的空间的至少一部分。间隔件的顶表面高于栅极堆叠的顶表面。

60. 发明授权

US08653576B2 Method of fabricating a SONOS gate structure with dual-thickness oxide 有权
标题翻译：制造具有双重厚度氧化物的SONOS栅极结构的方法
公开(公告)号：US08653576B2
公开(公告)日：2014-02-18
申请号：US12648598
申请日：2009-12-29
申请人： Tzyh-Cheang Lee , Jiunn-Ren Hwang , Tsung-Lin Lee
发明人： Tzyh-Cheang Lee , Jiunn-Ren Hwang , Tsung-Lin Lee
IPC分类号： H01L29/76
CPC分类号： H01L29/7923 , H01L21/28282 , H01L29/4234
摘要： A method of forming a SONOS gate structure. The method includes forming a gate pattern with sidewalls on a substrate, wherein the gate pattern includes a gate dielectric layer patterned on the substrate and a gate electrode patterned on the gate dielectric layer, forming a first oxide layer on the gate pattern and the substrate; etching back the first oxide layer to expose the substrate and the top of the gate electrode, leaving oxide spacers along the sidewalls of the gate pattern respectively; forming a second oxide layer on the substrate and the oxide spacers; and forming trapping dielectric spacers on the second oxide layer adjacent to the sidewalls of the gate pattern respectively.
摘要翻译：一种形成SONOS门结构的方法。该方法包括在衬底上形成具有侧壁的栅极图案，其中栅极图案包括在衬底上图案化的栅极电介质层和在栅极电介质层上图案化的栅电极，在栅极图案和衬底上形成第一氧化物层; 蚀刻第一氧化物层以暴露衬底和栅电极的顶部，分别沿着栅极图案的侧壁留下氧化物间隔物; 在所述衬底和所述氧化物间隔物上形成第二氧化物层; 以及分别在与栅极图案的侧壁相邻的第二氧化物层上形成俘获电介质间隔物。

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