专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明申请

US20130070835A1 CDR WITH DIGITALLY CONTROLLED LOCK TO REFERENCE 有权
标题翻译：具有数字控制的CDR锁定参考
公开(公告)号：US20130070835A1
公开(公告)日：2013-03-21
申请号：US13235628
申请日：2011-09-19
申请人： Vladimir Sindalovsky , Lane A. Smith , Brett D. Hardy , Jeffrey S. Kueng
发明人： Vladimir Sindalovsky , Lane A. Smith , Brett D. Hardy , Jeffrey S. Kueng
IPC分类号： H04L27/06 , H03K9/08
CPC分类号： H04L7/033 , H03L7/085 , H03L7/087 , H03L7/089 , H03L7/093
摘要： In described embodiments, a receiver includes a clock and data recovery (CDR) circuit with a voltage control oscillator (VCO) having proportional and integral loop control, and a Lock to Reference (L2R) mode circuit using Phase and Frequency Detector (PFD) control of the VCO during the absence of input data to the CDR. A regular CDR second order loop incorporating PFD control of the VCO during the absence of input data to the CDR achieves relatively rapid lock to reference when compared to counter-based lock to reference mode of operation.
摘要翻译：在所描述的实施例中，接收机包括具有比例和积分环路控制的压控振荡器（VCO）的时钟和数据恢复（CDR）电路，以及使用相位和频率检测器（PFD）控制的锁定到参考（L2R）模式电路在没有输入数据到CDR的情况下。在没有到CDR的输入数据的情况下，结合PFD的PFD控制的常规CDR二阶循环与基于操作的基于参考操作的锁相比，实现了相对较快的锁定参考。

52. 发明授权

US07869540B2 Method and apparatus for increased communication channel pre-emphasis for clock-like data patterns 有权
标题翻译：用于增加用于时钟状数据模式的通信信道预加重的方法和装置
公开(公告)号：US07869540B2
公开(公告)日：2011-01-11
申请号：US11506536
申请日：2006-08-18
申请人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Vladimir Sindalovsky
发明人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Vladimir Sindalovsky
IPC分类号： H04L25/49 , H04L25/03 , H04K1/02
CPC分类号： H04L25/03343 , H04L25/0286 , H04L25/03885
摘要： Methods and apparatus are disclosed for increased pre-emphasis for clock-like data patterns to compensate for channel distortions. One aspect of the invention compensates for channel distortions by evaluating a data pattern to be transmitted; determining if the data pattern satisfies one or more predefined criteria defining a clock-like data pattern; and generating a pre-emphasis level for the clock-like data patterns that is higher than a pre-emphasis level for the data patterns that do not satisfy the one or more predefined criteria. For example, a predefined window size can be defined for determining if the data pattern satisfies the one or more predefined criteria defining the clock-like data pattern. In one exemplary implementation, the higher pre-emphasis level is generated for one or more predefined data patterns. A table can optionally be accessed to determine the pre-emphasis level based on the data pattern.
摘要翻译：公开了用于增加对时钟状数据模式的预加重以补偿信道失真的方法和装置。本发明的一个方面通过评估要发送的数据模式来补偿信道失真; 确定数据模式是否满足定义时钟状数据模式的一个或多个预定标准; 以及对于不满足一个或多个预定标准的数据模式的高于预加重级别的时钟状数据模式，生成预加重级别。例如，可以定义预定窗口大小以确定数据模式是否满足定义时钟状数据模式的一个或多个预定标准。在一个示例性实现中，为一个或多个预定义的数据模式生成较高的预加重级别。可以可选地访问表以基于数据模式确定预加重级别。

53. 发明申请

US20100244937A1 Compensation Techniques for Reducing Power Consumption in Digital Circuitry 有权
标题翻译：降低数字电路功耗的补偿技术
公开(公告)号：US20100244937A1
公开(公告)日：2010-09-30
申请号：US12160373
申请日：2007-10-31
申请人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
发明人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： G05F1/10
CPC分类号： H03K19/00369
摘要： A compensation circuit for reducing power consumption in at least one digital circuit includes a first sample circuit connected to a first supply voltage, a second sample circuit connected to a second supply voltage, and a controller connected to the first and second sample circuits. The first and second sample circuits are substantially functionally equivalent to one another but optimized for different regions of operation within a specified range of PVT conditions. The controller is operative to receive respective output signals from the first and second sample circuits, to monitor a functionality of the second sample circuit relative to the first sample circuit, and to adjust a level of the second supply voltage to ensure correct operation of the second sample circuit throughout the specified range of PVT conditions. The digital circuit is operative from the second supply voltage.
摘要翻译：用于降低至少一个数字电路中的功耗的补偿电路包括连接到第一电源电压的第一采样电路，连接到第二电源电压的第二采样电路和连接到第一和第二采样电路的控制器。第一和第二采样电路基本上在功能上彼此相等，但是在PVT条件的指定范围内针对不同操作区域进行了优化。控制器可操作以从第一和第二采样电路接收相应的输出信号，以监测第二采样电路相对于第一采样电路的功能，并调整第二电源电压的电平，以确保第二采样电路的正常工作采样电路在指定的PVT条件范围内。数字电路从第二电源电压工作。

54. 发明授权

US07778377B2 Methods and apparatus for spread spectrum generation using a voltage controlled delay loop 有权
标题翻译：使用电压控制延迟环路进行扩频生成的方法和装置
公开(公告)号：US07778377B2
公开(公告)日：2010-08-17
申请号：US11141695
申请日：2005-05-31
申请人： Vladimir Sindalovsky , Lane A. Smith , Craig B. Ziemer
发明人： Vladimir Sindalovsky , Lane A. Smith , Craig B. Ziemer
IPC分类号： H03D3/24
CPC分类号： H04B15/02 , H04B2215/067
摘要： Methods and apparatus are provided for generating a frequency with a predefined offset from a reference frequency. A spread spectrum generator circuit is disclosed that comprises a voltage controlled delay loop for generating a plurality of signals having a different phase; and at least one interpolator for processing at least two of the signals to generate an output signal having a phase between a phase of the at least two of the signals, wherein the output is varied between a phase of the at least two of the signals to generate the spread spectrum. A spread spectrum having a frequency lower than an applied clock signal is generated using a continuous phase delay increase and a spread spectrum having a frequency higher than the clock signal is generated using a continuous phase delay decrease.
摘要翻译：提供了用于产生具有与参考频率的预定义偏移的频率的方法和装置。公开了一种扩频发生器电路，其包括用于产生具有不同相位的多个信号的电压控制延迟环路; 以及至少一个内插器，用于处理至少两个所述信号以产生具有所述至少两个所述信号的相位之间的相位的输出信号，其中所述输出在所述至少两个信号的相位之间变化生成扩频。使用连续的相位延迟增加来产生频率低于所施加的时钟信号的扩展频谱，并且使用连续的相位延迟减小产生具有高于时钟信号的频率的扩频。

55. 发明授权

US07561653B2 Method and apparatus for automatic clock alignment 有权
标题翻译：自动时钟对准的方法和装置
公开(公告)号：US07561653B2
公开(公告)日：2009-07-14
申请号：US11174228
申请日：2005-07-01
申请人： Vladimir Sindalovsky , Lane A. Smith
发明人： Vladimir Sindalovsky , Lane A. Smith
IPC分类号： H03D3/24
CPC分类号： H03L7/07 , H03L7/0814 , H04L7/0337
摘要： The present invention synchronizes signals generated and used in different clock domains. The invention is applicable to a CDR circuit in which phase adjustment of a multiphase clock to the phase of incoming data is implemented by controlling phase offsets from the PLL frequency relative to data sampling points Si and transition sampling points Ti. In particular, these offsets are controlled by both coarse and fine adjustments.Typically CDR circuits employ feedback phase control information being supplied to the VCDL. The above described adjustments result in these phase control signals having an arbitrary and time-changing relation to the PLL clock. By properly selecting an appropriate edge of the PLL clock signal, the present invention synchronizes these phase control signals into the PLL clock domain in order to apply VCDL control in a synchronous manner.
摘要翻译：本发明使在不同时钟域中产生和使用的信号同步。本发明适用于通过从相对于数据采样点Si和过渡采样点Ti控制来自PLL频率的相位偏移来实现多相时钟到输入数据相位的相位调整的CDR电路。特别地，这些偏移由粗调和微调两者来控制。通常，CDR电路使用提供给VCDL的反馈相位控制信息。上述调整导致这些相位控制信号具有与PLL时钟的任意和时变关系。通过适当地选择PLL时钟信号的适当边沿，本发明将这些相位控制信号同步到PLL时钟域中，以便以同步方式应用VCDL控制。

56. 发明授权

US07346879B2 Symmetric signal distribution through abutment connection 失效
标题翻译：通过对接连接的对称信号分配
公开(公告)号：US07346879B2
公开(公告)日：2008-03-18
申请号：US10880216
申请日：2004-06-29
申请人： Jung Cho , Robert M. Kylor , Vladimir Sindalovsky , Lane A. Smith
发明人： Jung Cho , Robert M. Kylor , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077
摘要： The present invention provides a method and apparatus for managing a large number of associated interconnects within an integrated circuit involving a modular approach to the macro cell layout. In particular, internal signal paths are created within each macro cell that permit connections to other macros by abutting these macros adjacent to one another. Moreover, these internal signal paths permit efficient distribution of a common source signal to each of such connected macros. The layout of the internal macro cell signal paths of the present invention also permits each of these macros to be reflected about its Y-axis, thereby increasing its versatility in being utilized in various circuit designs.
摘要翻译：本发明提供一种用于管理涉及宏小区布局的模块化方法的集成电路内的大量相关互连的方法和装置。特别地，在每个宏小区内创建内部信号路径，允许通过将这些宏邻接的方式连接到其他宏。此外，这些内部信号路径允许将公共源信号有效地分配给每个这样连接的宏。本发明的内部宏单元信号路径的布局还允许这些宏中的每一个都围绕其Y轴反射，从而增加其在各种电路设计中的使用的多功能性。

57. 发明申请

US20070253517A1 Method and apparatus for integral state initialization and quality of lock monitoring in a clock and data recovery system 有权
标题翻译：用于整体状态初始化的方法和装置以及时钟和数据恢复系统中锁定监视的质量
公开(公告)号：US20070253517A1
公开(公告)日：2007-11-01
申请号：US11414521
申请日：2006-04-28
申请人： Pervez Aziz , Gregory Sheets , Vladimir Sindalovsky
发明人： Pervez Aziz , Gregory Sheets , Vladimir Sindalovsky
IPC分类号： H03D3/24
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/093 , H04L7/0004 , H04L7/0331
摘要： Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or more quality of lock (QOL) metrics are also monitored that are derived from the integral register state value. A quality of a locking between a received signal and a local clock generated by a Clock and Data Recovery (CDR) system is evaluated by monitoring a state value of an integral register in a digital loop filter of the CDR system; evaluating one or more predefined criteria based on the integral register state value; and identifying a poor lock condition if the one or more predefined criteria are not satisfied.
摘要翻译：提供了用于提高二级CDR系统的性能的方法和装置。 CDR系统的整体状态被初始化为基于对于某些应用可以是先验已知的预期频率分布的值。还监视从积分寄存器状态值导出的一个或多个锁定质量（QOL）度量。通过监视CDR系统的数字环路滤波器中的积分寄存器的状态值来评估由时钟和数据恢复（CDR）系统产生的接收信号和本地时钟之间的锁定的质量; 基于积分寄存器状态值来评估一个或多个预定标准; 并且如果不满足一个或多个预定标准，则识别差的锁定条件。

58. 发明授权

US07003094B2 Adaptive interference cancellation for ADSL 有权
公开(公告)号：US07003094B2
公开(公告)日：2006-02-21
申请号：US09730781
申请日：2000-12-07
申请人： Jonathan Herman Fischer , Donald Raymond Laturell , Vladimir Sindalovsky
发明人： Jonathan Herman Fischer , Donald Raymond Laturell , Vladimir Sindalovsky
IPC分类号： H04M9/08
CPC分类号： H04B3/23 , H04B1/1036
摘要： An ADSL front end is implemented with an adaptive AM interference canceller to cancel out either a carrier signal of an interfering AM radio signal, or a carrier signal and its sidebands of an interfering AM radio signal, from a received ADSL signal. By canceling an interfering AM radio signal rather than simply filtering out the relevant interfered with frequency band, the interfered with frequency band remains useable for ADSL transmission. In one embodiment, a reference AM radio receiver is either fixedly or adaptively tuned to the carrier frequency of an interfering AM radio station, and the received signal in the frequency band surrounding that carrier frequency is digitized and provided to an adaptive interference canceller. The adaptive interference canceller adaptively adjusts a time delay and phase of the generated AM interference signal to optimize cancellation at a hybrid of the same AM radio signal received as interference over a subscriber line. The AM interference canceller may include a Hilbert bandpass filter, tuned to an appropriate carrier frequency by, e.g., an FFT analyzer. An LMS module adaptively adjusts the parameters of the I and Q channels of the Hilbert filter. In another embodiment, instead of including a reference AM radio receiver, only the carrier signal is removed from the received ADSL signal, leaving the presumably less significant sidebands intact. Preferably, a ratio of differential mode coupling to common mode coupling of the interfering AM radio station is determined to result in a better cancellation of the coupled AM interference signal.

59. 发明授权

US06745265B1 Method and apparatus for generating status flags in a memory device 失效
标题翻译：用于在存储器件中产生状态标志的方法和装置
公开(公告)号：US06745265B1
公开(公告)日：2004-06-01
申请号：US09531368
申请日：2000-03-21
申请人： Vladimir Sindalovsky
发明人： Vladimir Sindalovsky
IPC分类号： G06F300
CPC分类号： G06F5/12 , G06F2205/102 , G06F2205/126
摘要： A FIFO is provided which includes gray-encoded READ and WRITE counters in which partial capacity flags (referred to collectively as “WATERMARK level” flags herein) are generated when the difference between the count values in the two counters exceeds a first threshold level and which resets the flag when the difference between the count values drops below a second, lower threshold level. In accordance with the present invention, a single gray-coded WRITE pointer counter comprises a WRITE pointer register and a gray-code increment block. A READ pointer register comprises a shift register and a gray code increment block having plural stages and storing consecutive incremental WATERMARK values, based on the READ pulse count, therein. With each successive READ clock pulse, consecutive WATERMARK values are stored in the plural-stage READ pointer register, and with each READ clock pulse these values are incremented by one. The plural WATERMARK values are compared with the current value of the WRITE pointer register. By analyzing the current WRITE pointer value in connection with the plural consecutive WATERMARK values, the direction (ascending or descending) of the compared values can be determined and, due to the redundancy available from the multi-level WATERMARK values stored in the READ pointer register, hystersis is introduced so that the partial capacity flags are generated only when the difference between the READ and WRITE pulses crosses the WATERMARK level.
摘要翻译：提供FIFO，其包括灰度编码的READ和WRITE计数器，其中当两个计数器中的计数值之间的差超过第一阈值电平时，产生部分容量标志（这里统称为“WATERMARK级”标志）），并且哪个当计数值之间的差值下降到低于第二阈值水平时，复位该标志。根据本发明，单个灰度编码的WRITE指针计数器包括WRITE指针寄存器和灰度增量块。读指针寄存器包括移位寄存器和具有多级的灰度增量块，并且基于其读脉冲计数存储连续的增量WATERMARK值。对于每个连续的READ时钟脉冲，连续的WATERMARK值存储在多级READ指针寄存器中，并且对于每个READ时钟脉冲，这些值递增1。将多个WATERMARK值与WRITE指针寄存器的当前值进行比较。通过分析与多个连续WATERMARK值相关的当前WRITE指针值，可以确定比较值的方向（升序或降序），并且由于存储在READ指针寄存器中的多级WATERMARK值可用的冗余引入Hystersis，使得仅当READ和WRITE脉冲之间的差异超过WATERMARK电平时才产生部分容量标志。

60. 发明授权

US06525681B2 DC compensation method and apparatus 有权
公开(公告)号：US06525681B2
公开(公告)日：2003-02-25
申请号：US09820475
申请日：2001-03-29
申请人： Vladimir Sindalovsky , Donald Raymond Laturell
发明人： Vladimir Sindalovsky , Donald Raymond Laturell
IPC分类号： H03M110
CPC分类号： H03M1/1019 , H03M1/12 , H03M1/66
摘要： A method and apparatus which compensates for the effect of DC components due to imperfections in analog circuits used in a coder/decoder (CODEC) by adding a compensation value to an outgoing signal prior to the DC components being introduced. The method includes the steps of determining a compensation value to compensate for the effect of the DC components due to imperfections in analog circuits in a CODEC and adding the compensation value to a path within the CODEC. The apparatus includes an adder coupled in at least one outgoing path of the CODEC, the adder having an input for coupling to a DSP, wherein the DSP determines a DC compensation value to compensate for the effect of the DC components and the adder adds the DC compensation value to the outgoing path.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式