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1. 发明授权

US07965133B2 Compensation techniques for reducing power consumption in digital circuitry 有权
标题翻译：用于降低数字电路功耗的补偿技术
公开(公告)号：US07965133B2
公开(公告)日：2011-06-21
申请号：US12160373
申请日：2007-10-31
申请人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
发明人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： G05F1/10
CPC分类号： H03K19/00369
摘要： A compensation circuit for reducing power consumption in at least one digital circuit includes a first sample circuit connected to a first supply voltage, a second sample circuit connected to a second supply voltage, and a controller connected to the first and second sample circuits. The first and second sample circuits are substantially functionally equivalent to one another but optimized for different regions of operation within a specified range of PVT conditions. The controller is operative to receive respective output signals from the first and second sample circuits, to monitor a functionality of the second sample circuit relative to the first sample circuit, and to adjust a level of the second supply voltage to ensure correct operation of the second sample circuit throughout the specified range of PVT conditions. The digital circuit is operative from the second supply voltage.
摘要翻译：用于降低至少一个数字电路中的功耗的补偿电路包括连接到第一电源电压的第一采样电路，连接到第二电源电压的第二采样电路和连接到第一和第二采样电路的控制器。第一和第二采样电路基本上在功能上彼此相等，但是在PVT条件的指定范围内针对不同操作区域进行了优化。控制器可操作以从第一和第二采样电路接收相应的输出信号，以监测第二采样电路相对于第一采样电路的功能，并调整第二电源电压的电平，以确保第二采样电路的正常工作采样电路在指定的PVT条件范围内。数字电路从第二电源电压工作。

2. 发明授权

US07711043B2 Method and apparatus for determining latch position for decision-feedback equalization using single-sided eye 失效
标题翻译：用于使用单面眼确定用于判决反馈均衡的闩锁位置的方法和装置
公开(公告)号：US07711043B2
公开(公告)日：2010-05-04
申请号：US11540946
申请日：2006-09-29
申请人： Mohammad S. Mobin , Gary E. Schiessler , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
发明人： Mohammad S. Mobin , Gary E. Schiessler , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03057 , H04L2025/03503
摘要： Methods and apparatus are provided for determining the threshold position of one or more latches employed for decision-feedback equalization. A threshold position of a latch employed by a decision-feedback equalizer is determined by constraining input data such that the input data only contains transitions from a first binary value; obtaining a plurality of samples of a single-sided data eye associated with the constrained input data; and determining a threshold position of the latch based on the samples. The constrained input data can comprise (i) transitions from a binary value of 1 to a binary value of 0 or 1; or (ii) transitions from a binary value of 0 to a binary value of 0 or 1. The size of the single-sided data eye can be obtained by analyzing a histogram associated with the single-sided data eye to identify a region having a constant hit count.
摘要翻译：提供了用于确定用于判决反馈均衡的一个或多个锁存器的阈值位置的方法和装置。通过约束输入数据来确定由判决反馈均衡器采用的锁存器的阈值位置，使得输入数据仅包含来自第一二进制值的转换; 获得与所述约束输入数据相关联的单面数据眼睛的多个样本; 以及基于所述样本确定所述锁存器的阈值位置。受约束的输入数据可以包括（i）从二进制值1到二进制值0或1的转换; 或（ii）从二进制值0到二进制值0或1的转换。单面数据眼的大小可以通过分析与单面数据眼相关联的直方图来识别具有不断的命中数。

3. 发明授权

US07869540B2 Method and apparatus for increased communication channel pre-emphasis for clock-like data patterns 有权
标题翻译：用于增加用于时钟状数据模式的通信信道预加重的方法和装置
公开(公告)号：US07869540B2
公开(公告)日：2011-01-11
申请号：US11506536
申请日：2006-08-18
申请人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Vladimir Sindalovsky
发明人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Vladimir Sindalovsky
IPC分类号： H04L25/49 , H04L25/03 , H04K1/02
CPC分类号： H04L25/03343 , H04L25/0286 , H04L25/03885
摘要： Methods and apparatus are disclosed for increased pre-emphasis for clock-like data patterns to compensate for channel distortions. One aspect of the invention compensates for channel distortions by evaluating a data pattern to be transmitted; determining if the data pattern satisfies one or more predefined criteria defining a clock-like data pattern; and generating a pre-emphasis level for the clock-like data patterns that is higher than a pre-emphasis level for the data patterns that do not satisfy the one or more predefined criteria. For example, a predefined window size can be defined for determining if the data pattern satisfies the one or more predefined criteria defining the clock-like data pattern. In one exemplary implementation, the higher pre-emphasis level is generated for one or more predefined data patterns. A table can optionally be accessed to determine the pre-emphasis level based on the data pattern.
摘要翻译：公开了用于增加对时钟状数据模式的预加重以补偿信道失真的方法和装置。本发明的一个方面通过评估要发送的数据模式来补偿信道失真; 确定数据模式是否满足定义时钟状数据模式的一个或多个预定标准; 以及对于不满足一个或多个预定标准的数据模式的高于预加重级别的时钟状数据模式，生成预加重级别。例如，可以定义预定窗口大小以确定数据模式是否满足定义时钟状数据模式的一个或多个预定标准。在一个示例性实现中，为一个或多个预定义的数据模式生成较高的预加重级别。可以可选地访问表以基于数据模式确定预加重级别。

4. 发明申请

US20100244937A1 Compensation Techniques for Reducing Power Consumption in Digital Circuitry 有权
标题翻译：降低数字电路功耗的补偿技术
公开(公告)号：US20100244937A1
公开(公告)日：2010-09-30
申请号：US12160373
申请日：2007-10-31
申请人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
发明人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： G05F1/10
CPC分类号： H03K19/00369
摘要： A compensation circuit for reducing power consumption in at least one digital circuit includes a first sample circuit connected to a first supply voltage, a second sample circuit connected to a second supply voltage, and a controller connected to the first and second sample circuits. The first and second sample circuits are substantially functionally equivalent to one another but optimized for different regions of operation within a specified range of PVT conditions. The controller is operative to receive respective output signals from the first and second sample circuits, to monitor a functionality of the second sample circuit relative to the first sample circuit, and to adjust a level of the second supply voltage to ensure correct operation of the second sample circuit throughout the specified range of PVT conditions. The digital circuit is operative from the second supply voltage.
摘要翻译：用于降低至少一个数字电路中的功耗的补偿电路包括连接到第一电源电压的第一采样电路，连接到第二电源电压的第二采样电路和连接到第一和第二采样电路的控制器。第一和第二采样电路基本上在功能上彼此相等，但是在PVT条件的指定范围内针对不同操作区域进行了优化。控制器可操作以从第一和第二采样电路接收相应的输出信号，以监测第二采样电路相对于第一采样电路的功能，并调整第二电源电压的电平，以确保第二采样电路的正常工作采样电路在指定的PVT条件范围内。数字电路从第二电源电压工作。

5. 发明授权

US07649933B2 Method and apparatus for determining a position of an offset latch employed for decision-feedback equalization 有权
标题翻译：用于确定用于判决反馈均衡的偏移锁存器的位置的方法和装置
公开(公告)号：US07649933B2
公开(公告)日：2010-01-19
申请号：US11414522
申请日：2006-04-28
申请人： Christopher J. Abel , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
发明人： Christopher J. Abel , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/062 , H04L25/03057
摘要： Methods and apparatus are provided for determining a position of an offset latch employed for decision-feedback equalization. The position of an offset latch is determined by obtaining a plurality of samples of a data eye associated with a signal, the data eye comprised of a plurality of trajectories for transitions out of a given binary state; determining an amplitude of at least two of the trajectories based on the samples; and determining a position of an offset latch based on the determined amplitudes. The initial position of the offset latch can be placed, for example, approximately in the middle of the determined amplitudes for at least two of the trajectories. The initial position of the offset latch can be optionally skewed by a predefined amount to improve the noise margin.
摘要翻译：提供了用于确定用于判决反馈均衡的偏移锁存器的位置的方法和装置。通过获得与信号相关联的数据眼睛的多个采样来确定偏移锁存器的位置，数据眼睛包括用于从给定二进制状态转换的多个轨迹; 基于样本确定至少两个轨迹的振幅; 以及基于所确定的振幅来确定偏移锁存器的位置。偏移锁存器的初始位置例如可以放置在至少两个轨迹的确定幅度的中间。偏移锁存器的初始位置可以可选地倾斜预定义的量以改善噪声容限。

6. 发明申请

US20080080608A1 Method and apparatus for determining latch position for decision-feedback equalization using single-sided eye 失效
标题翻译：用于使用单面眼确定用于判决反馈均衡的闩锁位置的方法和装置
公开(公告)号：US20080080608A1
公开(公告)日：2008-04-03
申请号：US11540946
申请日：2006-09-29
申请人： Mohammad S. Mobin , Gary E. Schiessler , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
发明人： Mohammad S. Mobin , Gary E. Schiessler , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： H03H7/30
CPC分类号： H04L25/03057 , H04L2025/03503
摘要： Methods and apparatus are provided for determining the threshold position of one or more latches employed for decision-feedback equalization. A threshold position of a latch employed by a decision-feedback equalizer is determined by constraining input data such that the input data only contains transitions from a first binary value; obtaining a plurality of samples of a single-sided data eye associated with the constrained input data; and determining a threshold position of the latch based on the samples. The constrained input data can comprise (i) transitions from a binary value of 1 to a binary value of 0 or 1; or (ii) transitions from a binary value of 0 to a binary value of 0 or 1. The size of the single-sided data eye can be obtained by analyzing a histogram associated with the single-sided data eye to identify a region having a constant hit count.
摘要翻译：提供了用于确定用于判决反馈均衡的一个或多个锁存器的阈值位置的方法和装置。通过约束输入数据来确定由判决反馈均衡器采用的锁存器的阈值位置，使得输入数据仅包含来自第一二进制值的转换; 获得与所述约束输入数据相关联的单面数据眼睛的多个样本; 以及基于所述样本确定所述锁存器的阈值位置。受约束的输入数据可以包括（i）从二进制值1到二进制值0或1的转换; 或（ii）从二进制值0到二进制值0或1的转换。单面数据眼的大小可以通过分析与单面数据眼相关联的直方图来识别具有不断的命中数。

7. 发明申请

US20080043876A1 Method and apparatus for increased communication channel pre-emphasis for clock-like data patterns 有权
标题翻译：用于增加用于时钟状数据模式的通信信道预加重的方法和装置
公开(公告)号：US20080043876A1
公开(公告)日：2008-02-21
申请号：US11506536
申请日：2006-08-18
申请人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Vladimir Sindalovsky
发明人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Vladimir Sindalovsky
IPC分类号： H04B15/00
CPC分类号： H04L25/03343 , H04L25/0286 , H04L25/03885
摘要： Methods and apparatus are disclosed for increased pre-emphasis for clock-like data patterns to compensate for channel distortions. One aspect of the invention compensates for channel distortions by evaluating a data pattern to be transmitted; determining if the data pattern satisfies one or more predefined criteria defining a clock-like data pattern; and generating a pre-emphasis level for the clock-like data patterns that is higher than a pre-emphasis level for the data patterns that do not satisfy the one or more predefined criteria. For example, a predefined window size can be defined for determining if the data pattern satisfies the one or more predefined criteria defining the clock-like data pattern. In one exemplary implementation, the higher pre-emphasis level is generated for one or more predefined data patterns. A table can optionally be accessed to determine the pre-emphasis level based on the data pattern.
摘要翻译：公开了用于增加对时钟状数据模式的预加重以补偿信道失真的方法和装置。本发明的一个方面通过评估要发送的数据模式来补偿信道失真; 确定数据模式是否满足定义时钟状数据模式的一个或多个预定标准; 以及对于不满足一个或多个预定标准的数据模式的高于预加重级别的时钟状数据模式，生成预加重级别。例如，可以定义预定窗口大小以确定数据模式是否满足定义时钟状数据模式的一个或多个预定标准。在一个示例性实现中，为一个或多个预定义的数据模式生成较高的预加重级别。可以可选地访问表以基于数据模式确定预加重级别。

8. 发明授权

US07923868B2 Method and apparatus for adjusting a power supply of an integrated circuit 有权
标题翻译：用于调整集成电路的电源的方法和装置
公开(公告)号：US07923868B2
公开(公告)日：2011-04-12
申请号：US12012761
申请日：2008-02-05
申请人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
发明人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： H02J3/00
CPC分类号： H03K19/0027 , G06F1/3203 , H03K19/00384 , Y10T307/74
摘要： Disclosed is a circuit configured to apply a supply voltage to a switching element (e.g., a transistor). The circuit includes a latch and a processor. The latch is configured to sample a voltage of an output signal of the switching element, and the processor is configured to generate a power adjustment signal to adjust the supply voltage based on the voltage sampled by the latch.
摘要翻译：公开了一种被配置为向开关元件（例如，晶体管）施加电源电压的电路。该电路包括一个锁存器和一个处理器。锁存器被配置为对开关元件的输出信号的电压进行采样，并且处理器被配置为产生功率调整信号，以基于由锁存器采样的电压来调节电源电压。

9. 发明申请

US20080191789A1 Method and apparatus for adjusting a power supply of an integrated circuit 有权
标题翻译：用于调整集成电路的电源的方法和装置
公开(公告)号：US20080191789A1
公开(公告)日：2008-08-14
申请号：US12012761
申请日：2008-02-05
申请人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
发明人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： G05F1/10
CPC分类号： H03K19/0027 , G06F1/3203 , H03K19/00384 , Y10T307/74
摘要： Disclosed is a circuit configured to apply a supply voltage to a switching element (e.g., a transistor). The circuit includes a latch and a processor. The latch is configured to sample a voltage of an output signal of the switching element, and the processor is configured to generate a power adjustment signal to adjust the supply voltage based on the voltage sampled by the latch.
摘要翻译：公开了一种被配置为向开关元件（例如，晶体管）施加电源电压的电路。该电路包括一个锁存器和一个处理器。锁存器被配置为对开关元件的输出信号的电压进行采样，并且处理器被配置为产生功率调整信号，以基于由锁存器采样的电压来调节电源电压。

10. 发明授权

US07312667B2 Statically controlled clock source generator for VCDL clock phase trimming 失效
标题翻译：用于VCDL时钟相位修整的静态时钟源发生器
公开(公告)号：US07312667B2
公开(公告)日：2007-12-25
申请号：US11221316
申请日：2005-09-07
申请人： Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith , Craig B. Ziemer
发明人： Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith , Craig B. Ziemer
IPC分类号： H03B27/00
CPC分类号： H03L7/00 , H04L7/0337
摘要： The present invention addresses the generation of a controlled clock source for use in trimming VCDL delay line output clocks. In this trimming process, adjustments are made for static variations in these output clocks. The invention's use of a controlled clock source eliminates the need for this trimming process to be conducted in real time and reduces the expense of the circuitry required.
摘要翻译：本发明解决了用于微调VCDL延迟线输出时钟的受控时钟源的产生。在这个修整过程中，对这些输出时钟的静态变化进行调整。本发明使用受控的时钟源消除了对该修整过程的实时性的需要，并且降低了所需电路的费用。

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