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51. 发明申请

US20050175286A1 TAPERED STRUCTURE FOR PROVIDING COUPLING BETWEEN EXTERNAL OPTICAL DEVICE AND PLANAR OPTICAL WAVEGUIDE AND METHOD OF FORMING THE SAME 有权
标题翻译：用于提供外部光学装置与平面光波导之间的耦合的光栅结构及其形成方法
公开(公告)号：US20050175286A1
公开(公告)日：2005-08-11
申请号：US10775872
申请日：2004-02-10
申请人： Vipulkumar Patel , Prakash Gothoskar , Robert Montgomery , Margaret Ghiron
发明人： Vipulkumar Patel , Prakash Gothoskar , Robert Montgomery , Margaret Ghiron
IPC分类号： G02B6/10 , G02B6/34 , G02B6/42
CPC分类号： G02B6/42 , G02B6/34 , G02B6/4214
摘要： Methods of forming a tapered evanescent coupling region for use with a relatively thin silicon optical waveguide formed with, for example, an SOI structure. A tapered evanescent coupling region is formed in a silicon substrate that is used as a coupling substrate, the coupling substrate thereafter joined to the SOI structure. A gray-scale photolithography process is used to define a tapered region in photoresist, the tapered pattern thereafter transferred into the silicon substrate. A material exhibiting a lower refractive index than the silicon optical waveguide layer (e.g., silicon dioxide) is then used to fill the tapered opening in the substrate. Advantageously, conventional silicon processing steps may be used to form coupling facets in the silicon substrate (i.e., angled surfaces, V-grooves) in an appropriate relation to the tapered evanescent coupling region. The coupling facets may be formed contiguous with the tapered evanescent coupling region, or formed through the opposing side of the silicon substrate.
摘要翻译：形成锥形渐逝耦合区域的方法，用于与例如SOI结构形成的相对薄的硅光波导一起使用。在用作耦合衬底的硅衬底中形成锥形渐逝耦合区，然后耦合衬底连接到SOI结构。使用灰度光刻工艺来限定光致抗蚀剂中的锥形区域，此后的锥形图案转移到硅衬底中。然后使用显示比硅光波导层（例如二氧化硅）低的折射率的材料来填充衬底中的锥形开口。有利地，可以使用常规的硅处理步骤以与锥形渐逝耦合区域适当的关系在硅衬底（即成角度的表面，V形槽）中形成耦合面。耦合面可以形成为与锥形渐逝耦合区域相邻，或者通过硅衬底的相对侧形成。

52. 发明申请

US20050110108A1 Silicon-based Schottky barrier infrared optical detector 有权
标题翻译：硅基肖特基势垒红外光检测器
公开(公告)号：US20050110108A1
公开(公告)日：2005-05-26
申请号：US10990725
申请日：2004-11-17
申请人： Vipulkumar Patel , Margaret Ghiron , Prakash Gothoskar , Robert Montgomery , Soham Pathak , David Piede , Kalpendu Shastri , Katherine Yanushefski
发明人： Vipulkumar Patel , Margaret Ghiron , Prakash Gothoskar , Robert Montgomery , Soham Pathak , David Piede , Kalpendu Shastri , Katherine Yanushefski
IPC分类号： G02B6/12 , G02B6/122 , H01L31/00 , H01L31/0224 , H01L31/0232 , H01L31/0392 , H01L31/108 , H01L31/153
CPC分类号： H01L31/108 , G02B6/12004 , G02B6/1228 , H01L31/022408 , H01L31/0232 , H01L31/03921 , H01L31/153 , Y02E10/50
摘要： A silicon-based IR photodetector is formed within a silicon-on-insulator (SOI) structure by placing a metallic strip (preferably, a silicide) over a portion of an optical waveguide formed within a planar silicon surface layer (i.e., “planar SOI layer”) of the SOI structure, the planar SOI layer comprising a thickness of less than one micron. Room temperature operation of the photodetector is accomplished as a result of the relatively low dark current associated with the SOI-based structure and the ability to use a relatively small surface area silicide strip to collect the photocurrent. The planar SOI layer may be doped, and the geometry of the silicide strip may be modified, as desired, to achieve improved results over prior art silicon-based photodetectors.
摘要翻译：通过将金属条（优选硅化物）放置在形成在平面硅表面层内的光波导的一部分（即，“平面SOI”）上，在绝缘体上硅（SOI）结构中形成硅基红外光电检测器层“），平面SOI层包括小于1微米的厚度。由于与基于SOI的结构相关联的相对较低的暗电流和使用相对小的表面积硅化物带收集光电流的能力，光电检测器的室温操作是完成的。可以掺杂平面SOI层，并且根据需要可以修改硅化物带的几何形状，以实现相对于现有技术的硅基光电探测器的改进的结果。

53. 发明授权

US07706644B2 Offset launch mode from nanotaper waveguide into multimode fiber 有权
标题翻译：从纳米孔波导到多模光纤的偏移发射模式
公开(公告)号：US07706644B2
公开(公告)日：2010-04-27
申请号：US12218367
申请日：2008-07-15
申请人： Mark Webster , Prakash Gothoskar , Vipulkumar Patel , David Piede
发明人： Mark Webster , Prakash Gothoskar , Vipulkumar Patel , David Piede
IPC分类号： G02B6/26
CPC分类号： G02B6/30 , G02B6/3598 , G02B6/3636 , G02B6/3652 , G02B6/3692 , G02B6/4249
摘要： One or more nanotaper coupling waveguides formed within an optical substrate allows for straightforward, reproducible offset launch conditions to be achieved between an incoming signal and the core region of a multimode fiber (which may be disposed along an alignment fixture formed in the optical substrate), fiber array or other multimode waveguiding structure. Offset launching of a single mode signal into a multimode fiber couples the signal into favorable spatial modes which reduce the presence of differential mode dispersion along the fiber. This approach to providing single mode signal coupling into legacy multimode fiber is considered to be an improvement over the prior art which required the use of an interface element between a single mode fiber and multimode fiber, limiting the number of propagating signals and applications for the legacy multimode fiber. An optical switch may be used to select the specific nanotaper(s) for coupling into the multimode fiber.
摘要翻译：形成在光学衬底内的一个或多个纳米锥耦合波导允许在多模光纤（其可以沿着形成在光学衬底中的对准夹具设置）的入射信号和芯区域之间实现简单，可再现的偏移发射条件，光纤阵列或其他多模波导结构。偏移将单模信号发射到多模光纤中将信号耦合到有利的空间模式，这降低了沿着光纤的差分色散的存在。将单模信号耦合提供给传统多模光纤的这种方法被认为是对需要使用单模光纤和多模光纤之间的接口元件的现有技术的改进，限制了传播信号的数量和遗留的应用多模光纤可以使用光学开关来选择用于耦合到多模光纤的特定纳米锥。

54. 发明申请

US20110222812A1 Dopant Profile Control For High Speed Silicon-Based Optical Modulators 有权
标题翻译：高速硅基光调制器的掺杂分布控制
公开(公告)号：US20110222812A1
公开(公告)日：2011-09-15
申请号：US13029342
申请日：2011-02-17
申请人： Mark Webster , Vipulkumar Patel , Prakash Gothoskar , David Piede
发明人： Mark Webster , Vipulkumar Patel , Prakash Gothoskar , David Piede
IPC分类号： G02F1/01
CPC分类号： G02B6/12 , G02B6/26 , G02B26/00 , G02F1/025
摘要： A high speed silicon-based optical modulator with control of the dopant profiles in the body and gate regions of the device reduces the series resistance of the structure without incurring substantial optical power loss. That is, the use of increased dopant values in areas beyond the active region will allow for the series resistance to be reduced (and thus increase the modulating speed of the device) without incurring too large a penalty in signal loss. The dopant profiles within the gate and body regions are tailored to exhibit an intermediate value between the high dopant concentration in the contact areas and the low dopant concentration in the carrier integration window area.
摘要翻译：具有控制器件的主体和栅极区域中的掺杂剂分布的高速硅基光学调制器降低了结构的串联电阻而不会引起实质的光功率损耗。也就是说，在有源区域之外的区域中使用增加的掺杂剂值将允许降低串联电阻（从而增加器件的调制速度），而不会在信号损失中造成太大的惩罚。调整栅极和体区内的掺杂剂分布，以显示接触区域中的高掺杂剂浓度与载流子集成窗口区域中的低掺杂剂浓度之间的中间值。

55. 发明申请

US20090103850A1 Silicon-based optical modulator for analog applications 有权
标题翻译：用于模拟应用的硅基光调制器
公开(公告)号：US20090103850A1
公开(公告)日：2009-04-23
申请号：US12287366
申请日：2008-10-08
申请人： Kaipendu Shastri , Prakash Gothoskar , Vipulkumar Patel , David Piede , Mark Webster
发明人： Kaipendu Shastri , Prakash Gothoskar , Vipulkumar Patel , David Piede , Mark Webster
IPC分类号： G02F1/035
CPC分类号： G02F1/0121 , G02F1/2255 , G02F1/2257 , G02F2001/0152
摘要： A silicon-insulator-silicon capacitive (SISCAP) optical modulator is configured to provide analog operation for applications which previously required the use of relatively large, power-consuming and expensive lithium niobate devices. An MZI-based SISCAP modulator (preferably a balanced arrangement with a SISCAP device on each arm) is responsive to an incoming high frequency electrical signal and is biased in a region where the capacitance of the device is essentially constant and the transform function of the MZI is linear.
摘要翻译：硅 - 绝缘体 - 硅电容（SISCAP）光调制器被配置为为先前需要使用相对较大，耗电和昂贵的铌酸锂器件的应用提供模拟操作。基于MZI的SISCAP调制器（优选地，在每个臂上具有SISCAP器件的平衡布置）响应于输入的高频电信号，并且被偏置在器件的电容基本上恒定的区域中，并且MZI的变换函数是线性的

56. 发明申请

US20050289490A1 Integrated approach for design, simulation and verification of monolithic, silicon-based opto-electronic circuits 有权
标题翻译：用于单片硅基光电路的设计，仿真和验证的综合方法
公开(公告)号：US20050289490A1
公开(公告)日：2005-12-29
申请号：US11159283
申请日：2005-06-22
申请人： Kalpendu Shastri , Soham Pathak , Prakash Gothoskar , Paulius Mosinskis , Bipin Dama
发明人： Kalpendu Shastri , Soham Pathak , Prakash Gothoskar , Paulius Mosinskis , Bipin Dama
IPC分类号： G06F17/50 , G06G7/62
CPC分类号： G06F17/5036 , G06F17/5068
摘要： Computer-aided design (CAD) tools are used to perform the integrated design, verification and layout of electrical and optical components in a monolithic, silicon-based electro-optic chip. Separate top-level behavioral logic designs are prepared for the three different types of elements included within the final, silicon-based monolithic structure: (1) digital electronic integrated circuit elements; (2) analog/mixed signal electronic integrated circuit elements; and (3) opto-electronic elements (including passive and active optical elements). Once the behavioral logic design is completed, the results are combined and co-simulated. A physical layout design is developed and verified for each different type of element in the circuit. The separate physical layouts are then co-verified, to assess the properties of the overall physical design. The results of the co-simulation are compared to the results of the co-verification, with alterations made in the logic design and/or the physical layout until the desired operating parameters are obtained. Once the desired results are generated, conventional wafer-level fabrication operations are then considered to provide a final product (“tape out”).
摘要翻译：计算机辅助设计（CAD）工具用于在单片硅基电光芯片中执行电气和光学部件的集成设计，验证和布局。为最终的硅基单片结构中包含的三种不同类型的元件准备了独立的顶级行为逻辑设计：（1）数字电子集成电路元件; （2）模拟/混合信号电子集成电路元件; 和（3）光电元件（包括无源和有源光学元件）。一旦行为逻辑设计完成，结果将被合并并共同模拟。为电路中的每种不同类型的元件开发和验证物理布局设计。然后将单独的物理布局共同验证，以评估整体物理设计的属性。将共模拟的结果与协同验证的结果进行比较，在逻辑设计和/或物理布局中进行改变，直到获得所需的操作参数。一旦产生期望的结果，则常规晶圆级制造操作被认为是提供最终产品（“磁带输出”）。

57. 发明授权

US08803269B2 Wafer scale packaging platform for transceivers 有权
标题翻译：收发器晶圆级封装平台
公开(公告)号：US08803269B2
公开(公告)日：2014-08-12
申请号：US13463408
申请日：2012-05-03
申请人： Kalpendu Shastri , Vipulkumar Patel , Mark Webster , Prakash Gothoskar , Ravinder Kachru , Soham Pathak , Rao V. Yelamarty , Thomas Daugherty , Bipin Dama , Kaushik Patel , Kishor Desai
发明人： Kalpendu Shastri , Vipulkumar Patel , Mark Webster , Prakash Gothoskar , Ravinder Kachru , Soham Pathak , Rao V. Yelamarty , Thomas Daugherty , Bipin Dama , Kaushik Patel , Kishor Desai
IPC分类号： H01L31/0232 , H01L29/40 , H01L23/053 , H01L23/12
CPC分类号： H01L25/50 , G02B6/423 , G02B6/4244 , G02B6/4245 , G02B6/4249 , G02B6/4257 , G02B6/426 , H01L25/167 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014
摘要： A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a “platform” (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules.
摘要翻译：光电子收发器组件过程的晶片级实现利用硅晶片作为光学参考平面和平台，同时为多个单独的收发器模块组装所有必需的光学和电子部件。特别地，硅晶片被用作“平台”（插入器），在其上安装或集成多个收发器模块的所有组件，硅插入器的顶表面用作参考平面，用于定义分离光学元件之间的光信号路径。实际上，通过使用单个硅晶片作为大量单独的收发器模块的平台，可以使用晶片尺度组装过程以及这些模块的光学对准和测试。

58. 发明申请

US20110221019A1 Silicon-Based Schottky Barrier Detector With Improved Responsivity 有权
标题翻译：具有改善响应性的硅基肖特基势垒检测器
公开(公告)号：US20110221019A1
公开(公告)日：2011-09-15
申请号：US13038470
申请日：2011-03-02
申请人： Vipulkumar Patel , Prakash Gothoskar , Mark Webster , Christopher J. Lang
发明人： Vipulkumar Patel , Prakash Gothoskar , Mark Webster , Christopher J. Lang
IPC分类号： H01L31/108
CPC分类号： H01L31/101 , H01L31/1085
摘要： A planar, waveguide-based silicon Schottky barrier photodetector includes a third terminal in the form of a field plate to improve the responsivity of the detector. Preferably, a silicide used for the detection region is formed during a processing step where other silicide contact regions are being formed. The field plate is preferably formed as part of the first or second layer of CMOS metallization and is controlled by an applied voltage to modify the electric field in the vicinity of the detector's silicide layer. By modifying the electric field, the responsivity of the device is “tuned” so as to adjust the momentum of “hot” carriers (electrons or holes, depending on the conductivity of the silicon) with respect to the Schottky barrier of the device. The applied potential functions to align with the direction of momentum of the “hot” carriers in the preferred direction “normal” to the silicon-silicide interface, allowing for an increased number to move over the Schottky barrier and add to the generated photocurrent.
摘要翻译：平面的基于波导的硅肖特基势垒光电检测器包括场板形式的第三端子，以提高检测器的响应度。优选地，在其中形成其它硅化物接触区域的处理步骤期间形成用于检测区域的硅化物。场板优选地形成为第一或第二CMOS金属化层的一部分，并且通过施加的电压来控制，以修改检测器硅化物层附近的电场。通过修改电场，器件的响应度被“调谐”，以相对于器件的肖特基势垒调节“热”载流子（电子或空穴，取决于硅的导电性）的动量。所施加的电位功能与“硅”载体的优势方向“正常”硅硅化物界面的动量方向相一致，允许增加的数量移动到肖特基势垒上并增加产生的光电流。

59. 发明申请

US20110127633A1 Slotted Configuration for Optimized Placement of Micro-Components using Adhesive Bonding 有权
标题翻译：用于使用粘合剂粘合优化微组件放置的开槽配置
公开(公告)号：US20110127633A1
公开(公告)日：2011-06-02
申请号：US12955011
申请日：2010-11-29
申请人： Mary Nadeau , Vipulkumar Patel , Prakash Gothoskar , John Fangman , John Matthew Fangman , Mark Webster
发明人： Mary Nadeau , Vipulkumar Patel , Prakash Gothoskar , John Fangman , John Matthew Fangman , Mark Webster
IPC分类号： H01L27/12 , B32B3/30 , H01L27/04
CPC分类号： G02B7/025 , G02B6/4228 , G02B6/4239 , G02B7/003 , H01L23/345 , H01L23/544 , H01L24/29 , H01L24/32 , H01L24/83 , H01L2223/54426 , H01L2224/26175 , H01L2224/2919 , H01L2224/32225 , H01L2224/83121 , H01L2224/83143 , H01L2224/83192 , H01L2224/83234 , H01L2224/83385 , H01L2224/83862 , H01L2924/14 , Y10T428/24479 , H01L2924/0665 , H01L2924/00014 , H01L2924/00
摘要： An arrangement for improving adhesive attachment of micro-components in an assembly utilizes a plurality of parallel-disposed slots formed in the top surface of the substrate used to support the micro-components. The slots are used to control the flow and “shape” of an adhesive “dot” so as to quickly and accurately attach a micro-component to the surface of a substrate. The slots are formed (preferably, etched) in the surface of the substrate in a manner that lends itself to reproducible accuracy from one substrate to another. Other slots (“channels”) may be formed in conjunction with the bonding slots so that extraneous adhesive material will flow into these channels and not spread into unwanted areas.
摘要翻译：用于改善组件中微组件的粘合附着的装置利用形成在用于支撑微组件的衬底顶表面中的多个平行布置的槽。这些槽用于控制粘合剂“点”的流动和“形状”，以便将微组件快速且精确地附着在基板的表面上。在衬底的表面中形成（优选地，蚀刻）狭槽，使其自身具有从一个衬底到另一个衬底的可再现精度。其它槽（“通道”）可以与结合槽结合形成，使得外来粘合剂材料将流入这些通道并且不会扩散到不需要的区域。

60. 发明授权

US07701985B2 SOI-based tunable laser 有权
标题翻译：基于SOI的可调谐激光器
公开(公告)号：US07701985B2
公开(公告)日：2010-04-20
申请号：US12291246
申请日：2008-11-06
申请人： Mark Webster , David Piede , Prakash Gothoskar
发明人： Mark Webster , David Piede , Prakash Gothoskar
IPC分类号： H01S3/10 , H01S3/13
CPC分类号： H01S5/141 , H01S5/021 , H01S5/02248 , H01S5/02268 , H01S5/06256
摘要： A silicon-on-insulator (SOI)-based tunable laser is formed to include the gain medium (such as a semiconductor optical amplifier) disposed within a cavity formed within the SOI substrate. A tunable wavelength reflecting element and associated phase matching element are formed on the surface of the SOI structure, with optical waveguides formed in the surface SOI layer providing the communication between these components. The tunable wavelength element is controlled to adjust the optical wavelength. Separate discrete lensing elements may be disposed in the cavity with the gain medium, providing efficient coupling of the optical signal into the SOI waveguides. Alternatively, the gain medium itself may be formed to include spot converting tapers on its endfaces, the tapers used to provide mode matching into the associated optical waveguides.
摘要翻译：形成绝缘体上硅（SOI）的可调谐激光器以包括设置在形成于SOI衬底内的空腔内的增益介质（例如半导体光放大器）。在SOI结构的表面上形成可调波长反射元件和相关的相位匹配元件，其中形成在表面SOI层中的光波导提供这些部件之间的连通。可调波长元件被控制以调节光学波长。单独的离散透镜元件可以用增益介质设置在空腔中，从而提供光信号到SOI波导的有效耦合。或者，增益介质本身可以被形成为包括其端面上的点变换锥度，用于向相关联的光波导提供模式匹配的锥度。

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