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51. 发明授权

US06645795B2 Polysilicon doped transistor using silicon-on-insulator and double silicon-on-insulator 失效
公开(公告)号：US06645795B2
公开(公告)日：2003-11-11
申请号：US09848467
申请日：2001-05-03
申请人： K. Paul Muller , Dominic J. Schepis , Ghavam G. Shahidi
发明人： K. Paul Muller , Dominic J. Schepis , Ghavam G. Shahidi
IPC分类号： H01L2100
CPC分类号： H01L29/66757 , H01L29/66772 , H01L29/78618 , H01L29/78621 , H01L29/78648 , H01L29/78654
摘要： Steep concentration gradients are achieved in semiconductor device of small sizes formed on SOI or double SOI wafers by using implanted polycrystalline material such as polysilicon as a solid diffusion source. Rapid diffusion of impurities along grain boundaries relative to diffusion rates in monocrystalline materials provides a substantially constant impurity concentration at the interface between polycrystalline material and monocrystalline material. Steepness of the impurity concentration gradient is thus effectively scaled as transistor size is decreased to counter increased short channel and other deleterious effects. In the case of SOI wafers greater uniformity of electrical characteristics are achieved using the high quality of semiconductor material made available therein consistent with the relatively thin active layer. In the case of double SOI, a ground plane is formed under the conduction channel which regulates the geometry of the electric field in the conduction channel with much the same functional improvements as is achieved in dual gate transistor designs.

52. 发明授权

US06602759B2 Shallow trench isolation for thin silicon/silicon-on-insulator substrates by utilizing polysilicon 有权
公开(公告)号：US06602759B2
公开(公告)日：2003-08-05
申请号：US09731620
申请日：2000-12-07
申请人： Atul C. Ajmera , Klaus D. Beyer , Dominic J. Schepis
发明人： Atul C. Ajmera , Klaus D. Beyer , Dominic J. Schepis
IPC分类号： H01L2176
CPC分类号： H01L21/76227
摘要： A method for forming an isolation trench in a silicon or silicon-on-insulator substrate is described in which a trench is formed in the semiconductor structure (containing a multiple layer structure of Si, SiO2, and SiN layers) and an undoped polysilicon layer is deposited on the bottom and sidewalls of the trench and on the surface of the region adjacent to the trench. A substantial portion of the trench is left unfilled by the undoped polysilicon layer deposited. The polysilicon layer is thermally oxidized to form a thermal oxide that fills the trench and thereby avoids forming a birds-beak formation of the thermal oxide above the sidewalls of the trench. The isolation structure may be planarized by either removing the polysilicon layer from the region adjacent to the trench before oxidation or later removing the oxide from the SiN layer and adjusting height of the oxide in the trench. Alternatively, either a doped polysilicon layer or a doped SiO2 layer may be formed above the silicon nitride layer before the undoped polysilicon layer is deposited. In this case, the isolation structure is heat treated prior to oxidization to drive dopants from the doped layer into the undoped polysilicon layer, thereby forming a secondarily doped polysilicon layer from the undoped polysilicon layer. The doped layers are then removed by selective wet etching and expose the silicon nitride layer prior to oxidation.

53. 发明授权

US06506649B2 Method for forming notch gate having self-aligned raised source/drain structure 有权
标题翻译：用于形成具有自对准凸起源极/漏极结构的陷波栅的方法
公开(公告)号：US06506649B2
公开(公告)日：2003-01-14
申请号：US09811706
申请日：2001-03-19
申请人： Ka Hing Fung , Atul C. Ajmera , Victor Ku , Dominic J. Schepis
发明人： Ka Hing Fung , Atul C. Ajmera , Victor Ku , Dominic J. Schepis
IPC分类号： H01L21336
CPC分类号： H01L29/66628 , H01L29/42376 , H01L29/665 , H01L29/7835
摘要： An innovative MOSFET having a raised source drain (RSD) is constructed prior to implanting source-drain dopants. The RSD structure thus built has a distinct advantage in that the offset from the RSD to the MOSFET channel is fully adjustable to minimize the overlap capacitance in the device. The RSD construction uses a selective epitaxial process to effectively reduce the drain-source resistance. This improvement is even more significant in thin-film SOI technology. Using an RSD, the film outside the channel area thickens which, in turn, reduces the parasitic resistance. The method of constructing such a structure includes the steps of: forming a notch gate on a top surface of a substrate; covering the notch gate and the top surface of the substrate with a conformal dielectric film; etching the dielectric film to expose an upper surface of the notch gate and selected exposed areas of the substrate; selectively growing silicon on the etched surface of the gate notch and on the etched surface of the substrate; implanting doping to form a drain-source area; forming spacers on the vertical walls of the notch gate; and forming a salicide on the notch gate and on the source and drain areas. The MOSFET device may be alternately be built without the formation of spacers.
摘要翻译：在植入源极 - 漏极掺杂剂之前，构建了具有升高的源极漏极（RSD）的创新型MOSFET。如此构建的RSD结构具有明显的优点，即从RSD到MOSFET通道的偏移是完全可调的，以最小化器件中的重叠电容。 RSD结构使用选择性外延工艺来有效降低漏极 - 源极电阻。这种改进在薄膜SOI技术中更为显着。使用RSD，通道区域外部的膜变厚，这又降低了寄生电阻。构造这种结构的方法包括以下步骤：在衬底的顶表面上形成陷波门; 用保形绝缘膜覆盖基板的切口栅和顶表面; 蚀刻电介质膜以暴露陷波栅的上表面和基板的选定的曝光区域; 选择性地在栅极刻蚀的蚀刻表面上和衬底的蚀刻表面上生长硅; 注入掺杂以形成漏 - 源区; 在凹口门的垂直壁上形成间隔物; 并在凹口门和源极和漏极区域上形成自对准硅化物。可以交替地构建MOSFET器件而不形成间隔物。

54. 发明授权

US06492684B2 Silicon-on-insulator chip having an isolation barrier for reliability 有权
公开(公告)号：US06492684B2
公开(公告)日：2002-12-10
申请号：US09878681
申请日：2001-06-11
申请人： Ronald J. Bolam , Subhash B. Kulkarni , Dominic J. Schepis
发明人： Ronald J. Bolam , Subhash B. Kulkarni , Dominic J. Schepis
IPC分类号： H01L2901
CPC分类号： H01L29/66772 , H01L21/743 , H01L21/76264 , H01L21/76283 , H01L27/1203 , H01L29/78636 , H01L29/78648
摘要： An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

55. 发明授权

US06429084B1 MOS transistors with raised sources and drains 失效
标题翻译： MOS晶体管具有升高的源极和漏极
公开(公告)号：US06429084B1
公开(公告)日：2002-08-06
申请号：US09885828
申请日：2001-06-20
申请人： Heemyong Park , Fariborz Assaderaghi , Dominic J. Schepis
发明人： Heemyong Park , Fariborz Assaderaghi , Dominic J. Schepis
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L29/41783 , H01L29/458 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/66772 , H01L29/78618 , H01L29/78621
摘要： In raised source/drain CMOS processing, the prior art problem of lateral epi growth on the gate stack interfering physically with the raised S/D structures and producing device characteristics that vary along the length of the gate and the problem of overetch of the STI oxide during the preclean step is solved by using a sacrificial nitride layer to block both the STI region and the gate stack, together with a process sequence in which the halo and extension implants are performed after the S/D implant anneal.
摘要翻译：在升高的源极/漏极CMOS处理中，现有技术的栅极堆叠上的外延生长问题在物理上与升高的S / D结构物质干扰并产生沿栅极长度变化的器件特性以及STI氧化物的过蚀刻问题在预清洗步骤期间，通过使用牺牲氮化物层来阻止STI区域和栅极堆叠，以及在S / D注入退火之后执行卤素和延伸注入的工艺顺序来解决。

56. 发明授权

US06281095B1 Process of manufacturing silicon-on-insulator chip having an isolation barrier for reliability 有权
标题翻译：制造具有隔离屏障的绝缘体上硅芯片的可靠性的工艺
公开(公告)号：US06281095B1
公开(公告)日：2001-08-28
申请号：US09148918
申请日：1998-09-04
申请人： Ronald J. Bolam , Subhash B. Kulkarni , Dominic J. Schepis
发明人： Ronald J. Bolam , Subhash B. Kulkarni , Dominic J. Schepis
IPC分类号： H01L21301
CPC分类号： H01L29/66772 , H01L21/743 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/78636 , H01L29/78648
摘要： An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.
摘要翻译：具有隔离屏障的SOI芯片。 SOI芯片包括衬底，沉积在衬底上的氧化物层和沉积在氧化物层上的硅层。栅极沉积在硅层上方。第一金属触点沉积在栅极上方以形成与栅极的电接触。沉积第二和第三金属触点以形成与硅层的电接触。隔离屏障延伸穿过硅层和氧化物层，并部分地延伸到衬底中，以阻挡隔离屏障之外的氧化物层中的杂质扩散到隔离屏障内部的氧化物层中。隔离屏障围绕栅极，第一金属触点，第二金属触点和第三金属触点，其限定隔离屏障内部的有源芯片区域。还公开了制造SOI芯片的方法。

57. 发明授权

US5811357A Process of etching an oxide layer 失效
标题翻译：蚀刻氧化层的工艺
公开(公告)号：US5811357A
公开(公告)日：1998-09-22
申请号：US824744
申请日：1997-03-26
申请人： Michael D. Armacost , Tina J. Wagner , Michael L. Passow , Dominic J. Schepis , Matthew J. Sendelbach , William C. Wille
发明人： Michael D. Armacost , Tina J. Wagner , Michael L. Passow , Dominic J. Schepis , Matthew J. Sendelbach , William C. Wille
IPC分类号： H01L21/311 , H01L21/302
CPC分类号： H01L21/02063 , H01L21/31116
摘要： A dry etching process for etching an oxide layer on a substrate in which a plasma is created in a gaseous mixture containing C.sub.4 F.sub.8 and C.sub.2 F.sub.6. The dry etch process is useful for etching an oxide layer stopping on a silicon nitride layer on a semiconductor wafer of an integrated circuit structure as it eliminates resist blistering without sacrificing high selectivity to nitride, via wall angle, and/or etch uniformity.
摘要翻译：用于蚀刻在其中在含有C 4 F 8和C 2 F 6的气体混合物中产生等离子体的衬底上的氧化物层的干蚀刻工艺。干蚀刻工艺对于蚀刻在集成电路结构的半导体晶片上的氮化硅层上停止的氧化物层是有用的，因为它消除了抗蚀剂起泡，而不牺牲对氮化物，经由壁角度和/或蚀刻均匀性的高选择性。

58. 发明授权

US5622892A Method of making a self cooling electrically programmable fuse 失效
标题翻译：制造自制电可编程保险丝的方法
公开(公告)号：US5622892A
公开(公告)日：1997-04-22
申请号：US407431
申请日：1995-03-17
申请人： Raschid J. Bezama , Dominic J. Schepis , Krishna Seshan
发明人： Raschid J. Bezama , Dominic J. Schepis , Krishna Seshan
IPC分类号： H01L21/82 , H01L23/367 , H01L23/525 , H01L21/306 , H01L21/326
CPC分类号： H01L23/5256 , H01L23/3672 , H01L2924/0002 , Y10S438/922
摘要： A method of fabricating an electrically programmable fuse buried under quartz and layers of polyimide with a specific structure to enhance its "thermal" capabilities. The fuse is designed to "blow" and cool off quickly so as not to cause damage to areas above and surrounding the fuse. A passivation layer is added above the fuse to act as a heat sink and absorb and redistribute the heat generated from one localized area to a broader and cooler area. The materials used for the fuse and the heat sink are selected to be compatible with both oxide and polyimide personalization schemes. Modeling of the fuse enables optimizing the characteristics of the fuse, particularly to transmit to the surface of the passivation layer the thermal wave created during programming of the fuse.
摘要翻译：埋设在石英下的电可编程熔丝的制造方法和具有特定结构的聚酰亚胺层以提高其“热”能力。保险丝设计为“吹”并快速冷却，以免对保险丝上方和周围的区域造成损坏。保险丝上方加上钝化层，作为散热片，吸收并重新分配从一个局部区域产生的热量到较宽和较冷的区域。用于保险丝和散热器的材料被选择为与氧化物和聚酰亚胺个性化方案兼容。保险丝的建模可以优化保险丝的特性，特别是在保险丝编程期间向钝化层的表面传输热波。

59. 发明授权

US5086016A Method of making semiconductor device contact including transition metal-compound dopant source 失效
标题翻译：制造包括过渡金属化合物掺杂剂源的半导体器件接触的方法
公开(公告)号：US5086016A
公开(公告)日：1992-02-04
申请号：US606632
申请日：1990-10-31
申请人： Stephen B. Brodsky , Rajiv V. Joshi , John S. Lechaton , James G. Ryan , Dominic J. Schepis
发明人： Stephen B. Brodsky , Rajiv V. Joshi , John S. Lechaton , James G. Ryan , Dominic J. Schepis
IPC分类号： H01L21/225 , H01L21/28 , H01L21/285 , H01L21/331 , H01L21/60
CPC分类号： H01L21/76897 , H01L21/2254 , H01L21/28568 , H01L29/66272 , Y10S148/034 , Y10S148/035
摘要： A contact is provided in a self-aligned manner to a doped region a semiconductor substrate by first forming a layer of a transition metal-boride compound over a selected region on the substrate. A layer of a transition metal-nitride compound is formed over the layer of transition metal-boride compound, and the structure is heated to drive dopant from the layer of transition metal-boride compound into the substrate. The transition metal-boride/transition metal nitride layers are patterned to leave a contact to the doped region.

60. 发明授权

US4758531A Method of making defect free silicon islands using SEG 失效
标题翻译：使用SEG制造无缺陷硅岛的方法
公开(公告)号：US4758531A
公开(公告)日：1988-07-19
申请号：US111888
申请日：1987-10-23
申请人： Klaus D. Beyer , Louis L. Hsu , Dominic J. Schepis , Victor J. Silvestri
发明人： Klaus D. Beyer , Louis L. Hsu , Dominic J. Schepis , Victor J. Silvestri
IPC分类号： H01L21/205 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76294 , Y10S148/026 , Y10S148/029 , Y10S148/097
摘要： A method for forming epitaxial grown silicon structure having substantially defect free outer surfaces and resulting structure is provided. A silicon substrate is provided, on which an epitaxial silicon crystal is grown. The outer surface layer of the silicon epitaxially grown silicon crystal will contain defective material which is removed by oxidation of the outer layer to silicon dioxide. This removes the defect containing outer layer, creating a new outer layer which is substantially defect free.

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