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51. 发明授权

US08995216B2 Semiconductor device with refresh control circuit 有权
标题翻译：具有刷新控制电路的半导体器件
公开(公告)号：US08995216B2
公开(公告)日：2015-03-31
申请号：US13531807
申请日：2012-06-25
申请人： Kiyohiro Furutani
发明人： Kiyohiro Furutani
IPC分类号： G11C7/00 , G11C8/06 , G11C8/08 , G11C8/18 , G11C11/406
CPC分类号： G11C11/406 , G11C8/06 , G11C8/08 , G11C8/18 , G11C11/40615 , G11C2211/4067
摘要： In a semiconductor device including a row-based control circuit applied with a current reduction circuit having a standby state and an active state, a refresh control circuit generates a refresh request signal every predetermined time interval on a self-refresh mode and time-sequentially generates an internal active signal at N times in connection with the refresh request signal once. The row-based control circuit time-sequentially refreshes information of memory cells on the based of the internal active signal at the N times. The refresh control circuit inactivates the row-based control circuit by making the current reduction circuit the standby state.
摘要翻译：在包括具有待机状态和活动状态的电流降低电路的基于行的控制电路的半导体器件中，刷新控制电路在自刷新模式下以预定的时间间隔生成刷新请求信号，并且时间顺序地产生与刷新请求信号一次的N次内部有效信号。基于行的控制电路基于N次内部有效信号时间顺序刷新存储单元的信息。刷新控制电路通过使电流还原电路处于待机状态来使基于行的控制电路失活。

52. 发明授权

US07940112B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07940112B2
公开(公告)日：2011-05-10
申请号：US12753582
申请日：2010-04-02
申请人： Shinya Okuno , Kiyohiro Furutani
发明人： Shinya Okuno , Kiyohiro Furutani
IPC分类号： H01L35/00 , H03K17/16 , G11C7/04
CPC分类号： G11C8/10 , G11C5/144 , G11C5/145
摘要： To include a first X decoder constituted by a transistor whose off-leakage current has a first temperature characteristic, a pre-decoder circuit and a peripheral circuit constituted by a transistor whose off-leakage current has a second temperature characteristic, a power supply control circuit that inactivates the X decoder when a temperature exceeds a first threshold during a standby state, and a power supply control circuit that inactivates the pre-decoder and the peripheral circuit when a temperature exceeds a second threshold during the standby state. According to the present invention, whether power supply control is performed on a plurality of circuit blocks is determined based on different temperatures, therefore optimum power supply control can be performed on each of circuit blocks.
摘要翻译：为了包括由漏电流具有第一温度特性的晶体管构成的第一X解码器，由解除漏电流具有第二温度特性的晶体管构成的预解码器电路和外围电路，电源控制电路当待机状态期间温度超过第一阈值时，使X解码器失活;以及电源控制电路，其在待机状态期间当温度超过第二阈值时使预解码器和外围电路失活。根据本发明，基于不同的温度来确定是否对多个电路块执行电源控制，因此可以对每个电路块执行最佳的电源控制。

53. 发明授权

US07365578B2 Semiconductor device with pump circuit 有权
标题翻译：带泵电路的半导体器件
公开(公告)号：US07365578B2
公开(公告)日：2008-04-29
申请号：US11822184
申请日：2007-07-03
申请人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
发明人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
IPC分类号： H03K3/00
CPC分类号： G11C16/30 , G11C5/145 , G11C16/04 , H02M3/073 , H02M2003/071 , H02M2003/075 , H02M2003/077 , H03K3/356113
摘要： In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of −9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.
摘要翻译：在本半导体器件中，正的驱动泵电路由外部电源电位EXVDD（例如1.8V）驱动以产生正电压VPC（例如2.4V）。用于内部操作的负泵电路由正电压VPC驱动以产生对于字线的擦除或类似的内部操作所需的负电压VNA（例如-9.2V）。用于内部操作的负泵电路可以具有较少数量的泵级，并且因此消耗比通过外部电源电压EXVDD（例如1.8V）驱动电路时更小的面积。

54. 发明授权

US07180362B2 Semiconductor device with pump circuit 有权
公开(公告)号：US07180362B2
公开(公告)日：2007-02-20
申请号：US10941004
申请日：2004-09-15
申请人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
发明人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
IPC分类号： G05F1/10
CPC分类号： G11C16/30 , G11C5/145 , G11C16/04 , H02M3/073 , H02M2003/071 , H02M2003/075 , H02M2003/077 , H03K3/356113
摘要： In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of −9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.

55. 发明授权

US07042769B2 Semiconductor memory device capable of accurate and stable operation 有权
标题翻译：半导体存储器件能够准确稳定运行
公开(公告)号：US07042769B2
公开(公告)日：2006-05-09
申请号：US10938615
申请日：2004-09-13
申请人： Tadaaki Yamauchi , Kiyohiro Furutani
发明人： Tadaaki Yamauchi , Kiyohiro Furutani
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/109 , G11C7/10 , G11C7/1078 , G11C7/1087 , G11C7/1093
摘要： An external clock generating circuit generates a mode indicating signal at the “H” level and generates an external clock signal synchronized with a write command buffer signal, when a semiconductor memory device is not in an internal operation mode. When the semiconductor memory device enters an internal operation mode and the mode indicating signal makes a transition from “H” to “L”, the external clock signal is fixed at the “L” level. The external clock signal is not supplied to an external CUI, and the external CUI is set in a state in which reception of any external command is prohibited. Until the end of asynchronous reset, the mode indicating signal is kept at the “L” level, and thereafter raised to the “H” level, so that malfunction caused by an input of an external command during asynchronous reset period can be avoided.
摘要翻译：当半导体存储器件不处于内部操作模式时，外部时钟产生电路产生“H”电平的模式指示信号并产生与写入命令缓冲器信号同步的外部时钟信号。当半导体存储器件进入内部操作模式并且模式指示信号从“H”转变为“L”时，外部时钟信号固定在“L”电平。外部时钟信号不提供给外部CUI，外部CUI被设置为禁止接收任何外部命令的状态。直到异步复位结束为止，模式指示信号保持在“L”电平，然后升至“H”电平，从而避免在异步复位期间由外部指令输入引起的故障。

56. 发明申请

US20050057288A1 Semiconductor device with pump circuit 有权
标题翻译：带泵电路的半导体器件
公开(公告)号：US20050057288A1
公开(公告)日：2005-03-17
申请号：US10941004
申请日：2004-09-15
申请人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
发明人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
IPC分类号： G11C16/06 , G11C5/14 , G11C16/04 , G11C16/30 , H01L21/822 , H01L21/8247 , H01L27/04 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , H02M3/07 , H03L7/06
CPC分类号： G11C16/30 , G11C5/145 , G11C16/04 , H02M3/073 , H02M2003/071 , H02M2003/075 , H02M2003/077 , H03K3/356113
摘要： In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of −9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.
摘要翻译：在本半导体器件中，正的驱动泵电路由外部电源电位EXVDD（例如1.8V）驱动以产生正电压VPC（例如2.4V）。用于内部操作的负泵电路由正电压VPC驱动以产生对于字线的擦除或类似的内部操作所需的负电压VNA（例如-9.2V）。用于内部操作的负泵电路可以具有较少数量的泵级，并且因此消耗比通过外部电源电压EXVDD（例如1.8V）驱动电路时更小的面积。

57. 发明授权

US06777920B2 Internal power-supply potential generating circuit 失效
标题翻译：内部电源电位发生电路
公开(公告)号：US06777920B2
公开(公告)日：2004-08-17
申请号：US10247337
申请日：2002-09-20
申请人： Kiyohiro Furutani , Takeshi Hamamoto , Susumu Tanida
发明人： Kiyohiro Furutani , Takeshi Hamamoto , Susumu Tanida
IPC分类号： G05F140
CPC分类号： G05F1/465
摘要： The internal power-supply potential generating circuit includes a reference potential generating circuit having small dependency on an external power-supply potential and on a temperature, an MOS transistor for pull up, a level shifter producing a potential lower than a reference potential by a prescribed voltage to a first node and producing a potential lower than an internal power-supply potential by a voltage of the sum of the prescribed potential and an offset potential to a second node, and a differential amplifier bringing an MOS transistor out of conduction in response to the potential of the second node reaching the potential of the first node. Thus, the reference potential may be set lower by the offset voltage, allowing stable reference potential and internal power-supply potential to be obtained even if the external power-supply potential is lowered.
摘要翻译：内部电源电位产生电路包括对外部电源电位和温度具有较小依赖性的参考电位产生电路，用于上拉的MOS晶体管，产生低于参考电位的电位的电平转换器电压到第一节点，并且通过对第二节点的预定电位和偏移电位之和的电压产生低于内部电源电位的电位;以及差分放大器，使得MOS晶体管响应于第二节点的潜力达到第一节点的潜力。因此，即使外部电源电位降低，也可以将偏置电压设定为较低的基准电位，能够获得稳定的基准电位和内部电源电位。

58. 发明授权

US06477105B2 Semiconductor memory device with a hierarchical word line configuration capable of preventing leakage current in a sub-word line driver 失效
标题翻译：具有能够防止子字线驱动器中的漏电流的分级字线配置的半导体存储器件
公开(公告)号：US06477105B2
公开(公告)日：2002-11-05
申请号：US10103698
申请日：2002-03-25
申请人： Kengo Aritomi , Mikio Asakura , Takashi Ito , Kiyohiro Furutani
发明人： Kengo Aritomi , Mikio Asakura , Takashi Ito , Kiyohiro Furutani
IPC分类号： G11C800
CPC分类号： G11C8/12 , G11C8/10 , G11C8/14
摘要： Complementary sub-decode signals to be provided to a sub-word line driver are separately generated through different circuits using individual power-supply voltages. Thus, the generation of a through current in the sub-word line driver is prevented.
摘要翻译：要提供给子字线驱动器的互补子解码信号通过使用各个电源电压的不同电路分别产生。因此，防止了在子字线驱动器中产生直通电流。

59. 发明授权

US06417715B2 Clock generation circuit generating internal clock of small variation in phase difference from external clock, and semiconductor memory device including such clock generation circuit 失效
标题翻译：时钟产生电路产生与外部时钟相位差小变化的内部时钟，以及包括这种时钟发生电路的半导体存储器件
公开(公告)号：US06417715B2
公开(公告)日：2002-07-09
申请号：US09793999
申请日：2001-02-28
申请人： Takeshi Hamamoto , Kiyohiro Furutani
发明人： Takeshi Hamamoto , Kiyohiro Furutani
IPC分类号： G06F104
CPC分类号： H03L7/0805 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/133 , H03K5/135 , H03L7/07 , H03L7/0814 , H03L7/087 , H03L7/089 , H03L7/091
摘要： A clock generation circuit includes a clock input circuit receiving complementary external clocks to generate an internal clock, a variable delay circuit delaying the internal clock to generate an internal operation clock, a replica circuit further delaying the internal operation clock by a predetermined time to generate a return clock, a phase comparator directly comparing the phase where potential levels of external clocks cross with the phase of the return clock, and a delay control circuit adjusting the delay amount of the variable delay circuit according to a phase comparison result of the phase comparator.
摘要翻译：时钟生成电路包括：时钟输入电路，接收互补的外部时钟以产生内部时钟;可变延迟电路，延迟内部时钟以产生内部操作时钟;复制电路进一步将内部操作时钟延迟预定时间，以产生返回时钟，直接比较外部时钟的电位电平与返回时钟的相位相交的相位比较器的相位比较器，以及根据相位比较器的相位比较结果来调整可变延迟电路的延迟量的延迟控制电路。

60. 发明授权

US06407942B2 Semiconductor memory device with a hierarchical word line configuration capable of preventing leakage current in a sub-word line driver 失效
公开(公告)号：US06407942B2
公开(公告)日：2002-06-18
申请号：US09566488
申请日：2000-05-08
申请人： Kengo Aritomi , Mikio Asakura , Takashi Ito , Kiyohiro Furutani
发明人： Kengo Aritomi , Mikio Asakura , Takashi Ito , Kiyohiro Furutani
IPC分类号： G11C506
CPC分类号： G11C8/12 , G11C8/10 , G11C8/14
摘要： Complementary sub-decode signals to be provided to a sub-word line driver are separately generated through different circuits using individual power-supply voltages. Thus, the generation of a through current in the sub-word line driver is prevented.

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