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51. 发明申请

US20050212018A1 Conductive lines buried in insulating areas 审中-公开
公开(公告)号：US20050212018A1
公开(公告)日：2005-09-29
申请号：US11135172
申请日：2005-05-23
申请人： Jean-Pierre Schoellkopf , Robin Cerutti , Philippe Coronel , Thomas Skotnicki
发明人： Jean-Pierre Schoellkopf , Robin Cerutti , Philippe Coronel , Thomas Skotnicki
IPC分类号： H01L21/74 , H01L21/762 , H01L21/765 , H01L21/768 , H01L21/8244 , H01L23/485 , H01L23/528 , H01L23/535 , H01L27/11 , H01L29/78 , H01L29/76
CPC分类号： H01L21/743 , H01L21/76224 , H01L21/765 , H01L21/76802 , H01L21/76838 , H01L21/76895 , H01L23/485 , H01L23/5286 , H01L23/535 , H01L27/11 , H01L27/1104 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit comprising a semiconductor substrate in which active areas surround or are surrounded by hollowings filled with an insulator, and in which a conductive region is embedded in the insulator of at least one hollowing, the conductive region being connected to a reference voltage and being connected at least one neighboring element of the circuit.

52. 发明申请

US20050085024A1 Method for producing a field-effect transistor and transistor thus obtained 有权
标题翻译：由此获得的场效应晶体管和晶体管的制造方法
公开(公告)号：US20050085024A1
公开(公告)日：2005-04-21
申请号：US10943242
申请日：2004-09-16
申请人： Thomas Skotnicki , Philippe Coronel , Joel Hartmann
发明人： Thomas Skotnicki , Philippe Coronel , Joel Hartmann
IPC分类号： H01L21/336 , H01L29/423 , H01L29/786 , H01L21/84
CPC分类号： H01L29/78696 , H01L29/42384 , H01L29/42392 , H01L29/66772 , H01L29/66787
摘要： A field effect transistor is produced on a substrate. A semiconductor material is deposited on a portion of a single crystal temporary material. At least part of the temporary material is removed. A portion of a conducting material is then formed above and beneath the portion of semiconductor material. A layer of an electrically insulating material is located between the portion of temporary material and the substrate.
摘要翻译：在衬底上产生场效晶体管。半导体材料沉积在单晶临时材料的一部分上。至少部分暂时的材料被去除。然后在半导体材料的部分的上方和下方形成导电材料的一部分。电绝缘材料层位于临时材料的部分和基底之间。

53. 发明授权

US06759721B2 Integrated semiconductor DRAM-type memory device and corresponding fabrication process 有权
标题翻译：集成半导体DRAM型存储器件及相应的制造工艺
公开(公告)号：US06759721B2
公开(公告)日：2004-07-06
申请号：US10174490
申请日：2002-06-18
申请人： Thomas Skotnicki , Alexandre Villaret
发明人： Thomas Skotnicki , Alexandre Villaret
IPC分类号： H01L2714
CPC分类号： H01L29/42336 , H01L29/788
摘要： An integrated memory location structure includes an isolated semiconductor layer between the source region and the drain region of a transistor, and between the channel region and the control gate of the transistor. The isolated semiconductor layer includes two potential well zones separated by a potential barrier zone under the control gate of the transistor. A write circuit biases the memory location structure to confine charge carriers selectively in one of the two potential well zones. A read circuit biases the memory location structure to measure the drain current of the transistor and determine therefrom the stored logic state imposed by the position of the charges in one of the potential well zones.
摘要翻译：集成存储器位置结构包括在晶体管的源极区域和漏极区域之间以及沟道区域和晶体管的控制栅极之间的隔离半导体层。隔离半导体层包括由晶体管的控制栅极下方的势垒区隔开的两个势阱区。写入电路偏置存储器位置结构以将电荷载流子选择性地限制在两个势阱区域中的一个中。读取电路偏置存储器位置结构以测量晶体管的漏极电流，并从其中确定由电荷在一个潜在阱区中施加的存储的逻辑状态。

54. 发明授权

US06537894B2 Process for fabricating a substrate of the silicon-on-insulator or silicon-on-nothing type and resulting device 有权
公开(公告)号：US06537894B2
公开(公告)日：2003-03-25
申请号：US09920315
申请日：2001-08-01
申请人： Thomas Skotnicki , Michel Haond , Didier Dutartre
发明人： Thomas Skotnicki , Michel Haond , Didier Dutartre
IPC分类号： H01L2176
CPC分类号： H01L21/76264 , H01L21/76283
摘要： Processes are provided for fabricating a substrate having a silicon-on-insulator (SOI) or silicon-on-nothing (SON) architecture, which are applicable to the manufacture of semiconductor devices, especially transistors such as those of the MOS, CMOS, BICMOS, and HCMOS types. In the fabrication processes, a multilayer stack is grown on a substrate by non-selective full-wafer epitaxy. The multilayer stack includes a silicon layer on a Ge or SiGe layer. Active regions are defined and masked, and insulating pads are formed so as to be located around the perimeter of each of the active regions at predetermined intervals and placed against the sidewalls of the active regions. The insulating trenches are etched, and the SiGe or Ge layer is laterally etched so as to form an empty tunnel under the silicon layer. The trenches are filled with a dielectric. In the case of an SOI archiutecture, the tunnel is filled with a dielectric.

55. 发明授权

US08878258B2 Detector of biological or chemical material and corresponding array of detectors 有权
标题翻译：生物或化学材料的检测器和相应的检测器阵列
公开(公告)号：US08878258B2
公开(公告)日：2014-11-04
申请号：US12914033
申请日：2010-10-28
申请人： Stéphane Monfray , Thomas Skotnicki
发明人： Stéphane Monfray , Thomas Skotnicki
IPC分类号： G01N27/403 , H01L21/00 , G01N33/543 , G01N27/414
CPC分类号： G01N27/414 , G01N27/4145 , G01N33/48707 , G01N33/54373 , G01N33/5438
摘要： A detector of biological or chemical material, including a MOS transistor having its channel region inserted between upper and lower insulated gates, the upper insulated gate including a detection layer capable of generating a charge at the interface of the upper insulated gate and of its gate insulator, the thickness of the upper gate insulator being smaller than the thickness of the lower gate insulator.
摘要翻译：一种生物或化学材料的检测器，包括其沟道区域插入在上下绝缘栅之间的MOS晶体管，上绝缘栅包括能够在上绝缘栅极及其栅极绝缘体的界面处产生电荷的检测层，上栅极绝缘体的厚度小于下栅极绝缘体的厚度。

56. 发明授权

US08586445B2 Method for manufacturing a suspended membrane and dual-gate MOS transistor 有权
公开(公告)号：US08586445B2
公开(公告)日：2013-11-19
申请号：US12949286
申请日：2010-11-18
申请人： Stéphane Monfray , Thomas Skotnicki
发明人： Stéphane Monfray , Thomas Skotnicki
IPC分类号： H01L29/786 , H01L21/762
CPC分类号： H01L29/786 , H01L29/78648
摘要： A method for manufacturing a suspended membrane in a single-crystal semiconductor substrate, including the steps of: forming in the substrate an insulating ring delimiting an active area, removing material from the active area, successively forming in the active area a first and a second layers, the second layer being a single-crystal semiconductor layer, etching a portion of the internal periphery of said ring down to a depth greater than the thickness of the second layer, removing the first layer so that the second layer formed a suspended membrane anchored in the insulating ring.

57. 发明授权

US08378558B2 Thermoelectric generator 有权
标题翻译：热电发电机
公开(公告)号：US08378558B2
公开(公告)日：2013-02-19
申请号：US12911287
申请日：2010-10-25
申请人： Thomas Skotnicki
发明人： Thomas Skotnicki
IPC分类号： H01L41/113 , H02N11/00
CPC分类号： H02N2/18
摘要： A thermoelectric generator including, between first and second walls delimiting a tightly closed space, a layer of a piezoelectric material connected to output terminals; a plurality of openings crossing the piezoelectric layer and emerging into first and second cavities close to the first and second walls; and in the tight space, drops of a liquid, the first wall being capable of being in contact with a hot source having a temperature greater than the evaporation temperature of the liquid and the second wall being capable of being in contact with a cold source having a temperature smaller than the evaporation temperature of the liquid.
摘要翻译：一种热电发生器，包括限定紧密封闭空间的第一和第二壁之间，连接到输出端的压电材料层; 多个开口与所述压电层交叉并且出现在靠近所述第一和第二壁的第一和第二空腔中; 并且在紧密的空间中，液滴，第一壁能够与温度大于液体的蒸发温度的热源接触，第二壁能够与具有温度小于液体的蒸发温度。

58. 发明授权

US08049224B2 Process for transferring a layer of strained semiconductor material 有权
标题翻译：用于转移应变半导体材料层的工艺
公开(公告)号：US08049224B2
公开(公告)日：2011-11-01
申请号：US12862471
申请日：2010-08-24
申请人： Bruno Ghyselen , Daniel Bensahel , Thomas Skotnicki
发明人： Bruno Ghyselen , Daniel Bensahel , Thomas Skotnicki
IPC分类号： H01L29/12
CPC分类号： H01L29/1054 , H01L21/76254 , H01L21/76259 , Y10S438/938
摘要： Semiconductor wafers having a thin layer of strained semiconductor material. These structures include a substrate; an oxide layer upon the substrate; a silicon carbide (SiC) layer upon the oxide layer, and a strained layer of a semiconductor material in a strained state upon the silicon carbide layer, or a matching layer upon the donor substrate that is made from a material that induces strain in subsequent epitaxially grown layers thereon; a strained layer of a semiconductor material of defined thickness in a strained state; and an insulating or semi-insulating layer upon the strained layer in a thickness that retains the strained state of the strained layer. The insulating or semi-insulating layers are made of silicon carbide or oxides and act to retain strain in the strained layer.
摘要翻译：半导体晶片具有应变半导体材料的薄层。这些结构包括底物; 基底上的氧化物层; 氧化物层上的碳化硅（SiC）层，以及在碳化硅层上处于应变状态的半导体材料的应变层，或者由施主衬底上的由随后的外延生长引起应变的材料制成的匹配层生长层; 在应变状态下具有规定厚度的半导体材料的应变层; 以及在应变层上的绝缘或半绝缘层，其厚度保持应变层的应变状态。绝缘层或半绝缘层由碳化硅或氧化物制成并用于将应变保留在应变层中。

59. 发明申请

US20110115237A1 THERMOELECTRIC GENERATOR 有权
标题翻译：热电发生器
公开(公告)号：US20110115237A1
公开(公告)日：2011-05-19
申请号：US12902355
申请日：2010-10-12
申请人： Thomas Skotnicki
发明人： Thomas Skotnicki
IPC分类号： H02K7/18
CPC分类号： F03G7/06 , H02N10/00 , Y02T10/166
摘要： A thermoelectric generator including a membrane maintained by lateral ends and capable of taking a first shape when its temperature reaches a first threshold and a second shape when its temperature reaches a second threshold greater than the first threshold; at least one electrically conductive element attached to with the membrane and connecting the lateral ends of the membrane; and circuitry capable of generating, at the level of the membrane, a magnetic field orthogonal to the membrane displacement direction, the lateral ends of the membrane being connected to output terminals of the generator.
摘要翻译：一种热电发电机，其包括由横向端部保持的膜，当其温度达到第一阈值时，当其温度达到大于第一阈值的第二阈值时能够获得第一形状; 至少一个导电元件与膜连接并连接膜的侧端; 以及能够在膜的水平处产生与膜移位方向正交的磁场的电路，膜的横向端部连接到发生器的输出端子。

60. 再颁专利

USRE41841E1 Method for making a silicon substrate comprising a buried thin silicon oxide film 有权
标题翻译：一种用于制造包含掩埋的薄氧化硅膜的硅衬底的方法
公开(公告)号：USRE41841E1
公开(公告)日：2010-10-19
申请号：US11208132
申请日：2000-06-08
申请人： Malgorzata Jurczak , Thomas Skotnicki
发明人： Malgorzata Jurczak , Thomas Skotnicki
IPC分类号： H01L21/30
CPC分类号： H01L21/76251
摘要： A method for making a silicon substrate having a buried thin silicon oxide film is described. The method consists of: a) producing a first element having a first silicon body whereof the main surface is coated, in succession, with a buffer layer of germanium, or of an alloy of germanium and silicon, and with a thin silicon film; b) producing a second element, having a silicon body whereof a main surface is coated with a thin silicon oxide film; c) linking the first element with the second element such that the thin silicon film of the first element is in contact with the thin silicon oxide film of the second element; and d) eliminating the buffer layer to recuperate the silicon substrate having a buried thin silicon oxide film and a reusable silicon substrate. The method may be useful in making microelectronic devices such as CMOS and MOSFET devices.
摘要翻译：描述了制造具有掩埋的薄氧化硅膜的硅衬底的方法。该方法包括：a）制备具有第一硅体的第一元件，该第一硅体的主表面依次用锗的缓冲层或锗和硅的合金以及薄的硅膜涂覆; b）制造具有硅主体的第二元件，主体表面涂覆有薄的氧化硅膜; c）将第一元件与第二元件连接，使得第一元件的薄硅膜与第二元件的薄氧化硅膜接触; 以及d）消除缓冲层以恢复具有掩埋的薄氧化硅膜和可重复使用的硅衬底的硅衬底。该方法可用于制造诸如CMOS和MOSFET器件的微电子器件。

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