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1. 发明授权

US5679970A Triple gate flash-type EEPROM memory and its production process 失效
标题翻译：三门闪存式EEPROM存储器及其生产过程
公开(公告)号：US5679970A
公开(公告)日：1997-10-21
申请号：US360685
申请日：1995-02-02
申请人： Joel Hartmann
发明人： Joel Hartmann
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/0416 , H01L27/115
摘要： A memory including a semiconductor substrate, an array of memory cells mutually electrically insulated by side insulators, wherein each memory cell includes a gate stack consisting of a gate insulator, a floating gate and a control gate separated by an electrical insulator between the gates, said gate insulator being arranged between the floating gate and the substrate, a source and a drain formed in the substrate on either side of said stack and outside the side insulators, an erasing gate located above the source in partial overlap with the stack, and electrically insulated from the source and said stack by a thin insulator, as well as conductive strips for applying electrical signals to the gate stacks, erasing gates, sources and drains.
摘要翻译： PCT No.PCT / FR93 / 00667 Sec。 371日期：1995年2月2日 102（e）日期1995年2月2日PCT提交1993年7月1日PCT公布。公开号WO94 / 01892 日期1994年1月20日包括半导体衬底，由侧绝缘体互相电绝缘的存储单元阵列的存储器，其中每个存储单元包括由栅极绝缘体，浮置栅极和由电绝缘体分隔开的控制栅极组成的栅极堆叠在所述栅极之间，所述栅极绝缘体布置在所述浮置栅极和所述衬底之间，源极和漏极形成在所述堆叠的任一侧上的所述衬底中以及在所述侧绝缘体的外部，位于所述源极之上的擦除栅极与所述栅极部分重叠，堆叠，并且通过薄绝缘体与源极和所述堆叠电绝缘，以及用于将电信号施加到栅极堆叠，擦除栅极，源极和漏极的导电条。

2. 发明授权

US4682403A Method for interconnecting the active zones and gates of CMOS integrated circuits 失效
标题翻译：用于互连CMOS集成电路的有源区和门的方法
公开(公告)号：US4682403A
公开(公告)日：1987-07-28
申请号：US715512
申请日：1985-03-25
申请人： Joel Hartmann , Pierre Jeuch
发明人： Joel Hartmann , Pierre Jeuch
IPC分类号： H01L21/768 , H01L21/8238 , H01L27/092 , H01L29/417 , H01L29/78 , H01L21/90 , H01L21/441 , H01L21/443 , H01L29/62
CPC分类号： H01L21/823871 , H01L21/76895 , H01L21/823878 , H01L2924/0002
摘要： A method for interconnecting the active zones and/or gates of CMOS integrated circuits. The method comprises, during the formation of the gates in a first conductive coating, defining in the latter the dimensions of the connections to be produced, and wherein following the formation of the active zones, the gates are laterally insulated and then a second conductive coating producing the desired connections is deposited on the complete circuit, with the exception of the lateral insulation.
摘要翻译：一种用于互连CMOS集成电路的有源区和/或门的方法。该方法包括在第一导电涂层中形成栅极期间，在其中限定待制造的连接的尺寸，并且其中在形成有源区之后，栅极被横向绝缘，然后是第二导电涂层产生所需的连接被沉积在完整的电路上，但侧绝缘除外。

3. 发明授权

US4672313A Device for checking mobile electrical charges in a MOS integrated circuit 失效
标题翻译：用于检查MOS集成电路中的移动电荷的装置
公开(公告)号：US4672313A
公开(公告)日：1987-06-09
申请号：US580840
申请日：1984-02-16
申请人： Joel Hartmann , Pierre Jeuch
发明人： Joel Hartmann , Pierre Jeuch
IPC分类号： H01L21/66 , G01R31/28 , H01L21/339 , H01L29/762 , G01R31/22 , G01R15/12 , G01R31/02
CPC分类号： G01R31/2831
摘要： A device for checking the mobile electrical charges in a MOS integrated circuit having a wafer support, a polarization means applying a potential difference between the two faces of the silicon wafer on which are formed the integrated circuits by means of two electrodes, one constituted by a conductive diaphragm covering the silicon wafer and which is kept in contact with the silicon wafer by a pressure difference between these two faces, while the other is constituted by the electrically conductive wafer support.
摘要翻译：一种用于检查具有晶片支架的MOS集成电路中的移动电荷的装置，通过两个电极在其上形成集成电路的硅晶片的两个面之间施加电位差的极化装置，所述导电膜覆盖所述硅晶片，并且通过所述两个面之间的压力差与所述硅晶片保持接触，而另一个由所述导电晶片支撑件构成。

4. 发明授权

US4636281A Process for the autopositioning of a local field oxide with respect to an insulating trench 失效
标题翻译：局部场氧化物相对于绝缘沟槽自动定位的方法
公开(公告)号：US4636281A
公开(公告)日：1987-01-13
申请号：US744339
申请日：1985-06-13
申请人： Francois Buiguez , Joel Hartmann
发明人： Francois Buiguez , Joel Hartmann
IPC分类号： H01L21/76 , H01L21/763 , H01L21/306 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/763 , Y10S148/05
摘要： Process for the autopositioning of a local field oxide relative to an insulating trench.This process consists of forming at least one first insulating coating on a silicon substrate, producing a second insulating coating on the first coating, anisotropically etching the first and second coating until the region of the substrate in which the trench is to be formed is exposed, forming insulating spacers on the etched flanks of the first and second coatings, anisotropically etching the substrate region in order to form the trench, the second etched coating and the spacers used as a mask for said etching, eliminating the mask, forming the insulating edges in the trench, filling said trench with a material and forming the field oxide.
摘要翻译：局部场氧化物相对于绝缘沟槽自动定位的方法。该方法包括在硅衬底上形成至少一个第一绝缘涂层，在第一涂层上产生第二绝缘涂层，各向异性地蚀刻第一和第二涂层，直到其中要形成沟槽的衬底的区域被暴露，在第一和第二涂层的蚀刻侧面上形成绝缘间隔物，各向异性地蚀刻衬底区域以形成沟槽，第二蚀刻涂层和间隔物用作所述蚀刻的掩模，消除掩模，形成绝缘边缘沟槽，用材料填充所述沟槽并形成场氧化物。

5. 发明授权

US5336628A Method for fabricating semiconductor memory device 失效
标题翻译：半导体存储器件的制造方法
公开(公告)号：US5336628A
公开(公告)日：1994-08-09
申请号：US47161
申请日：1993-04-13
申请人： Joel Hartmann
发明人： Joel Hartmann
IPC分类号： H01L23/485 , H01L23/528 , H01L27/115 , H01L21/28
CPC分类号： H01L27/115 , H01L23/485 , H01L23/528 , H01L2924/0002
摘要： An improved integrated circuit and fabrication method for forming the improved integrated circuit is described. The method includes an anisotropic etching, without the use of either masks or photolithography, which removes insulating material from contact openings, but keeps insulating material on the sides of conductive layers, preventing inadvertent short circuits from the contact openings to the conductive layers. The maskless etching method makes it possible to avoid mask-wafer alignment errors and therefore frees designers to perfectly center contact openings within insulative regions without taking into account the surface area tolerances required under prior art fabrication methods. This freedom allows designers to design more highly integrated devices. The particular embodiments of the semiconductor integrated circuit may include floating gates (47) and control gates (52) covered with an upper oxide layer (53) on which electrical connection lines (11) have been installed.
摘要翻译：描述了用于形成改进的集成电路的改进的集成电路和制造方法。该方法包括各向异性蚀刻，而不使用掩模或光刻法，其从接触开口去除绝缘材料，但是将绝缘材料保持在导电层的侧面，防止从接触开口到导电层的无意的短路。无掩模蚀刻方法使得可以避免掩模 - 晶片对准误差，并且因此使设计人员能够在绝缘区域内完美地中心接触开口，而不考虑现有技术制造方法所需的表面积公差。这种自由允许设计人员设计更高集成度的设备。半导体集成电路的特定实施例可以包括浮动栅极（47）和覆盖有已经安装有电连接线（11）的上氧化物层（53）的控制栅极（52）。

6. 发明授权

US5246882A Method for embodying an electric circuit on an active element of an MIS integrated circuit 失效
标题翻译：在MIS集成电路的活动元件上实现电路的方法
公开(公告)号：US5246882A
公开(公告)日：1993-09-21
申请号：US722120
申请日：1991-06-27
申请人： Joel Hartmann
发明人： Joel Hartmann
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L21/8234 , H01L23/485 , H01L23/52 , H01L23/522 , H01L27/088
CPC分类号： H01L23/485 , H01L21/76802 , H01L2924/0002
摘要： A method of making an electric contact of an MIS integrated circuit includes the following stages: depositing a thick film made of one first electric nonconductor on the integrated circuit provided with this element; depositing on the first nonconductor film a crash or barrier film made of a highly resistive material or a nonconductor able to be etched selectively with respect to the first nonconductor and a second electric nonconductor; forming opposite the active element a first opening in the barrier film and fixing the dimensions at the level of the active element of the electric contact to be embodied; depositing on the resulting structure obtained at least one second nonconducting film forming a second opening in the second nonconducting film, the second opening having a width larger than that the first opening; etching of the first nonconductor exposed during the previous step by using the etched barrier film as a mask, thus forming an electric contact hole of the active element, and metallizing of this contact hole.
摘要翻译：制造MIS集成电路的电接触的方法包括以下步骤：在设置有该元件的集成电路上沉积由一个第一非电导体制成的厚膜; 在第一非导体膜上沉积由相对于第一非导体和第二非导体选择性地蚀刻的高电阻材料或非导体制成的碰撞或阻挡膜; 与所述有源元件相反地形成所述阻挡膜中的第一开口并将所述尺寸固定在要体现的所述电接触件的有源元件的水平处; 沉积在所得到的结构上，获得在第二非导电膜中形成第二开口的至少一个第二非导电膜，第二开口的宽度大于第一开口的宽度; 通过使用蚀刻的阻挡膜作为掩模，在前一步骤中暴露的第一非导体的蚀刻，从而形成有源元件的电接触孔，并且该接触孔的金属化。

7. 发明授权

US4632725A Method for interconnecting the active zones and/or the gates of a C/MOS integrated circuit 失效
标题翻译：用于互连C / MOS集成电路的有源区和/或栅极的方法
公开(公告)号：US4632725A
公开(公告)日：1986-12-30
申请号：US712218
申请日：1985-03-15
申请人： Joel Hartmann , Pierre Jeuch
发明人： Joel Hartmann , Pierre Jeuch
IPC分类号： H01L21/8238 , H01L21/768 , H01L27/092 , H01L29/78 , C23F1/02 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/76885
摘要： A method for interconnecting the active zones and/or the gates of a C/MOS integrated circuit characterized in that, after producing the constituent elements of the integrated circuit with the exception of the connections, on the complete circuit is directly deposited a coating of a conductive material, which is then etched in order to form the desired connection.
摘要翻译：一种用于互连C / MOS集成电路的有源区和/或栅极的方法，其特征在于，除了连接之后，在产生集成电路的组成元件之后，在完整电路上直接沉积一层导电材料，然后将其蚀刻以形成所需的连接。

8. 发明授权

US5696718A Device having an electrically erasable non-volatile memory and process for producing such a device 失效
标题翻译：具有电可擦除非易失性存储器的装置和用于制造这种装置的方法
公开(公告)号：US5696718A
公开(公告)日：1997-12-09
申请号：US553877
申请日：1995-11-06
申请人： Joel Hartmann
发明人： Joel Hartmann
IPC分类号： H01L21/8247 , H01L27/115 , H01L27/12 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： H01L29/7881 , H01L27/115 , H01L29/7885
摘要： Device having an electrically erasable, non-volatile memory and its production process. In a storage area the device has at least one memory cell (12) of the floating grid type with a source (16) and a drain (18) separated by a channel region (14). According to the invention, the device also comprises means (44,38) for applying a memory cell erasing voltage to the channel region (14), independently of the memory cells of adjacent areas, as a result of a complete electrical isolation or insulation of each area. Application to the production of non-volatile memories which can be carried in satellites for replacing EPROM memories.
摘要翻译：具有电可擦除，非易失性存储器及其制造工艺的装置。在存储区域中，该装置具有至少一个浮动格栅型存储单元（12），源极（16）和漏极（18）由沟道区域（14）分开。根据本发明，该装置还包括用于将独立于相邻区域的存储单元的存储单元擦除电压施加到沟道区域（14）的装置（44,58），作为完全电隔离或绝缘的结果每个区域。适用于可在卫星中携带以替代EPROM存储器的非易失性存储器的生产。

9. 发明授权

US5256584A Method for producing a non-volatile memory cell using spacers 失效
标题翻译：用间隔物制造非易失性存储单元的方法
公开(公告)号：US5256584A
公开(公告)日：1993-10-26
申请号：US877082
申请日：1992-05-22
申请人： Joel Hartmann
发明人： Joel Hartmann
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/266
CPC分类号： H01L27/11521 , H01L27/115 , Y10S148/111
摘要： Method for producing a non-volatile memory cell and obtained memory cell. This method consists of embodying strips in a stacking of one nonconducting film and one conductive film, both films intended to respectively form the gate nonconductors (210) and the floating gates (208) of transistors, of forming spacers (230) on the flanks of the strips of said stacking, of eliminating the spacers on the side of the drains of the memory points to be embodied, of implanting ions of a type with conductivity differing from that of the substrate by using the remaining spacers and the strips of said stacking as a mask so as to form the sources and drains (214, 216) of the transistors, respectively offset and aligned with respect to said strips, of eliminating the remaining spacers, of forming a thin electric nonconducting film (208) on the sources and drains of the transistors, of embodying conductive strips (206a) perpendicular to the diffused source and drain zones, and of etching the strips of said stacking by using the conductive strips as a mask.
摘要翻译：用于制造非易失性存储单元和获得的存储单元的方法。该方法包括在一个非导电膜和一个导电膜的堆叠中实现条带，两个薄膜旨在分别形成晶体管的栅极非导体（210）和浮动栅极（208），以形成间隔物（230）的侧面通过使用剩余的间隔件和所述堆叠的条带将所述堆叠的条带去除待具体化的存储器点的漏极侧的间隔物，以注入不同于衬底的导电类型的离子类型掩模，以形成晶体管的源极和漏极（214,216），分别偏移并相对于所述条对准，以消除剩余的间隔物，在源极和漏极上形成薄的电绝缘膜（208）的晶体管，其包括垂直于扩散源极和漏极区的导电条（206a），并且通过使用导电条作为掩模蚀刻所述堆叠的条。

10. 发明申请

US20050085024A1 Method for producing a field-effect transistor and transistor thus obtained 有权
标题翻译：由此获得的场效应晶体管和晶体管的制造方法
公开(公告)号：US20050085024A1
公开(公告)日：2005-04-21
申请号：US10943242
申请日：2004-09-16
申请人： Thomas Skotnicki , Philippe Coronel , Joel Hartmann
发明人： Thomas Skotnicki , Philippe Coronel , Joel Hartmann
IPC分类号： H01L21/336 , H01L29/423 , H01L29/786 , H01L21/84
CPC分类号： H01L29/78696 , H01L29/42384 , H01L29/42392 , H01L29/66772 , H01L29/66787
摘要： A field effect transistor is produced on a substrate. A semiconductor material is deposited on a portion of a single crystal temporary material. At least part of the temporary material is removed. A portion of a conducting material is then formed above and beneath the portion of semiconductor material. A layer of an electrically insulating material is located between the portion of temporary material and the substrate.
摘要翻译：在衬底上产生场效晶体管。半导体材料沉积在单晶临时材料的一部分上。至少部分暂时的材料被去除。然后在半导体材料的部分的上方和下方形成导电材料的一部分。电绝缘材料层位于临时材料的部分和基底之间。

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