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51. 发明申请

US20050193362A1 Multi-layer overlay measurement and correction technique for IC manufacturing 失效
标题翻译：用于IC制造的多层覆盖测量和校正技术
公开(公告)号：US20050193362A1
公开(公告)日：2005-09-01
申请号：US10790296
申请日：2004-03-01
申请人： Khoi Phan , Bharath Rangarajan , Bhanwar Singh
发明人： Khoi Phan , Bharath Rangarajan , Bhanwar Singh
IPC分类号： G01N21/956 , G03F7/20 , H01L21/66 , H01L23/544 , G06F17/50
CPC分类号： G03F7/70633 , G01N21/95607 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A system facilitating measurement and correction of overlay between multiple layers of a wafer is disclosed. The system comprises an overlay target that represents overlay between three or more layers of a wafer and a measurement component that determines overlay error existent in the overlay target, thereby determining overlay error between the three or more layers of the wafer. A control component can be provided to correct overlay error between adjacent and non-adjacent layers, wherein the correction is based at least in part on measurements obtained by the measurement component.
摘要翻译：公开了一种便于测量和校正晶片多层之间覆盖层的系统。该系统包括覆盖在三层或多层晶片之间的重叠目标，以及确定覆盖目标中存在的重叠误差的测量部件，从而确定晶片的三层或更多层之间的重叠误差。可以提供控制部件来校正相邻层和非相邻层之间的覆盖误差，其中校正至少部分地基于由测量部件获得的测量。

52. 发明授权

US06879406B1 Use of scatterometry as a control tool in the manufacture of extreme UV masks 失效
标题翻译：使用散射测量作为制造极端紫外线掩模的控制工具
公开(公告)号：US06879406B1
公开(公告)日：2005-04-12
申请号：US10677041
申请日：2003-10-01
申请人： Bharath Rangarajan , Ramkumar Subramanian , Bhanwar Singh
发明人： Bharath Rangarajan , Ramkumar Subramanian , Bhanwar Singh
IPC分类号： G01B11/24 , G03F1/00 , G03F1/14
CPC分类号： B82Y10/00 , B82Y40/00 , G03F1/24 , G03F1/84
摘要： One aspect of the present invention relates to a system and method for controlling an EUV mask fabrication process using a scatterometer. The system includes an EUV mask fabrication system comprising a translucent substrate having one or more layers of reflective material formed thereon and a patterned photoresist layer as the uppermost layer, a mask inspection system operatively connected to the mask fabrication system for examining the layers as they are being etched and developed by the mask fabrication system and generating data related thereto, and an EUV mask fabrication control system coupled to the mask inspection system for receiving data from the inspection system in order to regulate the mask fabrication system to facilitate obtaining desired critical dimensions. The method involves monitoring the etching of the features, generating data related to the features, and relaying the data to a control system to optimize the EUV mask fabrication process.
摘要翻译：本发明的一个方面涉及使用散射仪控制EUV掩模制造工艺的系统和方法。该系统包括EUV掩模制造系统，该系统包括其上形成有一层或多层反射材料的半透明基材和作为最上层的图案化光致抗蚀剂层，与该掩模制造系统可操作地连接的掩模检查系统，以便像它们一样检查这些层由掩模制造系统蚀刻和显影并产生与之相关的数据，以及耦合到掩模检查系统的EUV掩模制造控制系统，用于从检查系统接收数据，以便调节掩模制造系统以便于获得期望的临界尺寸。该方法包括监测特征的蚀刻，产生与特征有关的数据，以及将数据中继到控制系统以优化EUV掩模制造工艺。

53. 发明授权

US06844206B1 Refractive index system monitor and control for immersion lithography 失效
$Refractive index system monitor and control for immersion lithography$
标题翻译：折射率系统监测和控制浸没光刻
公开(公告)号：US06844206B1
公开(公告)日：2005-01-18
申请号：US10645363
申请日：2003-08-21
申请人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
发明人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： G03F7/20 , H01L21/00 , G03C5/00
CPC分类号： G03F7/70341
摘要： A system and/or method are disclosed for measuring and/or controlling refractive index (n) and/or lithographic constant (k) of an immersion medium utilized in connection with immersion lithography. A known grating structure is built upon a substrate. A refractive index monitoring component facilitates measuring and/or controlling the immersion medium by utilizing detected light scattered from the known grating structure.
摘要翻译：公开了用于测量和/或控制与浸没式光刻相关联的浸渍介质的折射率（n）和/或光刻常数（k）的系统和/或方法。已知的光栅结构被构建在衬底上。折射率监测部件通过利用从已知光栅结构散射的检测光，便于测量和/或控制浸没介质。

54. 发明授权

US06813574B1 Topographically aligned layers and method for adjusting the relative alignment of layers and apparatus therefor 有权
标题翻译：用于调整层的相对对准的方法和用于其的设备的方法
公开(公告)号：US06813574B1
公开(公告)日：2004-11-02
申请号：US09992599
申请日：2001-11-06
申请人： Sanjay K. Yedur , Bhanwar Singh , Bharath Rangarajan , Ramkumar Subramanian
发明人： Sanjay K. Yedur , Bhanwar Singh , Bharath Rangarajan , Ramkumar Subramanian
IPC分类号： G01N2186
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： Patterned layers in an integrated circuit (IC) or other device are aligned in conjunction with the detection of the topology of the layers. The topology can be used to determine the location of a metrology mark and/or to compensate for a horizontal shift in the apparent location of the metrology mark. Precise detection of topography can be achieved without physical contact with the IC or other device with an atomic force microscope.
摘要翻译：集成电路（IC）或其他设备中的图案层与层的拓扑结构的检测结合对齐。拓扑结构可用于确定计量标记的位置和/或补偿计量标记的表观位置的水平位移。无需使用原子力显微镜与IC或其他器件物理接触即可实现精确的形貌检测。

55. 发明授权

US06808591B1 Model based metal overetch control 有权
标题翻译：基于型号的金属防腐控制
公开(公告)号：US06808591B1
公开(公告)日：2004-10-26
申请号：US10021531
申请日：2001-12-12
申请人： Khoi A. Phan , Bharath Rangarajan , Christopher F. Lyons , Steven C. Avanzino , Ramkumar Subramanian , Bhanwar Singh , Cyrus E. Tabery
发明人： Khoi A. Phan , Bharath Rangarajan , Christopher F. Lyons , Steven C. Avanzino , Ramkumar Subramanian , Bhanwar Singh , Cyrus E. Tabery
IPC分类号： H01L21302
CPC分类号： H01L21/67253 , H01L21/32136
摘要： A systems and methodologies are provided for metal overetch control. Metal overetch processes are controlled by utilizing overetch device models to determine overetch times or overetch endpoints. The systems and methodologies reduce the need for manual testing and manual overetch characterization. An overetch system includes a metal etcher, a target device and an overetch controller. The target device is located in or on the metal etcher. The overetch controller is coupled to the metal etcher. The overetch controller controls overetching of the target device by the metal etcher. The overetch controller includes an overetch time controller, a set of etch control models and a control system.
摘要翻译：提供了用于金属过程控制的系统和方法。通过利用过滤设备模型来确定金属过蚀刻过程以确定过蚀刻时间或过程延伸端点。系统和方法减少了手动测试和手动过程表征的需要。一种过蚀系统包括金属蚀刻机，目标装置和过程控制器。目标设备位于金属蚀刻机中或其上。该过程控制器耦合到金属蚀刻器。过程控制器通过金属蚀刻器控制目标器件的过蚀刻。该过程控制器包括一个过时延时间控制器，一组蚀刻控制模型和一个控制系统。

56. 发明授权

US06758612B1 System and method for developer endpoint detection by reflectometry or scatterometry 有权
标题翻译：用于通过反射测量或散点测量进行开发人员端点检测的系统和方法
公开(公告)号：US06758612B1
公开(公告)日：2004-07-06
申请号：US10050471
申请日：2002-01-16
申请人： Cyrus E. Tabery , Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
发明人： Cyrus E. Tabery , Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： G03D500
CPC分类号： G03F7/3028
摘要： A system for regulating (e.g., terminating) a development process is provided. The system includes one or more light sources, each light source directing light to one or more patterns and/or gratings on a wafer. Light reflected from the patterns and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the dimensions achieved at respective portions of the wafer. The measuring system provides development related data to a processor that determines the acceptability of the development of the respective portions of the wafer. The collected light may be analyzed by scatterometry and/or reflectometry systems to produce development related data and the development related data may be examined to determine whether a development process end point has been reached, at which time the system can control the development process and terminate development.
摘要翻译：提供了一种用于调节（例如，终止）显影过程的系统。该系统包括一个或多个光源，每个光源将光引导到晶片上的一个或多个图案和/或光栅。从图案和/或光栅反射的光被测量系统收集，该系统处理所收集的光。所收集的光指示在晶片的相应部分处获得的尺寸。该测量系统将开发相关数据提供给处理器，该处理器确定晶片各个部分的可接受性。所收集的光可以通过散射法和/或反射测量系统进行分析以产生开发相关数据，并且可以检查开发相关数据以确定是否已经达到开发过程终点，此时系统可以控制开发过程并终止发展。

57. 发明授权

US06641963B1 System and method for in situ control of post exposure bake time and temperature 失效
标题翻译：曝晒后烘烤时间和温度的现场控制系统和方法
公开(公告)号：US06641963B1
公开(公告)日：2003-11-04
申请号：US09845239
申请日：2001-04-30
申请人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh , Ramkumar Subramanian
发明人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： G03F900
CPC分类号： G03F7/38 , G03B27/52
摘要： A system for regulating temperature of a post exposure baking process is provided. The system includes one or more light sources, each light source directing light to one or more gratings being baked and hardened on a wafer. Light reflected from the gratings is collected by a measuring system, which processes the collected light. Light passing through the gratings may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the baking and hardening of the respective portions of the wafer. The measuring system provides baking and hardening related data to a processor that determines the baking and hardening of the respective portions of the wafer. The system also includes a plurality of temperature controlling devices, each such device corresponds to a respective portion of the wafer and provides for the heating and/or cooling thereof. The processor selectively controls the temperature controlling devices so as to regulate temperature of the respective portions of the wafer.
摘要翻译：提供了一种用于调节后曝光烘烤处理温度的系统。该系统包括一个或多个光源，每个光源将光引导到在晶片上被烘烤和硬化的一个或多个光栅。从光栅反射的光被测量系统收集，该系统处理收集的光。通过光栅的光可以类似地由处理所收集的光的测量系统收集。所收集的光表示晶片的各个部分的烘烤和硬化。测量系统向处理器提供烘烤和硬化相关数据，该处理器确定晶片的相应部分的烘烤和硬化。该系统还包括多个温度控制装置，每个这样的装置对应于晶片的相应部分并提供其加热和/或冷却。处理器选择性地控制温度控制装置，以调节晶片各部分的温度。

58. 发明授权

US06630361B1 Use of scatterometry for in-situ control of gaseous phase chemical trim process 有权
标题翻译：使用散射法进行气相化学修饰过程的原位控制
公开(公告)号：US06630361B1
公开(公告)日：2003-10-07
申请号：US09894701
申请日：2001-06-28
申请人： Bhanwar Singh , Bharath Rangarajan , Michael K. Templeton , Ramkumar Subramanian , Cristina Cheung
发明人： Bhanwar Singh , Bharath Rangarajan , Michael K. Templeton , Ramkumar Subramanian , Cristina Cheung
IPC分类号： H01L2100
CPC分类号： H01L22/20 , G01N21/47 , G01N21/9501 , G01N21/956 , H01L21/67253
摘要： A system for regulating a gaseous phase chemical trim process is provided. The system includes one or more light sources, each light source directing light to one or more features and/or gratings on a wafer. Light reflected from the features and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the dimensions achieved at respective portions of the wafer. The measuring system provides trimming related data to a processor that determines the acceptability of the trimming of the respective portions of the wafer. The system also includes one or more trimming devices, each such device corresponding to a portion of the wafer and providing for the trimming thereof. The processor selectively controls the trimming devices to regulate trimming of the portions of the wafer.
摘要翻译：提供了一种用于调节气相化学修饰过程的系统。该系统包括一个或多个光源，每个光源将光引导到晶片上的一个或多个特征和/或光栅。从特征和/或光栅反射的光由测量系统收集，该系统处理收集的光。所收集的光指示在晶片的相应部分处获得的尺寸。测量系统向处理器提供修剪相关数据，该处理器确定了晶片各部分的修整的可接受性。该系统还包括一个或多个修整装置，每个这样的装置对应于晶片的一部分并提供其修剪。处理器选择性地控制修整装置来调节对晶片的部分的修整。

59. 发明授权

US06605855B1 CVD plasma process to fill contact hole in damascene process 有权
标题翻译： CVD等离子体工艺在镶嵌工艺中填充接触孔
公开(公告)号：US06605855B1
公开(公告)日：2003-08-12
申请号：US09650538
申请日：2000-08-30
申请人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Christopher F. Lyons , Sanjay K. Yedur , Ramkumar Subramanian
发明人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Christopher F. Lyons , Sanjay K. Yedur , Ramkumar Subramanian
IPC分类号： H01L2900
CPC分类号： H01L21/76808 , H01L21/31144 , H01L21/312 , H01L21/76831 , H01L2221/1063
摘要： The present invention relates to a method for fabricating interconnecting lines and vias in a layer of insulating material. A via is formed in the layer of insulating material. A protective material is formed so as to be conformal to at least edges and sidewalls of the via, the protective material facilitating shielding of at least the edges and sidewalls of the via from a trench etch step. The trench etch step is performed to form a trench opening in the insulating material. The via and trench are filled with a conductive metal.
摘要翻译：本发明涉及在绝缘材料层中制造互连线和通孔的方法。在绝缘材料层中形成通孔。形成保护材料以至少与通孔的边缘和侧壁共形，所述保护材料有助于屏蔽通孔的至少边缘和侧壁至沟槽蚀刻步骤。执行沟槽蚀刻步骤以在绝缘材料中形成沟槽开口。通孔和沟槽填充有导电金属。

60. 发明授权

US06602727B1 Scatterometry based active control of exposure conditions 有权
标题翻译：基于散射法的有效控制曝光条件
公开(公告)号：US06602727B1
公开(公告)日：2003-08-05
申请号：US10133874
申请日：2002-04-26
申请人： Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
发明人： Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： H01L2166
CPC分类号： H01L22/20
摘要： A system for regulating an exposure condition determining process is provided. The system includes one or more light sources, each light source directing light to one or more gratings exposed on one or more portions of a wafer. Light reflected from the gratings is collected by a measuring system, which processes the collected light. Light passing through the gratings may similarly be collected by the measuring system, which processes the collected light. The collected light is analyzed to determine whether exposure conditions should be adapted prior to exposing a pattern on the wafer. The measuring system provides grating signature data to a processor that determines the acceptability of the exposure condition by comparing determined signatures to desired signatures. The system also includes an exposing system that can be controlled to change exposure conditions. The processor selectively controls the exposing system, via the exposer driving system, to adapt such exposure conditions.
摘要翻译：提供一种用于调节曝光条件确定过程的系统。该系统包括一个或多个光源，每个光源将光引导到暴露在晶片的一个或多个部分上的一个或多个光栅。从光栅反射的光被测量系统收集，该系统处理收集的光。通过光栅的光可以类似地由处理所收集的光的测量系统收集。分析收集的光以确定在将图案暴露在晶片之前是否应适应曝光条件。测量系统向处理器提供光栅签名数据，该处理器通过将确定的签名与期望的签名进行比较来确定曝光条件的可接受性。该系统还包括可被控制以改变曝光条件的曝光系统。处理器通过曝光器驱动系统选择性地控制曝光系统，以适应这种曝光条件。

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