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51. 发明授权

US07890907B2 Computer program product for designing memory circuits having single-ended memory cells with improved read stability 有权
标题翻译：用于设计具有改善的读稳定性的单端存储单元的存储器电路的计算机程序产品
公开(公告)号：US07890907B2
公开(公告)日：2011-02-15
申请号：US12174707
申请日：2008-07-17
申请人： Keunwoo Kim , Rajiv V. Joshi , Vinod Ramadurai
发明人： Keunwoo Kim , Rajiv V. Joshi , Vinod Ramadurai
IPC分类号： G06F17/50
CPC分类号： G11C11/412 , G11C11/413
摘要： A memory cell for interconnection with READ and WRITE word lines and READ and WRITE bit lines includes a logical storage element such as a flip-flop formed by a first inverter and a second inverter cross-coupled to the first inverter. The storage element has first and second terminals and a storage element supply voltage terminal configured for interconnection with a first supply voltage. A WRITE access device is configured to selectively interconnect the first terminal to the WRITE bit line under control of the WRITE word line, and a pair of series READ access devices are configured to ground the READ bit line when the READ word line is active and the second terminal is at a high logical level. A logical “one” can be written to the storage element when a second supply voltage, greater than the first supply voltage, is applied to the WRITE word line, substantially without the use of a complementary WRITE bit line.
摘要翻译：用于与READ和WRITE字线以及READ和WRITE位线互连的存储单元包括逻辑存储元件，例如由第一反相器形成的触发器和与第一反相器交叉耦合的第二反相器。存储元件具有第一和第二端子以及被配置为与第一电源电压互连的存储元件电源电压端子。 WRITE访问设备被配置为在WRITE字线的控制下选择性地将第一终端与WRITE位线互连，并且一对串行READ访问设备被配置为当READ字线活动时将READ位线接地，并且第二终端处于高逻辑级。当将大于第一电源电压的第二电源电压施加到写字线时，基本上不使用互补的写位线，可以将逻辑“1”写入存储元件。

52. 发明授权

US07420836B1 Single-ended memory cell with improved read stability and memory using the cell 有权
标题翻译：单端存储单元，具有改善的读取稳定性和使用单元格的存储器
公开(公告)号：US07420836B1
公开(公告)日：2008-09-02
申请号：US11674292
申请日：2007-02-13
申请人： Keunwoo Kim , Rajiv V. Joshi , Vinod Ramadurai
发明人： Keunwoo Kim , Rajiv V. Joshi , Vinod Ramadurai
IPC分类号： G11C11/40
CPC分类号： G11C11/412 , G11C11/413
摘要： A memory cell for interconnection with READ and WRITE word lines and READ and WRITE bit lines includes a logical storage element such as a flip-flop formed by a first inverter and a second inverter cross-coupled to the first inverter. The storage element has first and second terminals and a storage element supply voltage terminal configured for interconnection with a first supply voltage. A WRITE access device is configured to selectively interconnect the first terminal to the WRITE bit line under control of the WRITE word line, and a pair of series READ access devices are configured to ground the READ bit line when the READ word line is active and the second terminal is at a high logical level. A logical “one” can be written to the storage element when a second supply voltage, greater than the first supply voltage, is applied to the WRITE word line, substantially without the use of a complementary WRITE bit line.
摘要翻译：用于与READ和WRITE字线以及READ和WRITE位线互连的存储单元包括逻辑存储元件，例如由第一反相器形成的触发器和与第一反相器交叉耦合的第二反相器。存储元件具有第一和第二端子以及被配置为与第一电源电压互连的存储元件电源电压端子。 WRITE访问设备被配置为在WRITE字线的控制下选择性地将第一终端与WRITE位线互连，并且一对串行READ访问设备被配置为当READ字线活动时将READ位线接地，并且第二终端处于高逻辑级。当将大于第一电源电压的第二电源电压施加到写字线时，基本上不使用互补的写位线，可以将逻辑“1”写入存储元件。

53. 发明授权

US07733689B2 Methods of operating and designing memory circuits having single-ended memory cells with improved read stability 失效
标题翻译：具有改善的读稳定性的具有单端存储单元的存储电路的操作和设计方法
公开(公告)号：US07733689B2
公开(公告)日：2010-06-08
申请号：US12174688
申请日：2008-07-17
申请人： Keunwoo Kim , Rajiv V. Joshi , Vinod Ramadurai
发明人： Keunwoo Kim , Rajiv V. Joshi , Vinod Ramadurai
IPC分类号： G11C11/40
CPC分类号： G11C11/412 , G11C11/413
摘要： A memory cell for interconnection with READ and WRITE word lines and READ and WRITE bit lines includes a logical storage element such as a flip-flop formed by a first inverter and a second inverter cross-coupled to the first inverter. The storage element has first and second terminals and a storage element supply voltage terminal configured for interconnection with a first supply voltage. A WRITE access device is configured to selectively interconnect the first terminal to the WRITE bit line under control of the WRITE word line, and a pair of series READ access devices are configured to ground the READ bit line when the READ word line is active and the second terminal is at a high logical level. A logical “one” can be written to the storage element when a second supply voltage, greater than the first supply voltage, is applied to the WRITE word line, substantially without the use of a complementary WRITE bit line.
摘要翻译：用于与READ和WRITE字线以及READ和WRITE位线互连的存储单元包括逻辑存储元件，例如由第一反相器形成的触发器和与第一反相器交叉耦合的第二反相器。存储元件具有第一和第二端子以及被配置为与第一电源电压互连的存储元件电源电压端子。 WRITE访问设备被配置为在WRITE字线的控制下选择性地将第一终端与WRITE位线互连，并且一对串行READ访问设备被配置为当READ字线活动时将READ位线接地，并且第二终端处于高逻辑级。当将大于第一电源电压的第二电源电压施加到写字线时，基本上不使用互补的写位线，可以将逻辑“1”写入存储元件。

54. 发明授权

US08767501B2 Self-reconfigurable address decoder for associative index extended caches 有权
标题翻译：用于关联索引扩展缓存的自重配置地址解码器
公开(公告)号：US08767501B2
公开(公告)日：2014-07-01
申请号：US13550762
申请日：2012-07-17
申请人： Rajiv V. Joshi , Ajay N. Bhoj
发明人： Rajiv V. Joshi , Ajay N. Bhoj
IPC分类号： G11C8/10
CPC分类号： G06F12/0864 , G06F2212/1021 , G11C15/04
摘要： Associative index extended (AIX) caches can be functionally implemented through a reconfigurable decoder that employs programmable line decoding. The reconfigurable decoder features scalability in the number of lines, the number of index extension bits, and the number of banks. The reconfigurable decoder can switch between pure direct mapped (DM) mode and direct mapped-associative index extended (DM-AIX) mode of operation. For banked configurations, the reconfigurable decoder provides the ability to run some banks in DM mode and some other banks in DM-AIX mode. A cache employing this reconfigurable decoder can provide a comparable level of latency as a DM cache with minimal modifications to a DM cache circuitry of an additional logic circuit on a critical signal path, while providing low power operation at low area overhead with SA cache-like miss rates. Address masking and most-recently-used-save replacement policy can be employed with a single bit overhead per line.
摘要翻译：关联索引扩展（AIX）缓存可以通过采用可编程线解码的可重构解码器进行功能实现。可重配置解码器具有线路数量的可扩展性，索引扩展位的数量和存储体的数量。可重构解码器可以在纯直接映射（DM）模式和直接映射关联索引扩展（DM-AIX）操作模式之间切换。对于组合配置，可重构解码器能够以DM模式运行某些存储区，并以DM-AIX模式运行其他存储区。采用该可重构解码器的高速缓存器可以提供与DM高速缓存相当的延迟水平，对关键信号路径上的附加逻辑电路的DM高速缓存电路进行最小修改，同时在低区域开销提供具有SA缓存类似的低功率操作错过率。地址掩码和最近使用的保存替换策略可以采用每行一个位开销。

55. 发明授权

US08578316B1 Methodologies for automatic 3-D device structure synthesis from circuit layouts for device simulation 有权
公开(公告)号：US08578316B1
公开(公告)日：2013-11-05
申请号：US13607678
申请日：2012-09-08
申请人： Rajiv V. Joshi , Ajay N. Bhoj
发明人： Rajiv V. Joshi , Ajay N. Bhoj
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5018
摘要： A method of automatically generating structure files employing a full structure generator automated program is provided. An annotated device layout file is generated from a design layout by annotating the codes for design shapes with additional text representing the functionality of a physical structure associated with each design shape. Functioning individual semiconductor devices are identified from the annotated device layout file, and a circuit area including multiple interconnected semiconductor devices are identified. A front-end-of-line (FEOL) device structure file and a back-end-of-line (BEOL) device structure file are generated from layer by layer analysis of the components of the annotated device layout within the circuit area. Finite element meshes (FEMs) are generated for the FEOL and BEOL structure files and merged to provide a structure file that can be employed for simulation of semiconductor devices therein.

56. 发明申请

US20130042217A1 STRUCTURAL MIGRATION OF INTEGRATED CIRCUIT LAYOUT 失效
标题翻译：集成电路布局的结构迁移
公开(公告)号：US20130042217A1
公开(公告)日：2013-02-14
申请号：US13205186
申请日：2011-08-08
申请人： Fook-Luen HENG , Rajiv V. Joshi , Alexey Y. Lvov , Xiaoping Tang
发明人： Fook-Luen HENG , Rajiv V. Joshi , Alexey Y. Lvov , Xiaoping Tang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Methods and systems for migrating circuit layouts. A floorplan layout is built for a target circuit using a subset of constraints that characterize a layout structure of an original circuit. Shape-constraint-based scaling is used on the floorplan layout by scaling parts of the floorplan layout in accordance with a plurality of different scaling ratios such that portions of the floorplan layout are concurrently scaled with the plurality of different scaling ratios. Cells are placed at locations defined by the floorplan layout. The floorplan layout is checked with shape-constraint-based legalization using all of the constraints to produce a migrated layout.
摘要翻译：迁移电路布局的方法和系统。使用表征原始电路的布局结构的约束子集为目标电路构建平面图布局。通过根据多个不同的缩放比例缩放平面图布局的部分，使得平面图布局的部分与多个不同的缩放比同时缩放，从而在平面图布局上使用基于形状约束的缩放。细胞被放置在由平面图布局定义的位置处。使用所有约束来生成迁移的布局，使用基于形状约束的合法化来检查平面图布局。

57. 发明授权

US07994042B2 Techniques for impeding reverse engineering 有权
标题翻译：阻止逆向工程的技术
公开(公告)号：US07994042B2
公开(公告)日：2011-08-09
申请号：US11924735
申请日：2007-10-26
申请人： Louis L. Hsu , Rajiv V. Joshi , David W. Kruger
发明人： Louis L. Hsu , Rajiv V. Joshi , David W. Kruger
IPC分类号： H01L21/00
CPC分类号： H01L21/76816 , H01L21/76825 , H01L21/76831 , H01L21/76834 , H01L23/573 , H01L27/02 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one implant region within the insulating layer, the implanted ions being configured to alter an etch rate through the insulating layer within the implant region. The insulating layer is etched to, at the same time, form at least one void both within the implant region and outside of the implant region, wherein the etch rate through the insulating layer within the implant region is different from an etch rate through the insulating layer outside of the implant region. The void is filled with at least one conductor material to form the feature in the insulating layer.
摘要翻译：提供了反逆向工程技术。一方面，提供了一种在绝缘层中形成至少一个特征的方法。该方法包括以下步骤。离子选择性地植入绝缘层中，以在绝缘层内形成至少一个注入区域，所述注入离子被配置为改变通过植入区域内的绝缘层的蚀刻速率。蚀刻绝缘层，同时在植入区域内和植入区域外部形成至少一个空隙，其中通过绝缘层在植入区域内的蚀刻速率与通过绝缘体的蚀刻速率不同在植入区域外侧。空隙填充有至少一种导体材料以在绝缘层中形成特征。

58. 发明授权

US07968944B2 Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof 有权
标题翻译：具有混合体厚度的FET的集成电路芯片及其制造方法
公开(公告)号：US07968944B2
公开(公告)日：2011-06-28
申请号：US12541641
申请日：2009-08-14
申请人： Rajiv V. Joshi , Louis C. Hsu , Oleg Gluschenkov
发明人： Rajiv V. Joshi , Louis C. Hsu , Oleg Gluschenkov
IPC分类号： H01L27/12 , H01L29/00
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/78654
摘要： An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.
摘要翻译：一种集成电路（IC）芯片，其可以是具有绝缘体上硅（SOI）场效应晶体管（FET）和制造芯片的方法的体CMOS IC芯片。 IC芯片包括具有埋入绝缘体层的凹坑的区域，并且在层上形成的FET是SOI FET。 SOI FET可以包括部分耗尽的SOI（PD-SOI）FET和完全耗尽的SOI（FD-SOI）FET，并且芯片也可以包括体FET。 FET通过轮廓化晶片的表面，将氧气保形地均匀地注入到均匀的深度，并平坦化以去除体FET区域中的掩埋氧化物（BOX）来形成。

59. 发明授权

US07911025B2 Fuse/anti-fuse structure and methods of making and programming same 有权
标题翻译：保险丝/反熔丝结构及制作和编程方法相同
公开(公告)号：US07911025B2
公开(公告)日：2011-03-22
申请号：US12127080
申请日：2008-05-27
申请人： Louis C. Hsu , Rajiv V. Joshi , Jack Allan Mandelman , Chih-Chao Yang
发明人： Louis C. Hsu , Rajiv V. Joshi , Jack Allan Mandelman , Chih-Chao Yang
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor structure. Methods of making and programming the fuse/anti-fuse structures are also provided.
摘要翻译：提供了用于熔丝/反熔丝结构的技术，包括内部导体结构，从内部导体结构向外间隔开的绝缘层，设置在绝缘层外部的外部导体结构，以及限定空腔的空腔限定结构，其中所述空腔限定结构的至少一部分由所述内部导体结构，所述绝缘层和所述外部导体结构中的至少一个形成。还提供了制造和编程保险丝/反熔丝结构的方法。

60. 发明授权

US07873891B2 Programmable voltage divider 有权
标题翻译：可编程分压器
公开(公告)号：US07873891B2
公开(公告)日：2011-01-18
申请号：US12114853
申请日：2008-05-05
申请人： Yuen H. Chan , Rajiv V. Joshi
发明人： Yuen H. Chan , Rajiv V. Joshi
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A test circuit and programmable voltage divider that may be used in the test circuit. The programmable voltage divider develops a voltage difference signal that may be digitally selected. The test circuit may be used to test and characterize sense amplifiers. The programmable voltage divider develops a signal with a selected polarity and magnitude that is provided to a sense amplifier being tested. The sense amplifier is set and its output latched. The latch contents are checked against an expected value. The difference voltage may be changed and the path retested to find passing and failing points.
摘要翻译：可以在测试电路中使用的测试电路和可编程分压器。可编程分压器产生可以数字选择的电压差信号。测试电路可用于测试和表征读出放大器。可编程分压器产生具有所选极性和幅度的信号，该极性和幅度被提供给被测试的读出放大器。读出放大器设置并输出锁存。根据预期值检查锁存内容。可以改变差值电压，重新测试路径以找到通过点和故障点。

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