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1. 发明授权

US07911025B2 Fuse/anti-fuse structure and methods of making and programming same 有权
标题翻译：保险丝/反熔丝结构及制作和编程方法相同
公开(公告)号：US07911025B2
公开(公告)日：2011-03-22
申请号：US12127080
申请日：2008-05-27
申请人： Louis C. Hsu , Rajiv V. Joshi , Jack Allan Mandelman , Chih-Chao Yang
发明人： Louis C. Hsu , Rajiv V. Joshi , Jack Allan Mandelman , Chih-Chao Yang
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor structure. Methods of making and programming the fuse/anti-fuse structures are also provided.
摘要翻译：提供了用于熔丝/反熔丝结构的技术，包括内部导体结构，从内部导体结构向外间隔开的绝缘层，设置在绝缘层外部的外部导体结构，以及限定空腔的空腔限定结构，其中所述空腔限定结构的至少一部分由所述内部导体结构，所述绝缘层和所述外部导体结构中的至少一个形成。还提供了制造和编程保险丝/反熔丝结构的方法。

2. 发明授权

US07470929B2 Fuse/anti-fuse structure and methods of making and programming same 失效
公开(公告)号：US07470929B2
公开(公告)日：2008-12-30
申请号：US11491721
申请日：2006-07-24
申请人： Louis C. Hsu , Rajiv V. Joshi , Jack Allan Mandelman , Chih-Chao Yang
发明人： Louis C. Hsu , Rajiv V. Joshi , Jack Allan Mandelman , Chih-Chao Yang
IPC分类号： H01L29/10
CPC分类号： H01L23/5256 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor structure. Methods of making and programming the fuse/anti-fuse structures are also provided.

3. 发明申请

US20080224261A1 Fuse/anti-fuse structure and methods of making and programming same 有权
标题翻译：保险丝/反熔丝结构及制作和编程方法相同
公开(公告)号：US20080224261A1
公开(公告)日：2008-09-18
申请号：US12127080
申请日：2008-05-27
申请人： Louis C. Hsu , Rajiv V. Joshi , Jack Allan Mandelman , Chih-Chao Yang
发明人： Louis C. Hsu , Rajiv V. Joshi , Jack Allan Mandelman , Chih-Chao Yang
IPC分类号： H01L23/525 , H01L21/44
CPC分类号： H01L23/5256 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor stricture Methods of making and programming the fuse/anti-fuse structures are also provided.
摘要翻译：提供了用于熔丝/反熔丝结构的技术，包括内部导体结构，从内部导体结构向外间隔开的绝缘层，设置在绝缘层外部的外部导体结构，以及限定空腔的空腔限定结构，其中空腔限定结构的至少一部分由内部导体结构，绝缘层和外部导体狭窄中的至少一个形成。还提供了制造和编程熔丝/反熔丝结构的方法。

4. 发明申请

US20080017858A1 Fuse/anti-fuse structure and methods of making and programming same 失效
标题翻译：保险丝/反熔丝结构及制作和编程方法相同
公开(公告)号：US20080017858A1
公开(公告)日：2008-01-24
申请号：US11491721
申请日：2006-07-24
申请人： Louis C. Hsu , Rajiv V. Joshi , Jack Allan Mandelman , Chih-Chao Yang
发明人： Louis C. Hsu , Rajiv V. Joshi , Jack Allan Mandelman , Chih-Chao Yang
IPC分类号： H01L29/04
CPC分类号： H01L23/5256 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor structure. Methods of making and programming the fuse/anti-fuse structures are also provided.
摘要翻译：提供了用于熔丝/反熔丝结构的技术，包括内部导体结构，从内部导体结构向外间隔开的绝缘层，设置在绝缘层外部的外部导体结构，以及限定空腔的空腔限定结构，其中所述空腔限定结构的至少一部分由所述内部导体结构，所述绝缘层和所述外部导体结构中的至少一个形成。还提供了制造和编程保险丝/反熔丝结构的方法。

5. 发明授权

US07732922B2 Simultaneous grain modulation for BEOL applications 失效
标题翻译： BEOL应用的同时粒度调制
公开(公告)号：US07732922B2
公开(公告)日：2010-06-08
申请号：US11970149
申请日：2008-01-07
申请人： Chih-Chao Yang , Louis C. Hsu , Rajiv V. Joshi
发明人： Chih-Chao Yang , Louis C. Hsu , Rajiv V. Joshi
IPC分类号： H01L29/40
CPC分类号： H01L23/53238 , H01L23/5226 , H01L23/53233 , H01L2924/0002 , H01L2924/00
摘要： The invention is directed to an improved semiconductor structure, such that within the same insulating layer, Cu interconnects embedded within the same insulating level layer have a different Cu grain size than other Cu interconnects embedded within the same insulating level layer.
摘要翻译：本发明涉及一种改进的半导体结构，使得在同一绝缘层内嵌入相同绝缘层的Cu互连件具有与嵌入在同一绝缘层中的其它Cu互连不同的Cu晶粒尺寸。

6. 发明授权

US08169077B2 Dielectric interconnect structures and methods for forming the same 有权
标题翻译：介电互连结构及其形成方法
公开(公告)号：US08169077B2
公开(公告)日：2012-05-01
申请号：US12185759
申请日：2008-08-04
申请人： Chih-Chao Yang , Louis C. Hsu , Rajiv V. Joshi
发明人： Chih-Chao Yang , Louis C. Hsu , Rajiv V. Joshi
IPC分类号： H01L23/52
CPC分类号： H01L21/76834 , H01L21/76814 , H01L21/76826 , H01L21/76843 , H01L21/76844 , H01L21/76846
摘要： Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma (e.g., Ar, He, Ne, Xe, N2, H2, NH3, and N2H2). Under the present invention, the noble metal layer could be formed directly on an optional glue layer that is maintained only on vertical surfaces of any trench or via formed in the exposed dielectric layer. In addition, the noble metal layer may or may not be provided along an interface between the via and an internal metal layer.
摘要翻译：提供介电互连结构及其形成方法。具体地说，本发明提供一种具有贵金属层（例如，Ru，Ir，Rh，Pt，RuTa以及Ru，Ir，Rh，Pt和RuTa的合金）的电介质互连结构，其直接形成在改性电介质上表面。在典型的实施方案中，通过用气态离子等离子体（例如Ar，He，Ne，Xe，N 2，H 2，NH 3和N 2 H 2）处理互连结构的暴露介电层来产生修饰的电介质表面。在本发明中，贵金属层可以直接形成在只保留在暴露的介电层中形成的任何沟槽或通孔的垂直表面上的任选的胶层上。此外，贵金属层可以沿着通孔和内部金属层之间的界面设置也可以不设置。

7. 发明授权

US07727888B2 Interconnect structure and method for forming the same 有权
标题翻译：互连结构及其形成方法
公开(公告)号：US07727888B2
公开(公告)日：2010-06-01
申请号：US11216198
申请日：2005-08-31
申请人： Chih-Chao Yang , Louis C. Hsu , Rajiv V. Joshi
发明人： Chih-Chao Yang , Louis C. Hsu , Rajiv V. Joshi
IPC分类号： H01L29/41 , H01L21/44
CPC分类号： H01L21/76814 , H01L21/76805 , H01L21/76808 , H01L21/76831 , H01L21/76844 , H01L21/76846 , H01L21/76849 , H01L21/76855 , Y10S438/964
摘要： An interconnect structure and a method for forming the same are described. Specifically, under the present invention, a gouge is created within a via formed in the interconnect structure before any trenches are formed. This prevents the above-mentioned trench damage from occurring. That is, the bottom surface of the trenches will have a roughness of less than approximately 20 nm, and preferably less than approximately 10 nm. In addition to the via, gouge and trench(es), the interconnect structure of the present invention includes at least two levels of metal wiring. Further, in a typical embodiment, the interconnect structure utilizes any dielectrics having a dielectric constant no greater than approximately 5.0.
摘要翻译：描述了互连结构及其形成方法。具体地说，在本发明中，在形成任何沟槽之前，在互连结构中形成的通孔内形成一个沟槽。这防止了上述的沟槽损坏发生。也就是说，沟槽的底表面将具有小于约20nm，优选小于约10nm的粗糙度。除了通孔，沟槽和沟槽之外，本发明的互连结构还包括至少两层金属布线。此外，在典型的实施例中，互连结构利用介电常数不大于约5.0的任何电介质。

8. 发明申请

US20090174075A1 SIMULTANEOUS GRAIN MODULATION FOR BEOL APPLICATIONS 失效
标题翻译：用于BEOL应用的同时颗粒调节
公开(公告)号：US20090174075A1
公开(公告)日：2009-07-09
申请号：US11970149
申请日：2008-01-07
申请人： Chih-Chao Yang , Louis C. Hsu , Rajiv V. Joshi
发明人： Chih-Chao Yang , Louis C. Hsu , Rajiv V. Joshi
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L23/53238 , H01L23/5226 , H01L23/53233 , H01L2924/0002 , H01L2924/00
摘要： The invention is directed to an improved semiconductor structure, such that within the same insulating layer, Cu interconnects embedded within the same insulating level layer have a different Cu grain size than other Cu interconnects embedded within the same insulating level layer.
摘要翻译：本发明涉及一种改进的半导体结构，使得在同一绝缘层内嵌入相同绝缘层的Cu互连件具有与嵌入在同一绝缘层中的其它Cu互连不同的Cu晶粒尺寸。

9. 发明申请

US20090023286A1 DIELECTRIC INTERCONNECT STRUCTURES AND METHODS FOR FORMING THE SAME 有权
标题翻译：介电互连结构及其形成方法
公开(公告)号：US20090023286A1
公开(公告)日：2009-01-22
申请号：US12173899
申请日：2008-07-16
申请人： Chih-Chao Yang , Louis C. Hsu , Rajiv V. Joshi
发明人： Chih-Chao Yang , Louis C. Hsu , Rajiv V. Joshi
IPC分类号： H01L21/768
CPC分类号： H01L21/76834 , H01L21/76814 , H01L21/76826 , H01L21/76843 , H01L21/76844 , H01L21/76846
摘要： Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma (e.g., Ar, He, Ne, Xe, N2, H2, NH3, and N2H2). Under the present invention, the noble metal layer could be formed directly on an optional glue layer that is maintained only on vertical surfaces of any trench or via formed in the exposed dielectric layer. In addition, the noble metal layer may or may not be provided along an interface between the via and an internal metal layer.
摘要翻译：提供介电互连结构及其形成方法。具体地说，本发明提供一种具有贵金属层（例如，Ru，Ir，Rh，Pt，RuTa以及Ru，Ir，Rh，Pt和RuTa的合金）的电介质互连结构，其直接形成在改性电介质上表面。在典型的实施方案中，通过用气态离子等离子体（例如Ar，He，Ne，Xe，N 2，H 2，NH 3和N 2 H 2）处理互连结构的暴露介电层来产生修饰的电介质表面。在本发明中，贵金属层可以直接形成在只保留在暴露的介电层中形成的任何沟槽或通孔的垂直表面上的任选的胶层上。此外，贵金属层可以沿着通孔和内部金属层之间的界面设置也可以不设置。

10. 发明申请

US20080290518A1 DIELECTRIC INTERCONNECT STRUCTURES AND METHODS FOR FORMING THE SAME 有权
标题翻译：介电互连结构及其形成方法
公开(公告)号：US20080290518A1
公开(公告)日：2008-11-27
申请号：US12185759
申请日：2008-08-04
申请人： Chih-Chao Yang , Louis C. Hsu , Rajiv V. Joshi
发明人： Chih-Chao Yang , Louis C. Hsu , Rajiv V. Joshi
IPC分类号： H01L23/52
CPC分类号： H01L21/76834 , H01L21/76814 , H01L21/76826 , H01L21/76843 , H01L21/76844 , H01L21/76846
摘要： Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma (e.g., Ar, He, Ne, Xe, N2, H2, NH3, and N2H2). Under the present invention, the noble metal layer could be formed directly on an optional glue layer that is maintained only on vertical surfaces of any trench or via formed in the exposed dielectric layer. In addition, the noble metal layer may or may not be provided along an interface between the via and an internal metal layer.
摘要翻译：提供介电互连结构及其形成方法。具体地说，本发明提供一种具有贵金属层（例如，Ru，Ir，Rh，Pt，RuTa以及Ru，Ir，Rh，Pt和RuTa的合金）的电介质互连结构，其直接形成在改性电介质上表面。在典型的实施方案中，通过用气态离子等离子体（例如Ar，He，Ne，Xe，N 2，H 2，NH 3和N 2 H 2）处理互连结构的暴露介电层来产生修饰的电介质表面。在本发明中，贵金属层可以直接形成在只保留在暴露的介电层中形成的任何沟槽或通孔的垂直表面上的任选的胶层上。此外，贵金属层可以沿着通孔和内部金属层之间的界面设置也可以不设置。

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