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51. 发明授权

US06347349B1 System for determining whether a subsequent transaction may be allowed or must be allowed or must not be allowed to bypass a preceding transaction 有权
标题翻译：用于确定是否允许或必须允许后续交易或不允许绕过前一交易的系统
公开(公告)号：US06347349B1
公开(公告)日：2002-02-12
申请号：US09221936
申请日：1998-12-28
申请人： Danny Marvin Neal , Steven Mark Thurber
发明人： Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1314
CPC分类号： G06F13/4036
摘要： An apparatus and method for mediating a sequence of transactions across a fabric in a data processing system are implemented. A fabric bridge orders a preceding transaction and a subsequent transaction according to a predetermined protocol. Using the protocol a determination is made whether the subsequent transaction may be allowed to bypass the previous transaction, must be allowed to bypass the previous transaction, or must not be allowed to bypass the preceding transaction. Transactions include load/store (L/S) system memory and L/S to input/output (I/O) device, and direct memory access (DMA) to system memory and DMA peer-to-peer transactions.
摘要翻译：实现了一种用于在数据处理系统中跨结构的中介交易序列的装置和方法。织物桥根据预定的协议订购前一事务和后续事务。使用协议确定后续事务是否可以绕过先前的事务，必须被允许绕过先前的事务，或不得允许绕过上一个事务。交易包括对输入/输出（I / O）设备的加载/存储（L / S）系统存储器和L / S以及对系统存储器和DMA对等交易的直接存储器访问（DMA）。

52. 发明授权

US06240474B1 Pipelined read transfers 失效
标题翻译：流水线读取传输
公开(公告)号：US06240474B1
公开(公告)日：2001-05-29
申请号：US08931705
申请日：1997-09-16
申请人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1314
CPC分类号： G06F13/28 , G06F13/4027
摘要： A methodology and implementing system are provided in which pipelined read transfers or PRTs are implemented. The PRTs include a request phase and a response phase. The PRT request phase involves a PRT request master delivering to a PRT request target, a source address, a destination address and the transfer size for the data being requested. In the PRT response phase, the PRT request target becomes a PRT response master, i.e. a PCI bus master, and initiates a completion of the transaction that was requested in the originating PRT request.
摘要翻译：提供了一种实现流水线读取传输或PRT的方法和实现系统。 PRT包括请求阶段和响应阶段。 PRT请求阶段涉及PRT请求主机传送到PRT请求目标，源地址，目的地地址和正在请求的数据的传输大小。在PRT响应阶段，PRT请求目标成为PRT响应主机，即PCI总线主机，并启动完成在发起PRT请求中请求的事务。

53. 发明授权

US06185642B2 Bus for high frequency operation with backward compatibility and hot-plug ability 失效
标题翻译：高性能PCI总线，用于高频操作，具有向后兼容性和热插拔能力
公开(公告)号：US06185642B2
公开(公告)日：2001-02-06
申请号：US09116058
申请日：1998-07-15
申请人： Bruce Leroy Beukema , Ronald Edward Fuhs , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Bruce Leroy Beukema , Ronald Edward Fuhs , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1300
CPC分类号： G06F13/4081
摘要： A peripheral interconnect for a computer system comprising a bridge, a peripheral bus, and a peripheral device, wherein at least one of these components is adapted to selectively operate in either a high performance mode or a low performance mode, the high performance mode using a first operating speed and a first protocol, and the low performance mode using a second operating speed which is lower than said first operating speed, and a second protocol which is different from the first protocol. The disclosed embodiment provides a high performance mode with a 100 MHz speed and a protocol that disallows pacing, and a low performance mode that uses a 66 MHz or 33 MHz speed and a standard PCI protocol that allows pacing. The high performance operating speed can be twice the low performance operating speed, by doubling the clock frequency and clocking data on only one clock edge, or by clocking data on both a rising edge and a falling edge of a clock signal while operating at the lower clock frequency. High performance adapters can provide split transaction capability, with a high performance bridge having the ability to support split transactions or alias split transactions to delayed transactions. Backward compatibility may also be provided for optional features such as hot-pluggability.
摘要翻译：一种用于包括桥接器，外围总线和外围设备的计算机系统的外设互连，其中这些组件中的至少一个适于选择性地以高性能模式或低性能模式操作，高性能模式使用第一操作速度和第一协议，以及使用低于所述第一操作速度的第二操作速度的低性能模式，以及不同于第一协议的第二协议。所公开的实施例提供具有100MHz速度的高性能模式和不允许起搏的协议，以及使用66MHz或33MHz速度的低性能模式和允许起搏的标准PCI协议。高性能运行速度可以是低性能运行速度的两倍，通过在一个时钟沿将时钟频率和时钟数据加倍，或者在时钟信号的上升沿和下降沿同时处理数据，同时在较低的时钟时钟频率。高性能适配器可以提供拆分事务功能，具有支持拆分事务或别名拆分事务延迟事务的高性能网桥。也可以向后兼容性提供可选功能，如热插拔。

54. 发明授权

US06175888B1 Dual host bridge with peer to peer support 失效
标题翻译：双主机桥与对等支持
公开(公告)号：US06175888B1
公开(公告)日：2001-01-16
申请号：US08627810
申请日：1996-04-10
申请人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1314
CPC分类号： G06F13/36 , G06F13/4027
摘要： A data processing system includes a processor, system memory and a number of peripheral devices, and one or more bridges which may connect between the processor, memory and peripheral devices and other hosts or peripheral devices such as in a network. A bridge, such as a PCI host bridge, connects between a primary bus (e.g system bus) and a secondary bus. The host bridge provides a dual host bridge function which creates two secondary bus interfaces. This allows increased loading capability under one dual host bridge compared to a lesser number of slots allowed under one normal host bridge. Also included is additional control logic for providing arbitration control and for steering transactions to the appropriate bus interface. Additionally, peer to peer support across the two secondary bus interfaces in provided.
摘要翻译：数据处理系统包括处理器，系统存储器和多个外围设备以及可以在处理器，存储器和外围设备以及诸如网络中的其它主机或外围设备之间连接的一个或多个桥接器。诸如PCI主机桥的桥连接在主总线（例如系统总线）和辅助总线之间。主桥提供双主机桥功能，其创建两个辅助总线接口。这允许在一个双主机桥下增加负载能力，而在一个正常主桥下允许的较少数量的时隙。还包括附加的控制逻辑，用于提供仲裁控制和用于转向事务到适当的总线接口。另外，提供的两个辅助总线接口的对等支持。

55. 发明授权

US6134621A Variable slot configuration for multi-speed bus 失效
标题翻译：多速总线可变插槽配置
公开(公告)号：US6134621A
公开(公告)日：2000-10-17
申请号：US092153
申请日：1998-06-05
申请人： Richard Allen Kelley , Danny Marvin Neal , James Otto Nicholson , Steven Mark Thurber
发明人： Richard Allen Kelley , Danny Marvin Neal , James Otto Nicholson , Steven Mark Thurber
IPC分类号： G06F13/14 , G06F13/40 , G06F13/00 , G06F1/08 , G06F13/38
CPC分类号： G06F13/4068
摘要： A method and apparatus are provided in which a control scheme is implemented to enable a PCI bus to operate more than two PCI slots into which PCI devices may be installed. The PCI slots are checked to determine if a PCI device is installed in the slots and the speed at which the installed PCI devices are capable of running. If any of the slots has a 33 MHz device installed in any of the slots, the system is enabled to run more than two slots, and all of the PCI devices will run at 33 MHz. When no 33 MHz cards or devices are installed in the PCI slots, and PCI devices are only installed in the first two slots, then the system is enabled to run only the first two slots at the speed of 66 MHz. In one alternative embodiment, a default configuration routine sets the PCI bus speed at one of the operating frequencies and modifies that default if it is determined during a system configuration cycle that another speed is more appropriate.
摘要翻译：提供了一种方法和装置，其中实现控制方案以使得PCI总线能够操作可以安装PCI设备的两个以上PCI插槽。检查PCI插槽以确定PCI设备是否安装在插槽中以及安装的PCI设备能够运行的速度。如果任何插槽中的任何一个插槽中都安装了一个33 MHz器件，则系统可以运行多于两个插槽，所有PCI设备将以33 MHz运行。当PCI插槽中没有安装33 MHz的卡或设备时，PCI设备仅安装在前两个插槽中，则系统只能以66 MHz的速度运行前两个插槽。在一个替代实施例中，默认配置例程将PCI总线速度设置为工作频率之一，并且如果在系统配置周期期间确定另一个速度更合适，则修改该默认值。

56. 发明授权

US6119191A Performing PCI access cycles through PCI bridge hub routing 有权
标题翻译：通过PCI桥中心路由执行PCI访问周期
公开(公告)号：US6119191A
公开(公告)日：2000-09-12
申请号：US144869
申请日：1998-09-01
申请人： Danny Marvin Neal , Steven Mark Thurber
发明人： Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F13/40 , G06F3/00 , G06F13/00
CPC分类号： G06F13/404
摘要： A method and implementing computer system is provided in which PCI CONFIG.sub.-- ADDRESS and CONFIG.sub.-- DATA conventions are maintained in a large computer system and each PCI Host Bridge (PHB) CONFIG.sub.-- ADDRESS register and each PHB CONFIG.sub.-- DATA register have separate and system-unique addresses. In one example, the operating system provides a service to translate the device driver's configuration operation to a particular bus and device in the system, to a particular CONFIG.sub.-- ADDRESS or CONFIG.sub.-- DATA register of the PHB which has that device under it. By using this method, the hierarchical system can use architecture-independent routing of addresses down to the PHB that contains the appropriate CONFIG.sub.-- ADDRESS and CONFIG.sub.-- DATA registers.
摘要翻译：提供了一种方法和实现的计算机系统，其中在大型计算机系统中维护PCI CONFIG-ADDRESS和CONFIG-DATA约定，并且每个PCI主机桥（PHB）CONFIG-ADDRESS寄存器和每个PHB CONFIG-DATA寄存器具有单独的系统 - 唯一地址。在一个示例中，操作系统提供服务以将设备驱动程序的配置操作转换为系统中的特定总线和设备，到具有该设备的PHB的特定CONFIG-ADDRESS或CONFIG-DATA寄存器。通过使用这种方法，分级系统可以使用地址下降到包含适当的CONFIG-ADDRESS和CONFIG-DATA寄存器的PHB的架构独立路由。

57. 发明授权

US6035355A PCI system and adapter requirements following reset 失效
标题翻译：复位后的PCI系统和适配器要求
公开(公告)号：US6035355A
公开(公告)日：2000-03-07
申请号：US67042
申请日：1998-04-27
申请人： Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F13/10 , G06F9/445 , G06F13/14 , G06F13/00
CPC分类号： G06F9/4411
摘要： A method of registering a newly added peripheral device with a computer system by responding with a status message from the device to a bus of the computer system, in response to an access attempt, and within a predetermined time period from the deasserting of the reset signal applied to device, so as to avoid stalling and thereby avoid the need to reboot the system in order to initialize the new peripheral device with the operating system. The device may be allowed to initially send a retry response, provided the response occurs during an initial latency period which is less than the predetermined time period. The invention also enables the peripheral device to respond to non-configuration cycles immediately following configuration completion. Internal logic of the peripheral device can be initialized after responding with the status message. Non-configuration access to the peripheral device can be prevented until it is ready to respond, by setting a bit (in the configuration space of the peripheral device to indicate that the peripheral device is ready.
摘要翻译：一种通过响应于访问尝试而将来自设备的状态消息与计算机系统的总线进行响应的计算机系统注册新添加的外围设备的方法，并且在从复位信号的解除的预定时间段内应用于设备，以避免停顿，从而避免重新启动系统以便使用操作系统初始化新的外围设备。如果响应发生在小于预定时间段的初始等待时间期间，则可以允许该设备最初发送重试响应。本发明还使外围设备能够在配置完成之后立即响应非配置周期。外部设备的内部逻辑可以在响应状态消息后进行初始化。可以通过设置一个位（在外围设备的配置空间中指示外围设备准备好）来准备好响应外部设备的非配置访问。

58. 发明授权

US6033254A Locating and guidance device for printed circuit boards 失效
标题翻译：印刷电路板定位和导向装置
公开(公告)号：US6033254A
公开(公告)日：2000-03-07
申请号：US859448
申请日：1997-05-20
申请人： Danny Marvin Neal , Roy Albert Rachui , James Robert Taylor , Fred Ervin Zumwalt
发明人： Danny Marvin Neal , Roy Albert Rachui , James Robert Taylor , Fred Ervin Zumwalt
IPC分类号： H01R12/70 , H01R12/88 , H01R13/629 , H01R13/64
CPC分类号： H01R12/7005 , H01R12/88 , H01R13/62905
摘要： A circuit board guidance device is arranged to have a circuit board such as a PCI I/O board 205 inserted therein for connection into an electrical socket or connector 203 located on a system motherboard 201. The guidance device includes a guidance mechanism which translates an insertion force applied in one direction into a connecting force effective to move the circuit board in a second direction. The guidance device is effective to aid in locating the circuit board 205 above connector 203 on the system motherboard 201, and also to aid in forcing the desired electrical connection between corresponding connectors on the circuit board 205 and a system motherboard 201. The guidance device is also effective in aiding in the extraction of the circuit board from its connection to the motherboard connector 203. An I/O bracket 261 is implemented to provide EMI grounding to the system bulkhead.
摘要翻译：电路板引导装置被布置成具有插入其中的诸如PCI I / O板205的电路板，用于连接到位于系统主板201上的电插座或连接器203.引导装置包括引导机构，其将插入沿一个方向施加的力作用于沿着第二方向移动电路板的连接力。引导装置有助于将系统母板201上的连接器203上的电路板205定位，并且还有助于强制电路板205上的相应连接器和系统母板201之间的期望的电连接。引导装置是还有效地帮助将电路板从与主板连接器203的连接提取。执行I / O支架261以向系统隔板提供EMI接地。

59. 发明授权

US5887144A Method and system for increasing the load and expansion capabilities of a bus through the use of in-line switches 失效
标题翻译：通过使用在线开关增加总线的负载和扩展能力的方法和系统
公开(公告)号：US5887144A
公开(公告)日：1999-03-23
申请号：US753116
申请日：1996-11-20
申请人： Guy Lynn Guthrie , Danny Marvin Neal , Richard Allen Kelley
发明人： Guy Lynn Guthrie , Danny Marvin Neal , Richard Allen Kelley
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4068
摘要： A method and system for expanding the load capabilities of a bus, such as the PCI bus. The system includes a primary bus, a plurality of secondary buses for connecting additional devices, a plurality of in-line switches, an arbiter, and control logic means. The plurality of in-line switches are used for connecting the primary bus to a corresponding one of the secondary buses, each one of the switches having an enable line for receiving a signal to enable or disable the switch. The arbiter is used for receiving requests for control of the primary bus, and for selecting one of the requests as a master for the control. The control logic means is used for enabling and disabling each of the switches, via the corresponding enable line, for connection or disconnection to the primary bus. The control logic means includes means, coupled to the arbiter, for gaining control over the primary bus prior to granting control to the master, and means for transmitting, during control over the primary bus, an enable signal to the switches corresponding to the secondary buses desired to be connected to the primary bus.
摘要翻译：一种用于扩展总线（如PCI总线）的负载能力的方法和系统。该系统包括主总线，用于连接附加设备的多个次总线，多个在线交换机，仲裁器和控制逻辑装置。多个在线开关用于将主总线连接到相应的一个辅助总线，每个开关具有用于接收信号以启用或禁用开关的使能线。仲裁器用于接收对主总线的控制请求，并用于选择其中一个请求作为控制主机。控制逻辑装置用于通过相应的使能线路使能和禁用每个开关用于连接或断开到主总线。控制逻辑装置包括耦合到仲裁器的装置，用于在向主机授予控制之前获得对主总线的控制，以及用于在对主总线进行控制期间向对应于辅助总线的开关发送使能信号的装置希望连接到主总线。

60. 发明授权

US5875310A Secondary I/O bus with expanded slot capacity and hot plugging capability 失效
标题翻译：具有扩展槽容量和热插拔能力的二次I / O总线
公开(公告)号：US5875310A
公开(公告)日：1999-02-23
申请号：US653040
申请日：1996-05-24
申请人： Patrick Allen Buckland , Richard Allen Kelley , Danny Marvin Neal
发明人： Patrick Allen Buckland , Richard Allen Kelley , Danny Marvin Neal
IPC分类号： G06F1/26 , G06F13/36 , G06F13/40
CPC分类号： G06F13/4081 , Y02B60/1228 , Y02B60/1235
摘要： A computer system is provided which supports an increase in the number of pluggable cards on the secondary I/O bus by using driver/receiver modules and direction control logic in place of more complex and more expensive bus to bus bridges. The number of pluggable cards on the I/O bus in a computer system is limited by the electrical loading of each card and the frequency of operations on the bus. Reducing the bus frequency provides more signal propagation time. The added signal propagation time supports the extension of the bus by driver/receiver modules and logic which controls the direction the driver/receiver modules drive the bus signals. Further, the driver/receiver modules support changing the hardware configuration of the system by adding or removing an I/O card without the need to cease data processing activity for the entire computer.
摘要翻译：提供了一种计算机系统，其通过使用驱动器/接收器模块和方向控制逻辑来代替更复杂和更昂贵的总线到总线桥，支持次级I / O总线上的可插拔卡的数量的增加。计算机系统中I / O总线上的可插拔卡的数量受到每个卡的电气负载和总线上的操作频率的限制。减少总线频率提供更多的信号传播时间。增加的信号传播时间支持由驱动器/接收器模块和控制驱动器/接收器模块驱动总线信号的方向的逻辑扩展总线。此外，驱动程序/接收器模块支持通过添加或删除I / O卡来更改系统的硬件配置，而无需停止整个计算机的数据处理活动。

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