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51. 发明授权

US08878257B2 Methods and apparatus for an ISFET 有权
标题翻译： ISFET的方法和装置
公开(公告)号：US08878257B2
公开(公告)日：2014-11-04
申请号：US12794591
申请日：2010-06-04
申请人： Patrice M. Parris , Weize Chen , Richard J. De Souza , Md M. Hoque , John M. McKenna
发明人： Patrice M. Parris , Weize Chen , Richard J. De Souza , Md M. Hoque , John M. McKenna
IPC分类号： G01N27/414 , H01L27/115 , H01L29/788 , H01L29/94 , H01L49/02 , G11C16/04 , H01L29/66 , H01L23/522
CPC分类号： G01N27/4148 , G05F1/575 , G11C16/0416 , H01L21/28035 , H01L23/5223 , H01L27/11526 , H01L27/11558 , H01L28/40 , H01L28/60 , H01L29/66825 , H01L29/788 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.
摘要翻译： ISFET包括耦合到CMOS器件中的浮动栅极的控制栅极。控制栅极，例如多孔阱电容器被配置为接收偏置电压并且在控制栅极和浮置栅极之间实现俘获电荷的移动。因此，ISFET的阈值电压可以被修整到预定值，从而将修剪信息（浮置栅极中的俘获电荷的量）存储在ISFET本身内。

52. 发明申请

US20140252472A1 SEMICONDUCTOR DEVICE WITH INCREASED SAFE OPERATING AREA 有权
标题翻译：具有增加的安全操作区域的半导体器件
公开(公告)号：US20140252472A1
公开(公告)日：2014-09-11
申请号：US13792876
申请日：2013-03-11
申请人： Weize Chen , Patrice M. Parris
发明人： Weize Chen , Patrice M. Parris
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7816 , H01L29/0653 , H01L29/0847 , H01L29/1083 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： A semiconductor device includes a substrate having a surface, a composite body region disposed in the substrate, having a first conductivity type, and comprising a body contact region at the surface of the substrate and a well in which a channel is formed during operation, a source region disposed in the semiconductor substrate adjacent the composite body region and having a second conductivity type, and an isolation region disposed between the body contact region and the source region. The composite body region further includes a body conduction path region contiguous with and under the source region, and the body conduction path region has a higher dopant concentration level than the well.
摘要翻译：半导体器件包括具有表面的衬底，设置在衬底中的复合体区域，具有第一导电类型，并且包括在衬底的表面处的体接触区域和在操作期间形成沟道的阱，源极区域，设置在与所述复合体区域相邻并具有第二导电类型的所述半导体衬底中;以及隔离区域，设置在所述本体接触区域和所述源极区域之间。复合体区域还包括与源极区域相邻并且在源极区域附近的体导电路径区域，并且身体传导路径区域具有比阱更高的掺杂剂浓度水平。

53. 发明申请

US20140242762A1 Tunable Schottky Diode with Depleted Conduction Path 有权
标题翻译：可调谐肖特基二极管与耗散的导通路径
公开(公告)号：US20140242762A1
公开(公告)日：2014-08-28
申请号：US14269825
申请日：2014-05-05
申请人： Weize Chen , Xin Lin , Patrice M. Parris
发明人： Weize Chen , Xin Lin , Patrice M. Parris
IPC分类号： H01L29/66 , H01L27/06
CPC分类号： H01L29/66893 , H01L27/0629 , H01L29/0619 , H01L29/0623 , H01L29/0653 , H01L29/0692 , H01L29/08 , H01L29/1066 , H01L29/107 , H01L29/66143 , H01L29/872
摘要： A method of fabricating a Schottky diode having an integrated junction field-effect transistor (JFET) device includes forming a conduction path region in a semiconductor substrate along a conduction path of the Schottky diode. The conduction path region has a first conductivity type. A lateral boundary of an active area of the Schottky diode is defined by forming a well of a device isolating structure in the semiconductor substrate having a second conductivity type. An implant of dopant of the second conductivity type is conducted to form a buried JFET gate region in the semiconductor substrate under the conduction path region. The implant is configured to further form the device isolating structure in which the Schottky diode is disposed.
摘要翻译：制造具有集成结型场效应晶体管（JFET）器件的肖特基二极管的方法包括沿着肖特基二极管的导通路径在半导体衬底中形成导电路径区域。导电路径区域具有第一导电类型。通过在具有第二导电类型的半导体衬底中形成器件隔离结构的阱来限定肖特基二极管的有源区的横向边界。进行第二导电类型的掺杂剂的注入以在导电路径区域下的半导体衬底中形成掩埋JFET栅极区域。植入物构造成进一步形成其中设置肖特基二极管的器件隔离结构。

54. 发明申请

US20110261500A1 BACK END OF LINE METAL-TO-METAL CAPACITOR STRUCTURES AND RELATED FABRICATION METHODS 审中-公开
标题翻译：金属 - 金属电容器结构的背面和相关制造方法
公开(公告)号：US20110261500A1
公开(公告)日：2011-10-27
申请号：US12765575
申请日：2010-04-22
申请人： Patrice M. Parris , Richard J. De Souza , Weize Chen , Moaniss Zitouni
发明人： Patrice M. Parris , Richard J. De Souza , Weize Chen , Moaniss Zitouni
IPC分类号： H01G4/00 , B05D5/12
CPC分类号： H01G4/33 , H01G4/232 , H01L23/5223 , H01L28/86 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： Apparatus and related fabrication methods are provided for capacitor structures. One embodiment of a capacitor structure comprises a plurality of consecutive metal layers and another metal layer. Each via layer of a plurality of via layers is interposed between metal layers of the plurality of metal layers. The plurality of metal layers and the plurality of via layers are cooperatively configured to provide a first plurality of vertical conductive structures corresponding to a first electrode and a second plurality of vertical conductive structures corresponding to a second electrode. The plurality of consecutive metal layers form a plurality of vertically-aligned regions and provide intralayer electrical interconnections among the first plurality of vertical conductive structures. The first metal layer provides an intralayer electrical interconnection among the second plurality of vertical conductive structures, wherein each vertically-aligned region has a vertical conductive structure of the second plurality of vertical conductive structures disposed therein.
摘要翻译：为电容器结构提供了装置和相关的制造方法。电容器结构的一个实施例包括多个连续的金属层和另一个金属层。多个通孔层的每个通孔层插入在多个金属层的金属层之间。多个金属层和多个通孔层协作地构造成提供对应于对应于第二电极的第一电极和第二多个垂直导电结构的第一多个垂直导电结构。多个连续的金属层形成多个垂直排列的区域，并且在第一多个垂直导电结构之间提供层间电互连。第一金属层在第二多个垂直导电结构之间提供内层电互连，其中每个垂直对齐区域具有设置在其中的第二多个垂直导电结构的垂直导电结构。

55. 发明申请

US20090267127A1 Single Poly NVM Devices and Arrays 有权
标题翻译：单Poly NVM器件和阵列
公开(公告)号：US20090267127A1
公开(公告)日：2009-10-29
申请号：US12109736
申请日：2008-04-25
申请人： Weize Chen , Richard J. De Souza , Xin Lin , Patrice M. Parris
发明人： Weize Chen , Richard J. De Souza , Xin Lin , Patrice M. Parris
IPC分类号： H01L27/115 , H01L21/8247 , H01L21/8242
CPC分类号： H01L29/7881 , G11C16/10 , H01L27/11519 , H01L27/11521 , H01L29/42324
摘要： A single-poly non-volatile memory includes a PMOS select transistor (210) formed with a select gate (212), and P+ source and drain regions (211, 213) formed in a shared n-well region (240), a serially connected PMOS floating gate transistor (220) formed with part of a p-type floating gate layer (222) and P+ source and drain regions (221, 223) formed in the shared n-well region (240), and a coupling capacitor (230) formed over a p-well region (250) and connected to the PMOS floating gate transistor (220), where the coupling capacitor (230) includes a first capacitor plate formed with a second part of the p-type floating gate layer (222) and an underlying portion of the p-well region (250).
摘要翻译：单多晶非易失性存储器包括形成有选择栅极（212）的PMOS选择晶体管（210），以及形成在共享的n阱区域（240）中的P +源区和漏区（211,213）形成有形成在共用n阱区域（240）中的p型浮栅（222）和P +源区和漏区（221,223）的一部分的连接PMOS浮栅晶体管（220）和耦合电容器 230），其形成在p阱区（250）上并连接到PMOS浮栅晶体管（220），其中耦合电容器（230）包括形成有p型浮栅的第二部分的第一电容器板（ 222）和p阱区（250）的下层部分。

56. 发明授权

US07740805B2 Integrated CMOS-compatible biochip 失效
标题翻译：集成CMOS兼容生物芯片
公开(公告)号：US07740805B2
公开(公告)日：2010-06-22
申请号：US11095338
申请日：2005-03-31
申请人： Patrice M. Parris
发明人： Patrice M. Parris
IPC分类号： B01L3/00
CPC分类号： B01L3/502715 , B01L3/502707 , B01L2200/10 , B01L2200/12 , B01L2300/023 , B01L2300/024 , B01L2300/0627 , B01L2300/0645 , B01L2400/0406 , B01L2400/0415 , G01N2035/00158
摘要： A device for analyzing a fluid sample is provided. The device includes a substrate, a trench formed in said substrate, and a processor. The trench includes a channel, a sample chamber, and a reagent chamber, each in fluid communication with each another. The sample chamber is configured to receive the fluid sample. The processor is integrally formed in the substrate and is in communication with the trench. The processor is configured to analyze the fluid sample. Methods for manufacturing the device are also provided.
摘要翻译：提供了用于分析流体样品的装置。该器件包括衬底，形成在所述衬底中的沟槽和处理器。沟槽包括各自彼此流体连通的通道，样品室和试剂室。样品室被配置为接收流体样品。处理器一体地形成在基板中并且与沟槽连通。处理器配置为分析流体样品。还提供了用于制造该装置的方法。

57. 发明授权

US5892379A Transistor protection circuit and method 失效
标题翻译：晶体管保护电路及方法
公开(公告)号：US5892379A
公开(公告)日：1999-04-06
申请号：US867661
申请日：1997-06-02
申请人： Juan Buxo , Andreas A. Wild , Gary H. Loechelt , Thomas E. Zirkle , E. James Prendergast , Patrice M. Parris
发明人： Juan Buxo , Andreas A. Wild , Gary H. Loechelt , Thomas E. Zirkle , E. James Prendergast , Patrice M. Parris
IPC分类号： H03K17/0812 , H03K19/003 , H03B1/00 , H03K17/687
CPC分类号： H03K17/08122 , H03K19/00315
摘要： A circuit and method protect a transistor (68, 70) from damage when controlling an input signal (V.sub.PROG) that exceeds a gate to channel stress voltage of the transistor. A small, low current protection transistor (64, 66) is serially coupled to the gate electrode of the transistor being protected. The gate of the protection transistor is biased to a voltage (V.sub.P, V.sub.N) of lower magnitude than the input signal to limit the voltage applied to the gate of the protected transistor to a value within the stress voltage of the protected transistor.
摘要翻译：当控制超过晶体管的栅极至沟道应力电压的输入信号（VPROG）时，电路和方法保护晶体管（68,70）免受损坏。一个小的低电流保护晶体管（64,66）串联耦合到被保护的晶体管的栅电极。保护晶体管的栅极被偏置为比输入信号更低的电压（VP，VN），以将施加到受保护晶体管的栅极的电压限制在受保护晶体管的应力电压内的值。

58. 发明授权

US09927392B2 Sensing field effect transistor devices, systems in which they are incorporated, and methods of their fabrication 有权
公开(公告)号：US09927392B2
公开(公告)日：2018-03-27
申请号：US14459841
申请日：2014-08-14
申请人： Raymond M. Roop , Jose Fernandez Villasenor , Stephen R. Hooper , Patrice M. Parris
发明人： Raymond M. Roop , Jose Fernandez Villasenor , Stephen R. Hooper , Patrice M. Parris
IPC分类号： G01N27/414 , H05K3/10
CPC分类号： G01N27/4148
摘要： Embodiments of sensing devices include one or more integrated circuit (IC) die, a housing, and a fluid barrier material. Each IC die includes an electrode-bearing surface and a contact surface. One of the die includes an SFET with a sensing electrode proximate to the electrode-bearing surface. The same or a different die includes a reference electrode proximate to the electrode-bearing surface. The die(s) also include IC contacts at the contact surface(s), and conductive structures coupled between the SFET, the reference electrode, and the IC contacts. The housing includes a mounting surface, and housing contacts formed at the mounting surface. The IC contacts are coupled to the housing contacts. The fluid barrier material is positioned between the mounting surface and the IC die. The fluid barrier material provides a fluid barrier between the IC and housing contacts and a space that encompasses the sensing electrode and the reference electrode.

59. 发明申请

US20100109090A1 CMOS LATCH-UP IMMUNITY 有权
公开(公告)号：US20100109090A1
公开(公告)日：2010-05-06
申请号：US12262922
申请日：2008-10-31
申请人： Moaniss Zitouni , Patrice M. Parris
发明人： Moaniss Zitouni , Patrice M. Parris
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/0921 , H01L21/823878
摘要： Latch-up of CMOS devices (20, 20′) is improved by using a structure (40, 40′, 80) having electrically coupled but floating doped regions (64, 64′; 65, 65′) between the N-channel (44) and P-channel (45) devices. The doped regions (64, 64′; 65, 65′) desirably lie substantially parallel to the source-drain regions (422, 423; 432, 433) of the devices (44, 45) between the Pwell (42) and Nwell (43) regions in which the source-drain regions (422, 423; 432, 433) are located. A first (“N BAR”) doped region (64, 64′) forms a PN junction (512) with the Pwell (42), spaced apart from a source/drain region (423) in the Pwell (42), and a second (“P BAR”) doped region (55, 55′) forms a PN junction (513) with the Nwell (43), spaced apart from a source/drain region (433) in the Nwell (43). A further NP junction (511) lies between the N BAR (64) and P BAR (65) regions. The N BAR (64) and P BAR (65) regions are ohmically coupled, preferably by a low resistance metal conductor (62), and otherwise floating with respect to the device or circuit reference potentials (e.g., Vss, Vdd).
摘要翻译：通过使用具有电耦合但浮置的掺杂区域（64,64'; 65,65'）的结构（40,40'，80）来改善CMOS器件（20,20'）的锁存，N结构 44）和P沟道（45）器件。掺杂区域（64,64'; 65,65'）理想地位于Pwell（42）和Nwell（...）之间的器件（44,45）的源极 - 漏极区域（422,423; 432,433） 43）源极 - 漏极区域（422,423,432,433）所在的区域。第一（“N BAR”）掺杂区域（64,64'）与Pwell（42）中的P阱（42）形成PN结（512），与Pwell（42）中的源极/漏极区域（423）间隔开，并且第二（“P BAR”）掺杂区域（55,55'）与N阱（43）中的源极/漏极区域（433）间隔开，形成具有N阱（43）的PN结（513）。另外的NP结（511）位于N BAR（64）和P BAR（65）区之间。 N BAR（64）和P BAR（65）区域优选地通过低电阻金属导体（62）欧姆耦合，并且否则相对于器件或电路参考电位（例如，Vss，Vdd）浮置。

60. 发明授权

US07211477B2 High voltage field effect device and method 有权
公开(公告)号：US07211477B2
公开(公告)日：2007-05-01
申请号：US11124469
申请日：2005-05-06
申请人： Edouard D. de Frésart , Richard J. De Souza , Xin Lin , Jennifer H. Morrison , Patrice M. Parris , Moaniss Zitouni
发明人： Edouard D. de Frésart , Richard J. De Souza , Xin Lin , Jennifer H. Morrison , Patrice M. Parris , Moaniss Zitouni
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/0847 , H01L29/7833 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92′) serially located between the channel (90) and the source (70, 70′) or drain (76, 76′). A buried region (96, 96′) of the same conductivity type as the drift space (92, 92′) and the source (70, 70′) or drain (76, 76′) is provided below the drift space (92, 92′), separated therefrom in depth by a narrow gap (94, 94′) and ohmically coupled to the source (70, 70′) or drain (76, 76′). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94′). As the S-D voltage (Vo) and current (109, Io) increase, this difference (Vt) induces high field conduction between the drift space (92, 92′) and the buried region (96, 96′) and diverts part (112, It) of the S-D current (109, Io) through the buried region (96, 96′) and away from the near surface portions of the drift space (92, 92′) where breakdown generally occurs. Thus, BVdss is increased.

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