专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07700996B2 Tunable antifuse elements 有权
标题翻译：可调谐反熔丝元件
公开(公告)号：US07700996B2
公开(公告)日：2010-04-20
申请号：US12361944
申请日：2009-01-29
申请人： Patrice M. Parris , Weize Chen , John M. McKenna , Jennifer H. Morrison , Moaniss Zitouni , Richard J. De Souza
发明人： Patrice M. Parris , Weize Chen , John M. McKenna , Jennifer H. Morrison , Moaniss Zitouni , Richard J. De Souza
IPC分类号： H01L29/94
CPC分类号： H01L27/112 , H01L23/5252 , H01L27/11206 , H01L2924/0002 , Y10S438/981 , H01L2924/00
摘要： A tunable antifuse element (102, 202, 204, 504, 952) includes a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) includes a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a rupture region (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.
摘要翻译：可调谐反熔断元件（102,202,204,504,952）包括具有形成在表面中的有源区域（106）的基板材料（101），栅电极（104），其至少部分位于有源区域（106）和设置在栅电极（104）和有源区（106）之间的电介质层（110）。电介质层（110）包括可调阶梯结构（127）。在操作期间，施加在栅极电极（104）和有源区域（106）之间的电压产生穿过电介质层（110）的电流路径以及在破裂区域（130）中电介质层（110）的破裂。电介质层（110）可以通过改变阶梯层厚度和层的几何形状来调节。

2. 发明申请

US20090127587A1 TUNABLE ANTIFUSE ELEMENTS 有权
标题翻译：可避免的元素
公开(公告)号：US20090127587A1
公开(公告)日：2009-05-21
申请号：US12361944
申请日：2009-01-29
申请人： Patrice M. Parris , Weize Chen , John M. McKenna , Jennifer H. Morrison , Moaniss Zitouni , Richard J. De Souza
发明人： Patrice M. Parris , Weize Chen , John M. McKenna , Jennifer H. Morrison , Moaniss Zitouni , Richard J. De Souza
IPC分类号： H01L29/78 , H01L29/86 , H01L25/07
CPC分类号： H01L27/112 , H01L23/5252 , H01L27/11206 , H01L2924/0002 , Y10S438/981 , H01L2924/00
摘要： A tunable antifuse element (102, 202, 204, 504, 952) includes a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) includes a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a rupture region (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.
摘要翻译：可调谐反熔断元件（102,202,204,504,952）包括具有形成在表面中的有源区域（106）的基板材料（101），栅电极（104），其至少部分位于有源区域（106）和设置在栅电极（104）和有源区（106）之间的电介质层（110）。电介质层（110）包括可调阶梯结构（127）。在操作期间，施加在栅极电极（104）和有源区域（106）之间的电压产生穿过电介质层（110）的电流路径以及在破裂区域（130）中电介质层（110）的破裂。电介质层（110）可以通过改变阶梯层厚度和层的几何形状来调节。

3. 发明授权

US07528015B2 Tunable antifuse element and method of manufacture 有权
标题翻译：可调谐反熔丝元件及其制造方法
公开(公告)号：US07528015B2
公开(公告)日：2009-05-05
申请号：US11169962
申请日：2005-06-28
申请人： Patrice M. Parris , Weize Chen , John M. McKenna , Jennifer H. Morrison , Moaniss Zitouni , Richard J. De Souza
发明人： Patrice M. Parris , Weize Chen , John M. McKenna , Jennifer H. Morrison , Moaniss Zitouni , Richard J. De Souza
IPC分类号： H01L21/82 , H01L21/44 , H01L21/31
CPC分类号： H01L27/112 , H01L23/5252 , H01L27/11206 , H01L2924/0002 , Y10S438/981 , H01L2924/00
摘要： A tunable antifuse element (102, 202, 204, 504, 952) and method of fabricating the tunable antifuse element, including a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) including the fabrication of one of a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a plurality of rupture regions (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.
摘要翻译：一种可调谐反熔断元件（102,202,204,504,952）和制造可调谐反熔丝元件的方法，包括在表面上形成有源区（106）的基片材料（101），具有位于有源区域（106）上方的至少一部分，和设置在栅电极（104）和有源区域（106）之间的电介质层（110）。介电层（110）包括制造可调阶梯结构（127）之一。在操作期间，施加在栅极电极（104）和有源区域（106）之间的电压产生穿过介电层（110）的电流路径，并且多个断裂区域（130）中的电介质层（110）的破裂，。电介质层（110）可以通过改变阶梯层厚度和层的几何形状来调节。

4. 发明申请

US20110261500A1 BACK END OF LINE METAL-TO-METAL CAPACITOR STRUCTURES AND RELATED FABRICATION METHODS 审中-公开
标题翻译：金属 - 金属电容器结构的背面和相关制造方法
公开(公告)号：US20110261500A1
公开(公告)日：2011-10-27
申请号：US12765575
申请日：2010-04-22
申请人： Patrice M. Parris , Richard J. De Souza , Weize Chen , Moaniss Zitouni
发明人： Patrice M. Parris , Richard J. De Souza , Weize Chen , Moaniss Zitouni
IPC分类号： H01G4/00 , B05D5/12
CPC分类号： H01G4/33 , H01G4/232 , H01L23/5223 , H01L28/86 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： Apparatus and related fabrication methods are provided for capacitor structures. One embodiment of a capacitor structure comprises a plurality of consecutive metal layers and another metal layer. Each via layer of a plurality of via layers is interposed between metal layers of the plurality of metal layers. The plurality of metal layers and the plurality of via layers are cooperatively configured to provide a first plurality of vertical conductive structures corresponding to a first electrode and a second plurality of vertical conductive structures corresponding to a second electrode. The plurality of consecutive metal layers form a plurality of vertically-aligned regions and provide intralayer electrical interconnections among the first plurality of vertical conductive structures. The first metal layer provides an intralayer electrical interconnection among the second plurality of vertical conductive structures, wherein each vertically-aligned region has a vertical conductive structure of the second plurality of vertical conductive structures disposed therein.
摘要翻译：为电容器结构提供了装置和相关的制造方法。电容器结构的一个实施例包括多个连续的金属层和另一个金属层。多个通孔层的每个通孔层插入在多个金属层的金属层之间。多个金属层和多个通孔层协作地构造成提供对应于对应于第二电极的第一电极和第二多个垂直导电结构的第一多个垂直导电结构。多个连续的金属层形成多个垂直排列的区域，并且在第一多个垂直导电结构之间提供层间电互连。第一金属层在第二多个垂直导电结构之间提供内层电互连，其中每个垂直对齐区域具有设置在其中的第二多个垂直导电结构的垂直导电结构。

5. 发明授权

US07211477B2 High voltage field effect device and method 有权
公开(公告)号：US07211477B2
公开(公告)日：2007-05-01
申请号：US11124469
申请日：2005-05-06
申请人： Edouard D. de Frésart , Richard J. De Souza , Xin Lin , Jennifer H. Morrison , Patrice M. Parris , Moaniss Zitouni
发明人： Edouard D. de Frésart , Richard J. De Souza , Xin Lin , Jennifer H. Morrison , Patrice M. Parris , Moaniss Zitouni
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/0847 , H01L29/7833 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92′) serially located between the channel (90) and the source (70, 70′) or drain (76, 76′). A buried region (96, 96′) of the same conductivity type as the drift space (92, 92′) and the source (70, 70′) or drain (76, 76′) is provided below the drift space (92, 92′), separated therefrom in depth by a narrow gap (94, 94′) and ohmically coupled to the source (70, 70′) or drain (76, 76′). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94′). As the S-D voltage (Vo) and current (109, Io) increase, this difference (Vt) induces high field conduction between the drift space (92, 92′) and the buried region (96, 96′) and diverts part (112, It) of the S-D current (109, Io) through the buried region (96, 96′) and away from the near surface portions of the drift space (92, 92′) where breakdown generally occurs. Thus, BVdss is increased.

6. 发明申请

US20150316503A1 Differential Pair Sensing Circuit Structures 有权
标题翻译：差分传感电路结构
公开(公告)号：US20150316503A1
公开(公告)日：2015-11-05
申请号：US14265622
申请日：2014-04-30
申请人： Md M. Hoque , Patrice M. Parris , Weize Chen , Richard J. De Souza
发明人： Md M. Hoque , Patrice M. Parris , Weize Chen , Richard J. De Souza
IPC分类号： G01N27/414 , H01L29/78 , H01L29/66
CPC分类号： G01N27/4148 , H01L21/28282 , H01L27/11531 , H01L29/66 , H01L29/66409 , H01L29/78 , H01L29/788
摘要： A differential pair sensing circuit (300) includes control gates (306, 316) for separately programming a reference transistor (350) and a chemically-sensitive transistor (351) to a desired threshold voltage Vt to eliminate the mismatch between the transistors in order to increase the sensitivity and/or accuracy of the sensing circuit without increasing the circuit size.
摘要翻译：差分对检测电路（300）包括用于将参考晶体管（350）和化学敏感晶体管（351）单独编程为期望阈值电压Vt的控制栅极（306,316），以消除晶体管之间的失配，以便提高感测电路的灵敏度和/或精度，而不增加电路尺寸。

7. 发明申请

US20130270606A1 Semiconductor Device with Integrated Breakdown Protection 有权
标题翻译：具有集成故障保护的半导体器件
公开(公告)号：US20130270606A1
公开(公告)日：2013-10-17
申请号：US13448994
申请日：2012-04-17
申请人： Weize Chen , Hubert M. Bode , Richard J. De Souza , Patrice M. Parris
发明人： Weize Chen , Hubert M. Bode , Richard J. De Souza , Patrice M. Parris
IPC分类号： H01L29/06 , H01L21/336 , H01L29/78
CPC分类号： H01L29/7823 , H01L21/2253 , H01L29/0626 , H01L29/0653 , H01L29/0865 , H01L29/0882 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/66659 , H01L29/66681 , H01L29/7824 , H01L29/7835
摘要： A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. The device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path.
摘要翻译：一种器件包括具有第一导电类型的半导体衬底，半导体衬底中的器件隔离区，限定有源区，并具有第二导电类型，有源区中的体区，并具有第一导电类型，漏极区域，并且与身体区域间隔开以限定器件的导电路径，漏极区域具有第二导电类型。器件隔离区域和体区域彼此间隔开以建立低于导通路径中的第二击穿电压的第一击穿电压。

8. 发明授权

US08344443B2 Single poly NVM devices and arrays 有权
标题翻译：单一的NV NV设备和阵列
公开(公告)号：US08344443B2
公开(公告)日：2013-01-01
申请号：US12109736
申请日：2008-04-25
申请人： Weize Chen , Richard J. De Souza , Xin Lin , Patrice M. Parris
发明人： Weize Chen , Richard J. De Souza , Xin Lin , Patrice M. Parris
IPC分类号： H01L29/788 , H01L27/115 , H01L21/8247
CPC分类号： H01L29/7881 , G11C16/10 , H01L27/11519 , H01L27/11521 , H01L29/42324
摘要： A single-poly non-volatile memory includes a PMOS select transistor (210) formed with a select gate (212), and P+ source and drain regions (211, 213) formed in a shared n-well region (240), a serially connected PMOS floating gate transistor (220) formed with part of a p-type floating gate layer (222) and P+ source and drain regions (221, 223) formed in the shared n-well region (240), and a coupling capacitor (230) formed over a p-well region (250) and connected to the PMOS floating gate transistor (220), where the coupling capacitor (230) includes a first capacitor plate formed with a second part of the p-type floating gate layer (222) and an underlying portion of the p-well region (250).
摘要翻译：单多晶非易失性存储器包括形成有选择栅极（212）的PMOS选择晶体管（210），以及形成在共享的n阱区域（240）中的P +源区和漏区（211,213）形成有形成在共用n阱区域（240）中的p型浮栅（222）和P +源区和漏区（221,223）的一部分的连接PMOS浮栅晶体管（220）和耦合电容器 230），其形成在p阱区（250）上并连接到PMOS浮栅晶体管（220），其中耦合电容器（230）包括形成有p型浮栅的第二部分的第一电容器板（ 222）和p阱区（250）的下层部分。

9. 发明授权

US09236472B2 Semiconductor device with integrated breakdown protection 有权
标题翻译：具有集成故障保护的半导体器件
公开(公告)号：US09236472B2
公开(公告)日：2016-01-12
申请号：US13448994
申请日：2012-04-17
申请人： Weize Chen , Hubert M. Bode , Richard J. De Souza , Patrice M. Parris
发明人： Weize Chen , Hubert M. Bode , Richard J. De Souza , Patrice M. Parris
IPC分类号： H01L29/78 , H01L29/66 , H01L29/06 , H01L29/10
CPC分类号： H01L29/7823 , H01L21/2253 , H01L29/0626 , H01L29/0653 , H01L29/0865 , H01L29/0882 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/66659 , H01L29/66681 , H01L29/7824 , H01L29/7835
摘要： A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. The device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path.
摘要翻译：一种器件包括具有第一导电类型的半导体衬底，半导体衬底中的器件隔离区，限定有源区，并具有第二导电类型，有源区中的体区，并具有第一导电类型，漏极区域，并且与身体区域间隔开以限定器件的导电路径，漏极区域具有第二导电类型。器件隔离区域和体区域彼此间隔开以建立低于导通路径中的第二击穿电压的第一击穿电压。

10. 发明授权

US09024380B2 Semiconductor device with floating RESURF region 有权
标题翻译：具有浮动RESURF区域的半导体器件
公开(公告)号：US09024380B2
公开(公告)日：2015-05-05
申请号：US13529589
申请日：2012-06-21
申请人： Weize Chen , Richard J. De Souza , Patrice M. Parris
发明人： Weize Chen , Richard J. De Souza , Patrice M. Parris
IPC分类号： H01L29/66 , H01L29/06 , H01L29/78
CPC分类号： H01L29/0692 , H01L29/0634 , H01L29/0653 , H01L29/66659 , H01L29/7835
摘要： A device includes a semiconductor substrate, a body region in the semiconductor substrate, having a first conductivity type, and including a channel region through which charge carriers flow, a drain region in the semiconductor substrate, having a second conductivity type, and spaced from the body region along a first lateral dimension, a drift region in the semiconductor substrate, having the second conductivity type, and electrically coupling the drain region to the channel region, and a plurality of floating reduced surface field (RESURF) regions in the semiconductor substrate adjacent the drift region, having the first conductivity type, and around which the charge carriers drift through the drift region under an electric field arising from a voltage applied to the drain region. Adjacent floating RESURF regions of the plurality of floating RESURF regions are spaced from one another along a second lateral dimension of the device by a respective gap.
摘要翻译：一种器件包括半导体衬底，半导体衬底中的主体区域，具有第一导电类型，并且包括电荷载流子流过的沟道区域，半导体衬底中的漏极区域，具有第二导电类型，并与第二导电类型间隔开沿着第一横向尺寸的主体区域，具有第二导电类型的半导体衬底中的漂移区域，以及将漏极区域电耦合到沟道区域，以及在半导体衬底相邻的多个浮动缩小表面场（RESURF）区域具有第一导电类型的漂移区域，并且电荷载流子在由施加到漏极区域的电压产生的电场下漂移穿过漂移区域。多个浮动RESURF区域的相邻的浮动RESURF区域沿设备的第二横向尺寸彼此间隔开。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式