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    • 53. 发明授权
    • Spray distribution measuring device and measuring method
    • 喷雾分布测量装置及测量方法
    • US6053037A
    • 2000-04-25
    • US141111
    • 1998-08-27
    • Shinji KojimaOsamu Matsumoto
    • Shinji KojimaOsamu Matsumoto
    • F02M61/18B05B15/00F02M65/00G01F23/16G01M15/00
    • B05B15/00F02M65/00G01F23/162
    • A spray distribution measuring device comprises a chamber 4 having a spray nozzle 1 as a measurement object at the top; a saucer 3 arranged below the spray nozzle within the chamber 4 and partitioned into a plurality of regions each having a prescribed area; measuring tubes 6 each installed substantially vertically from each region of the saucer 3 and having a prescribed sectional area, the upper end of each of which opens into the bottom of each region of the saucer; pressure sensors 7 each installed at the lower end of each of the measuring tubes to measure the head pressure of each measuring tube; and a controller 10 for computing a difference between the pressure applied to the pressure sensor and an initial pressure, and measures the spray distribution on the basis of a difference between the head pressure of the a test solution accumulated in each measuring tube by spraying and the initial pressure before the spraying.
    • 喷雾分配​​测量装置包括:在顶部具有作为测量对象的喷嘴1的腔室4; 托盘3,其布置在腔室4内的喷雾喷嘴下方,并分隔成多个具有规定面积的区域; 测量管6各自基本垂直地安装在托盘3的每个区域上并且具有规定的截面积,每个开口的上端通向托盘的每个区域的底部; 每个测量管的下端安装有压力传感器7,以测量每个测量管的头部压力; 以及控制器10,用于计算施加到压力传感器的压力与初始压力之间的差异,并且基于通过喷射在每个测量管中累积的测试溶液的头部压力与第一喷射量之间的差异来测量喷雾分布 喷涂前的初始压力。
    • 55. 发明授权
    • Voltage comparator and pipeline type A/D converter
    • 电压比较器和流水线型A / D转换器
    • US5696511A
    • 1997-12-09
    • US738585
    • 1996-10-29
    • Osamu MatsumotoToshio Kumamoto
    • Osamu MatsumotoToshio Kumamoto
    • H03M1/10H03F3/45H03M1/06H03M1/12H03M1/14H03M1/16H03M1/42
    • H03M1/0695H03M1/167
    • In a pipeline type A/D converter, a sample/hold.cndot.subtracter circuit of an A/D converter block of a first stage samples an analog voltage and outputs an offset voltage at a first phase, and subtracts an output voltage of an A/D converter from the sampled analog voltage in a second phase. An A/D converter of an A/D converter block of a succeeding stage subtracts the output voltage of the sample/hold.cndot.subtracter circuit of the first phase from the output voltage of the sample hold.cndot.subtracter circuit of the second phase, and converts the subtracted result into a digital code. The influence of an offset of a differential amplifier included in the sample/hold.cndot.subtracter circuit is removed so that A/D conversion of high accuracy is allowed.
    • 在流水线型A / D转换器中,第一级的A / D转换器模块的采样/保持减法器电路对模拟电压进行采样,并在第一阶段输出偏移电压,并且减去A / D转换器从第二阶段的采样模拟电压。 后级的A / D转换器模块的A / D转换器从第二相的采样保持电路的输出电压中减去第一相的采样/保持电路的输出电压,并将其转换 减去结果成数字代码。 除去包含在采样/保持抑制电路中的差分放大器的偏移的影响,使得允许高精度的A / D转换。
    • 56. 发明授权
    • Two input-two output differential latch circuit
    • 两路输入二输出差分锁存电路
    • US5625308A
    • 1997-04-29
    • US557556
    • 1995-11-14
    • Osamu MatsumotoTakahiro MikiToshio Kumamoto
    • Osamu MatsumotoTakahiro MikiToshio Kumamoto
    • H03M1/34H03K3/0233H03K3/356H03K3/289
    • H03K3/35606H03K3/356034H03K3/35613
    • A high-performance differential latch circuit which includes a differential amplifier circuit comprised of an NMOS transistor (27) serving as a constant current source, PMOS transistors (3, 4) and NMOS transistors (23,24), a latch circuit comprised of NMOS transistors (25, 26), and a switch circuit comprised of NMOS transistors (21,22,28) for alternately operating the differential amplifying function and latch function, the transistor (27) serving as the constant current source having a drain terminal directly connected to the transistors (23,24) and a source terminal directly connected to a ground voltage (2), whereby the differential latch circuit differentially amplifies the signals without the loss of the constant current source function during the differential amplification.
    • 一种高性能差分锁存电路,包括由用作恒流源的NMOS晶体管(27),PMOS晶体管(3,4)和NMOS晶体管(23,24)组成的差分放大器电路,由NMOS 晶体管(25,26)以及由NMOS晶体管(21,22,28)组成的用于交替操作差分放大功能和锁存功能的开关电路,用作恒流源的晶体管(27)具有直接连接的漏极端子 到晶体管(23,24)和直接连接到接地电压(2)的源极端子,由此差分锁存电路在差分放大期间不损失恒定电流源功能而差分放大信号。
    • 59. 发明授权
    • Potential detecting circuit
    • 电位检测电路
    • US5208488A
    • 1993-05-04
    • US937452
    • 1992-08-31
    • Akira TakibaOsamu MatsumotoYukihiro Saeki
    • Akira TakibaOsamu MatsumotoYukihiro Saeki
    • G05F3/24G11C5/14G11C16/12G11C16/30
    • G11C5/143G05F3/24G11C16/12G11C16/30
    • A potential detecting circuit comprises a first MOS transistor of a first conductivity type whose drain receives an input potential that is equal to or lower, in absolute value, than a second potential whose absolute value is higher than that of a first potential, a second MOS transistor of a second conductivity type whose source is connected to the source of the first transistor and gate receives the first potential, a third MOS transistor of the first conductivity type whose source is connected to the second MOS transistor, source receives a reference potential whose absolute value is lower than that of the first potential, and gate receives the first potential, a detecting potential control block for applying to the first MOS transistor a potential varying in accordance with the input potential, and a potential detect output terminal for providing a detected potential, the potential detect output terminal being a junction between the drains of the second and third MOS transistors.
    • 电位检测电路包括第一导电类型的第一MOS晶体管,其漏极接收绝对值比绝对值高于第一电位的第二电位的绝对值等于或等于的输入电位,第二MOS 第二导电类型的晶体管,其源极连接到第一晶体管和栅极的源极接收第一电位,源极连接到第二MOS晶体管的第一导电类型的第三MOS晶体管接收参考电位,绝对值 值低于第一电位,栅极接收第一电位;检测电位控制块,用于向第一MOS晶体管施加根据输入电位变化的电位;以及电位检测输出端,用于提供检测电位 电位检测输出端子是第二和第三MOS晶体管的漏极之间的结点。