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51. 发明申请

US20070012967A1 Thin film transistor array panel and fabrication 有权
标题翻译：薄膜晶体管阵列和制造
公开(公告)号：US20070012967A1
公开(公告)日：2007-01-18
申请号：US11486330
申请日：2006-07-12
申请人： Sang-Gab Kim , Woo-Geun Lee , Shi-Yul Kim , Jin-Ho Ju , Jang-Soo Kim , Sang-Woo Whangbo , Min-Seok Oh , Hye-Young Ryu , Hong-Kee Chin
发明人： Sang-Gab Kim , Woo-Geun Lee , Shi-Yul Kim , Jin-Ho Ju , Jang-Soo Kim , Sang-Woo Whangbo , Min-Seok Oh , Hye-Young Ryu , Hong-Kee Chin
IPC分类号： H01L31/113
CPC分类号： H01L27/124 , G02F2001/13629 , H01L29/458
摘要： The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.
摘要翻译：本发明提供一种薄膜晶体管阵列面板的制造方法，其包括在基板上形成栅极线; 在栅极线上形成栅极绝缘层，半导体层和欧姆接触; 形成包括Mo的第一导电膜，包括Al的第二导电膜和在欧姆接触上包含Mo的第三导电膜; 在所述第三导电膜上形成第一光致抗蚀剂图案; 使用第一光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜，欧姆接触和半导体层; 将第一光致抗蚀剂图案去除预定厚度以形成第二光致抗蚀剂图案; 使用第二光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜以暴露欧姆接触的一部分; 并使用含Cl气体和含F气体蚀刻暴露的欧姆接触。

52. 发明申请

US20060192906A1 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20060192906A1
公开(公告)日：2006-08-31
申请号：US11356853
申请日：2006-02-17
申请人： Hye-Young Ryu , Jang-Soo Kim , Sang-Gab Kim , Hong-Kee Chin , Min-Seok Oh , Hee-Hwan Choe , Shi-Yul Kim
发明人： Hye-Young Ryu , Jang-Soo Kim , Sang-Gab Kim , Hong-Kee Chin , Min-Seok Oh , Hee-Hwan Choe , Shi-Yul Kim
IPC分类号： G02F1/136
CPC分类号： G02F1/136286 , G02F1/133345 , G02F1/1362 , G02F2001/136222 , G02F2202/02
摘要： A thin film transistor array panel is provided, which includes a gate line, a data line intersecting the gate line, a storage electrode apart from the gate and data lines, a thin film transistor connected to the gate and data lines and having a drain electrode, a pixel electrode connected to the drain electrode, a first insulating layer over the thin film transistor and disposed under the pixel electrode, and a second insulating layer disposed on the first insulating layer and having an opening exposing the first insulating layer on the storage electrode.
摘要翻译：提供薄膜晶体管阵列面板，其包括栅极线，与栅极线相交的数据线，与栅极和数据线分开的存储电极，连接到栅极和数据线并具有漏极的薄膜晶体管连接到漏电极的像素电极，薄膜晶体管上的第一绝缘层，并且设置在像素电极下方;第二绝缘层，设置在第一绝缘层上，并且具有使存储电极上的第一绝缘层露出的开口。

53. 发明申请

US20060131581A1 Thin film transistor array panel and method for manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20060131581A1
公开(公告)日：2006-06-22
申请号：US11255801
申请日：2005-10-21
申请人： Sang-Gab Kim , Min-Seok Oh , Hong-Kee Chin , Jeong-Min Park , Shi-Yul Kim , Hee-Hwan Choe
发明人： Sang-Gab Kim , Min-Seok Oh , Hong-Kee Chin , Jeong-Min Park , Shi-Yul Kim , Hee-Hwan Choe
IPC分类号： H01L29/04
CPC分类号： H01L29/458 , G02F2001/136236 , H01L27/124 , H01L27/1288
摘要： A method for manufacturing a TFT array panel including forming a gate line having a gate electrode on a insulating layer, a gate insulating layer on the gate line, a semiconductor on the gate insulating layer, an ohmic contact on the semiconductor, a data line having a source electrode and a drain electrode apart form the source electrode on the ohmic contact, a passivation layer having a contact hole to expose the drain electrode, and a pixel electrode connected to the drain electrode through the contact hole. The drain electrode and the source electrode are formed by a photolithography using a negative photoresist pattern. The negative photoresist pattern includes a first portion having a first thickness corresponding to a channel area, a second portion having a second thickness corresponding to a data line area, and a third portion having a third thickness corresponding to another area.
摘要翻译：一种TFT阵列板的制造方法，包括在绝缘层上形成具有栅电极的栅极线，栅极线上的栅极绝缘层，栅极绝缘层上的半导体，半导体上的欧姆接触，数据线，源电极和漏电极分开形成欧姆接触上的源电极，具有露出漏电极的接触孔的钝化层和通过接触孔连接到漏电极的像素电极。漏电极和源电极通过使用负光致抗蚀剂图案的光刻形成。负型光致抗蚀剂图案包括具有对应于沟道区域的第一厚度的第一部分，具有对应于数据线区域的第二厚度的第二部分和具有对应于另一区域的第三厚度的第三部分。

54. 发明授权

US07876412B2 Thin film transistor array panel and method for manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07876412B2
公开(公告)日：2011-01-25
申请号：US12704503
申请日：2010-02-11
申请人： Sang-Gab Kim , Min-Seok Oh , Hong-Kee Chin , Jeong-Min Park , Shi-Yul Kim , Hee-Hwan Choe
发明人： Sang-Gab Kim , Min-Seok Oh , Hong-Kee Chin , Jeong-Min Park , Shi-Yul Kim , Hee-Hwan Choe
IPC分类号： G02F1/1343 , G02F1/1337
CPC分类号： H01L29/458 , G02F2001/136236 , H01L27/124 , H01L27/1288
摘要： A method for manufacturing a TFT array panel including forming a gate line having a gate electrode on a insulating layer, a gate insulating layer on the gate line, a semiconductor on the gate insulating layer, an ohmic contact on the semiconductor, a data line having a source electrode and a drain electrode apart form the source electrode on the ohmic contact, a passivation layer having a contact hole to expose the drain electrode, and a pixel electrode connected to the drain electrode through the contact hole. The drain electrode and the source electrode are formed by a photolithography using a negative photoresist pattern. The negative photoresist pattern includes a first portion having a first thickness corresponding to a channel area, a second portion having a second thickness corresponding to a data line area, and a third portion having a third thickness corresponding to another area.
摘要翻译：一种TFT阵列板的制造方法，包括在绝缘层上形成具有栅电极的栅极线，栅极线上的栅极绝缘层，栅极绝缘层上的半导体，半导体上的欧姆接触，数据线，源电极和漏电极分开形成欧姆接触上的源电极，具有露出漏电极的接触孔的钝化层和通过接触孔连接到漏电极的像素电极。漏电极和源电极通过使用负光致抗蚀剂图案的光刻形成。负型光致抗蚀剂图案包括具有对应于沟道区域的第一厚度的第一部分，具有对应于数据线区域的第二厚度的第二部分和具有对应于另一区域的第三厚度的第三部分。

55. 发明授权

US07794612B2 Method of manufacturing a display substrate 有权
标题翻译：制造显示基板的方法
公开(公告)号：US07794612B2
公开(公告)日：2010-09-14
申请号：US11698483
申请日：2007-01-25
申请人： Hong-Kee Chin , Sang-Gab Kim , Min-Seok Oh
发明人： Hong-Kee Chin , Sang-Gab Kim , Min-Seok Oh
IPC分类号： B29D11/00
CPC分类号： H01L27/1288 , G02F1/136204 , H01L27/1244
摘要： A method of manufacturing a display substrate includes forming a first metallic pattern including gate and storage conductors and a gate electrode of a switching device on a base substrate, forming a gate insulation layer, forming a second metallic pattern and a channel portion including a source line, source and drain electrodes of the switching device, forming a passivation layer and a photoresist film on the second metallic pattern, patterning the photoresist film to form a first pattern portion corresponding to the gate and source conductors and the switching device, and a second pattern portion formed on the storage line, etching the passivation layer and the gate insulation layer, and forming a pixel electrode using the first pattern portion. Therefore, excessive etching of the stepped portion may be prevented, so that a short-circuit defect between a metallic pattern and a pixel electrode may be prevented.
摘要翻译：一种制造显示基板的方法包括在基底基板上形成包括栅极和存储导体的第一金属图案和开关器件的栅电极，形成栅极绝缘层，形成第二金属图案和包括源极线的沟道部分开关器件的源极和漏极，在第二金属图案上形成钝化层和光致抗蚀剂膜，图案化光致抗蚀剂膜以形成对应于栅极和源极导体和开关器件的第一图案部分，以及第二图案形成在存储线上的部分，蚀刻钝化层和栅极绝缘层，以及使用第一图案部分形成像素电极。因此，可以防止阶梯部分的过度蚀刻，从而可以防止金属图案和像素电极之间的短路缺陷。

56. 发明申请

US20090017574A1 THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME, DISPLAY APPARATUS HAVING THE SAME AND METHOD OF MANUFACTURING THE DISPLAY APPARATUS 失效
标题翻译：薄膜晶体管，其制造方法，具有该方法的显示装置和制造显示装置的方法
公开(公告)号：US20090017574A1
公开(公告)日：2009-01-15
申请号：US12146763
申请日：2008-06-26
申请人： Sang-Gab Kim , Shi-Yul Kim , Hong-Sick Park , Hee-Hwan Choe , Hong-Kee Chin , Min-Seok Oh
发明人： Sang-Gab Kim , Shi-Yul Kim , Hong-Sick Park , Hee-Hwan Choe , Hong-Kee Chin , Min-Seok Oh
IPC分类号： H01L21/336 , H01L33/00
CPC分类号： H01L29/66765 , G02F1/1368 , H01L27/12 , H01L27/124 , H01L29/458
摘要： A thin film transistor includes a gate electrode on a substrate, a gate insulating layer on the substrate, a channel pattern, a source electrode and a drain electrode. The channel pattern includes a semiconductor pattern formed on the gate electrode and overlaying the gate electrode as well as first and second conductive adhesive patterns formed on the semiconductor pattern and spaced apart from each other. The source electrode includes a first barrier pattern, a source pattern and a first capping pattern sequentially formed on the first conductive adhesive pattern. The drain electrode includes a second barrier pattern, a drain pattern and a second capping pattern sequentially formed on the second conductive adhesive pattern. Etched portions of the first and second conductive adhesive patterns have a substantially vertical profile to prevent the exposure of the source and drain electrodes, thereby improving the characteristics of the thin film transistor.
摘要翻译：薄膜晶体管包括衬底上的栅电极，衬底上的栅极绝缘层，沟道图案，源电极和漏电极。沟道图案包括形成在栅电极上并覆盖栅电极的半导体图案以及形成在半导体图案上并彼此间隔开的第一和第二导电粘合剂图案。源电极包括顺序地形成在第一导电粘合剂图案上的第一阻挡图案，源图案和第一封盖图案。漏电极包括顺序地形成在第二导电粘合剂图案上的第二阻挡图案，漏极图案和第二封盖图案。第一和第二导电粘合剂图案的蚀刻部分具有基本垂直的轮廓，以防止源极和漏极的暴露，从而改善薄膜晶体管的特性。

57. 发明申请

US20070170145A1 Method of manufacturing a display substrate 有权
标题翻译：制造显示基板的方法
公开(公告)号：US20070170145A1
公开(公告)日：2007-07-26
申请号：US11698483
申请日：2007-01-25
申请人： Hong-Kee Chin , Sang-Gab Kim , Min-Seok Oh
发明人： Hong-Kee Chin , Sang-Gab Kim , Min-Seok Oh
IPC分类号： B29D11/00
CPC分类号： H01L27/1288 , G02F1/136204 , H01L27/1244
摘要： A method of manufacturing a display substrate includes forming a first metallic pattern including gate and storage conductors and a gate electrode of a switching device on a base substrate, forming a gate insulation layer, forming a second metallic pattern and a channel portion including a source line, source and drain electrodes of the switching device, forming a passivation layer and a photoresist film on the second metallic pattern, patterning the photoresist film to form a first pattern portion corresponding to the gate and source conductors and the switching device, and a second pattern portion formed on the storage line, etching the passivation layer and the gate insulation layer, and forming a pixel electrode using the first pattern portion. Therefore, excessive etching of the stepped portion may be prevented, so that a short-circuit defect between a metallic pattern and a pixel electrode may be prevented.
摘要翻译：一种制造显示基板的方法包括在基底基板上形成包括栅极和存储导体的第一金属图案和开关器件的栅电极，形成栅极绝缘层，形成第二金属图案和包括源极线的沟道部分开关器件的源极和漏极，在第二金属图案上形成钝化层和光致抗蚀剂膜，图案化光致抗蚀剂膜以形成对应于栅极和源极导体和开关器件的第一图案部分，以及第二图案形成在存储线上的部分，蚀刻钝化层和栅极绝缘层，以及使用第一图案部分形成像素电极。因此，可以防止台阶部分的过度蚀刻，从而可以防止金属图案和像素电极之间的短路缺陷。

58. 发明申请

US20070111412A1 Thin film transistor array panel and method of manufacturing the same 审中-公开
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20070111412A1
公开(公告)日：2007-05-17
申请号：US11600481
申请日：2006-11-15
申请人： Min-Seok Oh , Jeong-Min Park , Sang-Gab Kim , Hong-Kee Chin , Chang-Oh Jeong , Hong-Sick Park , Shi-Yul Kim
发明人： Min-Seok Oh , Jeong-Min Park , Sang-Gab Kim , Hong-Kee Chin , Chang-Oh Jeong , Hong-Sick Park , Shi-Yul Kim
IPC分类号： H01L21/84
CPC分类号： H01L21/32139 , H01L21/0273 , H01L27/12 , H01L27/124 , H01L27/1288
摘要： In one embodiment, a thin film transistor array display panel and method of manufacturing the same are provided. A method includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact layer on the gate line; forming a data layer on the ohmic contact layer; forming a photosensitive pattern on the data layer; etching the data layer to form a data line including a source electrode and a drain electrode that is opposite to the source electrode; reflowing the photosensitive pattern to cover side surfaces of the source electrode and the drain electrode; and etching the ohmic contact layer using the reflowed photosensitive pattern as a mask.
摘要翻译：在一个实施例中，提供了薄膜晶体管阵列显示面板及其制造方法。一种方法包括在基板上形成栅极线; 在栅极线上形成栅极绝缘层，半导体层和欧姆接触层; 在欧姆接触层上形成数据层; 在数据层上形成感光图案; 蚀刻数据层以形成包括与源电极相对的源电极和漏电极的数据线; 回流感光图案以覆盖源电极和漏电极的侧表面; 并使用回流感光图案作为掩模蚀刻欧姆接触层。

59. 发明申请

US20060137611A1 Plasma apparatus 审中-公开
标题翻译：等离子体仪器
公开(公告)号：US20060137611A1
公开(公告)日：2006-06-29
申请号：US11298107
申请日：2005-12-09
申请人： Hee-Hwan Choe , Sang-Gab Kim , Min-Seok Oh , Hong-Kee Chin
发明人： Hee-Hwan Choe , Sang-Gab Kim , Min-Seok Oh , Hong-Kee Chin
IPC分类号： C23C16/00 , C23F1/00
CPC分类号： H01J37/321 , H01L21/67069
摘要： The present invention relates to a plasma apparatus comprising a reaction chamber having a reaction space which accommodates a substrate to be treated; a coil located on the outside of the reaction space; a power source applying alternating frequency power on the coil; and a conducting plate located between the coil and the reaction space and generating an induced current from the alternating frequency power applied on the coil. Thus, the present invention provides a plasma apparatus that induces a uniform electric field in an internal gas of the reaction chamber.
摘要翻译：等离子体装置技术领域本发明涉及一种等离子体装置，其包括具有容纳待处理基板的反应空间的反应室; 位于反应空间外侧的线圈; 在所述线圈上施加交流频率功率的电源; 以及位于线圈和反应空间之间的导电板，并且从施加在线圈上的交流频率功率产生感应电流。因此，本发明提供一种等离子体装置，其在反应室的内部气体中引起均匀的电场。

60. 发明授权

US09671637B2 Touch screen substrate and method of manufacturing the same 有权
公开(公告)号：US09671637B2
公开(公告)日：2017-06-06
申请号：US12903688
申请日：2010-10-13
申请人： Yun-Jong Yeo , Hong-Kee Chin
发明人： Yun-Jong Yeo , Hong-Kee Chin
IPC分类号： G06F3/042 , G02F1/1333 , G06F3/041 , H01L27/12
CPC分类号： G02F1/13338 , G06F3/0412 , G06F3/042 , H01L27/12 , H01L27/1214 , Y10T29/49105
摘要： In a touch screen substrate and a method of manufacturing the same, the touch screen substrate includes a base substrate, a light blocking pattern, a first sensing element and a first switching element. The light blocking pattern includes an inorganic layer formed on the base substrate and a light blocking layer formed on the inorganic layer, the light blocking layer transmitting an infrared light and absorbing a visible light. The first sensing element is formed on the light blocking pattern and senses the infrared light. The first switching element is electrically connected to the first sensing element. Thus, an undercut may be prevented from being formed at a lower portion of the light blocking pattern, and an adhesive strength between the light blocking pattern and the base substrate may be enhanced.

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