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51. 发明授权

US5103273A Nonvolatile memory array having cells with two tunnelling windows 失效
标题翻译：具有具有两个隧道窗口的单元的非易失性存储器阵列
公开(公告)号：US5103273A
公开(公告)日：1992-04-07
申请号：US589347
申请日：1990-09-28
申请人： Manzur Gill , Theodore D. Lindgren
发明人： Manzur Gill , Theodore D. Lindgren
IPC分类号： G11C17/00 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115
摘要： A nonvolatile memory cell having separate regions for programming and erasing. The cells are formed in an array at a face of a semiconductor body, each cell including a source that is part of a source-column line and including a drain that is part of a drain-column line. Each cell has first, second and third sub-channels between source and drain. The conductivity of the first sub-channel of each cell is controlled by a field-plate, which is part of a field-plate-column line, positioned over and insulated from the first sub-channel. The conductivity of each of the second sub-channels is controlled by a floating gate formed over and insulated from the second sub-channel. Each floating gate has a first tunnelling window positioned over the adjacent source-column line and has a second tunnelling window positioned over the adjacent drain-column line. Row lines, including control gates, are positioned over and insulated from the floating gates of the cells for reading, programming and erasing the cells. The row lines, including control gates, are also positioned over and insulated from the third sub-channels. The field-plate conductor permits programming of the cells through the first tunnelling window only and erasing of the cells through the second tunnelling window only, or vice versa.
摘要翻译：具有用于编程和擦除的分离区域的非易失性存储单元。电池在半导体本体的表面上以阵列形成，每个电池包括作为源 - 列线的一部分的源，并且包括作为漏 - 列线的一部分的漏极。每个单元在源极和漏极之间具有第一，第二和第三子通道。每个电池单元的第一子通道的电导率由场板控制，该场板是位于第一子通道上并与第一子通道绝缘的场板 - 列 - 列线的一部分。每个第二子通道的电导率由形成在第二子通道上并与第二子通道绝缘的浮动栅极控制。每个浮动栅极具有位于相邻源极列线上方的第一隧道窗口，并且具有位于相邻排列 - 列线上方的第二隧道窗口。包括控制栅极的行线位于单元的浮动栅极上并与其隔离，用于读取，编程和擦除单元。包括控制栅极的行线也位于第三子通道上并与第三子通道绝缘。场板导体仅允许通过第一隧道窗口对单元进行编程，并且仅通过第二隧道窗口擦除单元，反之亦然。

52. 发明授权

US4947222A Electrically programmable and erasable memory cells with field plate conductor defined drain regions 失效
标题翻译：电气可编程和可擦除存储单元，具有定义漏极区域的导体板导体
公开(公告)号：US4947222A
公开(公告)日：1990-08-07
申请号：US385846
申请日：1989-07-26
申请人： Manzur Gill , Sebastiano D'Arrigo
发明人： Manzur Gill , Sebastiano D'Arrigo
IPC分类号： H01L21/8247 , H01L29/788
CPC分类号： H01L27/11517 , H01L29/7883
摘要： First and second EEPROM cells have first and second source regions (28a, 28b) formed in a semiconductor layer (12) to be of a second conductivity type opposite the first conductivity type of the layer and to be spaced apart from each other. A field plate conductor (100) is insulatively disposed adjacent, and defines, an inversion region (102), and further is laterally spaced between the first and second source regions (28a, 28b). The inversion region (102) is inverted from the first conductivity type to the second conductivity type upon application of a predetermined voltage to the field plate conductor (100). First and second channel regions (48a, 48b) are defined between the respective source regions (28a, 28b) and the inversion region (102) and each include floating gate and control gate subchannel regions (60a, 62a, 62b, 60b). First and second floating gate conductors (40a, 40b) are insulatively disposed adjacent respective floating gate subchannel regions (60 a, 60b) to control their conductance. A control gate conductor is insulatively disposed adjacent the control gate subchannel regions (62a, 62b) to control their conductance. In another embodiment, the floating gate conductor (100) is replaced with a pair of field plate conductors (42a, 42b) that control the conductance of respective subchannel regions (64a, 64b). The field plate conductors (42a, 42b) act to self-align a diffused drain region (46) that replaces the inversion region (102).
摘要翻译：第一和第二EEPROM单元具有在半导体层（12）中形成为与第一导电类型相反的第二导电类型并且彼此间隔开的第一和第二源极区（28a，28b）。场平板导体（100）被绝缘地邻近并限定反转区域（102），并且还在第一和第二源极区域（28a，28b）之间横向隔开。当对场板导体（100）施加预定电压时，反转区域（102）从第一导电类型转换为第二导电类型。第一和第二通道区域（48a，48b）被限定在各个源极区域（28a，28b）和反转区域（102）之间，并且各自包括浮动栅极和控制栅极子通道区域（60a，62a，62b，60b）。第一和第二浮栅导体（40a，40b）被绝缘地设置在相邻的浮栅子通道区域（60a，60b）附近，以控制它们的电导。控制栅极导体与控制栅极子通道区域（62a，62b）相邻地间隔地设置以控制它们的电导。在另一个实施例中，浮动栅极导体（100）由控制各个子通道区域（64a，64b）的电导的一对场板导体（42a，42b）代替。场板导体（42a，42b）用于使取代反转区域（102）的扩散漏极区域（46）自对准。

53. 发明授权

US07157304B2 Single level metal memory cell using chalcogenide cladding 有权
公开(公告)号：US07157304B2
公开(公告)日：2007-01-02
申请号：US10838966
申请日：2004-05-05
申请人： Tyler A. Lowrey , Manzur Gill
发明人： Tyler A. Lowrey , Manzur Gill
IPC分类号： H01L21/00
CPC分类号： H01L27/2409 , G11C13/0004 , G11C2213/72 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： An apparatus including a volume of phase change material disposed between a first conductor and a second conductor on a substrate, and a plurality of electrodes coupled to the volume of phase change material and the first conductor. A method including introducing, over a first conductor on a substrate, a plurality of electrodes coupled to the first conductor, introducing a phase change material over the plurality of electrodes and in electrical communication with the plurality of electrodes, and introducing a second conductor over the phase change material and coupled to the phase change material.

54. 发明授权

US06912146B2 Using an MOS select gate for a phase change memory 失效
标题翻译：使用MOS选择栅极进行相变存储器
公开(公告)号：US06912146B2
公开(公告)日：2005-06-28
申请号：US10318705
申请日：2002-12-13
申请人： Manzur Gill , Tyler Lowrey
发明人： Manzur Gill , Tyler Lowrey
IPC分类号： G11C11/34 , G11C16/02 , G11C17/00 , H01L27/115 , H01L47/00
CPC分类号： G11C13/0004 , G11C2013/0071 , G11C2213/79
摘要： An NMOS field effect transistor may be utilized to drive the memory cell of a phase change memory. As a result, the leakage current may be reduced dramatically.
摘要翻译： NMOS场效应晶体管可用于驱动相变存储器的存储单元。结果，泄漏电流可能显着降低。

55. 发明授权

US5570314A EEPROM devices with smaller cell size 失效
标题翻译：具有较小单元尺寸的EEPROM器件
公开(公告)号：US5570314A
公开(公告)日：1996-10-29
申请号：US365208
申请日：1994-12-28
申请人： Manzur Gill
发明人： Manzur Gill
IPC分类号： H01L21/8247 , G11C11/34
CPC分类号： H01L27/11521
摘要： An EEPROM and method for making the same, having precisely shaped field oxide regions and memory cells, to provide improved electrical operating characteristics and increased memory density. A layer of field oxide is grown over an n-type substrate having a p-well and the layer of field oxide is selectively etched to form rows of field oxide. Rows of tunnel oxide are formed between the rows of field oxide. A first layer of polysilicon, or poly-1, is formed over the wafer and a layer of ONO is formed over the poly-1. Using the same mask, the ONO, poly-1, field oxide, and tunnel oxide are stack etched. Bit lines are formed, followed by oxide spacers. A second layer of polysilicon, or poly-2 is formed and selectively etched to form word lines. The exposed ONO and poly-1 are etched using the same mask to form floating gate regions. Subsequent process steps provide word lines to metal dielectric, contacts, metal and passivation.
摘要翻译：一种EEPROM及其制造方法，具有精确成形的场氧化物区域和存储单元，以提供改进的电气操作特性和增加的存储器密度。在具有p阱的n型衬底上生长场氧化物层，并且选择性地蚀刻场氧化物层以形成行场氧化物。隧道氧化物行形成在场氧化物行之间。在晶片上形成第一层多晶硅或多晶硅，并在多晶硅上形成一层ONO。使用相同的掩模，将ONO，poly-1，场氧化物和隧道氧化物进行叠层蚀刻。形成位线，随后形成氧化物间隔物。形成第二层多晶硅或多晶硅，并选择性地蚀刻以形成字线。使用相同的掩模蚀刻暴露的ONO和poly-1以形成浮栅区域。随后的工艺步骤为金属电介质，触点，金属和钝化提供字线。

56. 发明授权

US5521110A Method of making EEPROM devices with smaller cell size 失效
标题翻译：制造具有较小单元尺寸的EEPROM器件的方法
公开(公告)号：US5521110A
公开(公告)日：1996-05-28
申请号：US525286
申请日：1995-09-08
申请人： Manzur Gill
发明人： Manzur Gill
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521
摘要： An EEPROM and method for making the same, having precisely shaped field oxide regions and memory cells, to provide improved electrical operating characteristics and increased memory density. A layer of field oxide is grown over an n-type substrate having a p-well and the layer of field oxide is selectively etched to form rows of field oxide. Rows of tunnel oxide are formed between the rows of field oxide. A first layer of polysilicon, or poly-1, is formed over the wafer and a layer of ONO is formed over the poly-1. Using the same mask, the ONO, poly-1, field oxide, and tunnel oxide are stack etched. Bit lines are formed, followed by oxide spacers. A second layer of polysilicon,or poly-2 is formed and selectively etched to form word lines. The exposed ONO and poly-1 are etched using the same mask to form floating gate regions. Subsequent process steps provide word lines to metal dielectric, contacts, metal and passivation.
摘要翻译：一种EEPROM及其制造方法，具有精确成形的场氧化物区域和存储单元，以提供改进的电气操作特性和增加的存储器密度。在具有p阱的n型衬底上生长场氧化物层，并且选择性地蚀刻场氧化物层以形成行场氧化物。隧道氧化物行形成在场氧化物行之间。在晶片上形成第一层多晶硅或多晶硅，并在多晶硅上形成一层ONO。使用相同的掩模，将ONO，poly-1，场氧化物和隧道氧化物进行叠层蚀刻。形成位线，随后形成氧化物间隔物。形成第二层多晶硅或多晶硅，并选择性地蚀刻以形成字线。使用相同的掩模蚀刻暴露的ONO和poly-1以形成浮栅区域。随后的工艺步骤为金属电介质，触点，金属和钝化提供字线。

57. 发明授权

US5469383A Memory cell array having continuous-strip field-oxide regions 失效
标题翻译：具有连续带状场氧化物区域的存储单元阵列
公开(公告)号：US5469383A
公开(公告)日：1995-11-21
申请号：US265349
申请日：1994-06-24
申请人： Dave J. McElroy , Manzur Gill , Pradeep L. Shah
发明人： Dave J. McElroy , Manzur Gill , Pradeep L. Shah
IPC分类号： H01L21/8247 , H01L27/115 , G11C11/34
CPC分类号： H01L27/11521 , H01L27/115
摘要： A CMOS memory cell array and a method of forming it, which avoids problems caused by field oxide corner-rounding. A moat pattern defines alternating columns of active areas and field oxide regions. A source line pattern defines rows of source lines. Silicon dopant is implanted in areas not covered by the source line pattern to form buried n+ source lines. The field oxide regions are formed in areas not covered by the moat pattern. Subsequent fabrication steps may be in accordance with conventional CMOS fabrication techniques.
摘要翻译：一种CMOS存储单元阵列及其形成方法，其避免了由场氧化物四舍五入引起的问题。护城河模式定义了活动区域和场氧化物区域的交替列。源线模式定义了源行行。将硅掺杂剂注入到未被源极线图案覆盖的区域中以形成埋入的n +源极线。场氧化物区域形成在未被护套图案覆盖的区域中。随后的制造步骤可以与传统的CMOS制造技术相一致。

58. 发明授权

US5306658A Method of making virtual ground memory cell array 失效
标题翻译：制作虚拟接地存储单元阵列的方法
公开(公告)号：US5306658A
公开(公告)日：1994-04-26
申请号：US68472
申请日：1993-05-27
申请人： Manzur Gill
发明人： Manzur Gill
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L21/70
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/105
摘要： A memory cell array for a nonvolatile memory device having single-transistor cells (10). Row lines (15) connect the control gates of each row of cells. Column lines (17) connect the drain regions (11) and source regions (12) of columns of cells, such that pairs of row-adjacent cells share a column line (17). Each shared column line (17) has two junctions for each pair of cells that share the column line. One junction is graded for source regions (12) and the other is abrupt for drain regions (11).
摘要翻译：一种用于具有单晶体管单元（10）的非易失性存储器件的存储单元阵列。行线（15）连接每行单元格的控制门。列线（17）连接单元列的漏极区域（11）和源极区域（12），使得对相邻的行相邻单元格共享列线（17）。每个共享列线（17）对于共享列线的每对单元格具有两个连接点。对于源极区域（12），一个结点被分级，而另一个对于漏极区域（11）是突变的。

59. 发明授权

US5262846A Contact-free floating-gate memory array with silicided buried bitlines and with single-step-defined floating gates 失效
标题翻译：具有硅化掩埋位线和单步定义浮动栅极的非接触式浮栅存储器阵列
公开(公告)号：US5262846A
公开(公告)日：1993-11-16
申请号：US750699
申请日：1991-08-20
申请人： Manzur Gill , Howard L. Tigelaar
发明人： Manzur Gill , Howard L. Tigelaar
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/78 , H01L29/44
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between bitlines is by thick field oxide. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The sides of the floating gates are defined with a single patterning step. The resulting structure is a dense cross-point array of programmable memory cells.
摘要翻译：一个无接触的浮栅非易失性存储单元阵列和具有硅化NSAG位线的工艺，以及埋在相对厚的氧化硅之下的源/漏区。位线具有相对较小的电阻，消除了对具有大量位线触点的并行金属导体的需要。阵列具有相对小的位线电容，并且可以构造成具有相对较小的尺寸。位线之间的隔离是通过厚场氧化物。字线可以由具有低电阻率的硅化多晶或其它材料形成。通过将栅极扩展到厚场氧化物上并且可能通过在控制栅极和浮置栅极之间使用具有相对高的介电常数的绝缘体来改善编程和擦除电压到浮栅的耦合。浮动栅极的侧面由单个图案化步骤限定。所得到的结构是可编程存储器单元的密集交叉点阵列。

60. 发明授权

US5100819A Method of making electrically programmable and erasable memory cells with field plate conductor defined drain regions 失效
标题翻译：制造具有场板导体限定漏极区域的电可编程和可擦除存储单元的方法
公开(公告)号：US5100819A
公开(公告)日：1992-03-31
申请号：US618786
申请日：1990-11-27
申请人： Manzur Gill , Sebastiano D'Arrigo
发明人： Manzur Gill , Sebastiano D'Arrigo
IPC分类号： H01L21/8247 , H01L29/788
CPC分类号： H01L27/11517 , H01L29/7883
摘要： First and second EEPROM cells have first and second source regions (28a, 28b) formed in a semiconductor layer (12) to be of a second conductivity type opposite the first conductivity type of the layer and to be spaced apart from each other. A field plate conductor (100) is insulatively disposed adjacent, and defines, an inversion region (102), and further is laterally spaced between the first and second source regions (28a, 28b). The inversion region (102) is inverted from the first conductivity type to the second conductivity type upon application of a predetermined voltage to the field plate conductor (100). First and second channel regions (48a, 48b) are defined between the respective source regions (28a28b) and the inversion region (102) and each include floating gate and control gate subchannel regions (60a, 62a, 62b, 60b). First and second floating gate conductors (40a, 40b) are insulatively disposed adjacent respective floating gate subchannel regions (60a , 60b) to control their conductance. A control gate conductor is insulatively disposed adjacent the control gate subchannel regions (62a, 62b) to control their conductance. In another embodiment, the field plate conductor (100) is replaced with a pair of field plate conductors (42a, 42b) that control the conductance of respective subchannel regions (64a, 64b). The field plate conductors (42a, 42b) act to self-align a diffused drain region (46) that replaces the inversion region (102).
摘要翻译：第一和第二EEPROM单元具有在半导体层（12）中形成为与第一导电类型相反的第二导电类型并且彼此间隔开的第一和第二源极区（28a，28b）。场平板导体（100）被绝缘地邻近并限定反转区域（102），并且还在第一和第二源极区域（28a，28b）之间横向隔开。当对场板导体（100）施加预定电压时，反转区域（102）从第一导电类型转换为第二导电类型。第一和第二通道区域（48a，48b）被限定在各个源极区域（28a + B，28b）和反转区域（102）之间，并且每个包括浮动栅极和控制栅极子通道区域（60a，62a，62b，60b）。第一和第二浮栅导体（40a，40b）被绝缘地设置在相邻的浮栅子通道区域（60a，60b）附近，以控制它们的电导。控制栅极导体与控制栅极子通道区域（62a，62b）相邻地间隔地设置以控制它们的电导。在另一实施例中，场板导体（100）由控制各个子通道区域（64a，64b）的电导的一对场板导体（42a，42b）代替。场板导体（42a，42b）用于使取代反转区域（102）的扩散漏极区域（46）自对准。

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