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1. 发明授权

US07223688B2 Single level metal memory cell using chalcogenide cladding 有权
标题翻译：使用硫族化物包层的单层金属存储单元
公开(公告)号：US07223688B2
公开(公告)日：2007-05-29
申请号：US10389114
申请日：2003-03-14
申请人： Tyler A. Lowrey , Manzur Gill
发明人： Tyler A. Lowrey , Manzur Gill
IPC分类号： H01L21/3205
CPC分类号： H01L27/2409 , G11C13/0004 , G11C2213/72 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： An apparatus including a volume of phase change material disposed between a first conductor and a second conductor on a substrate, and a plurality of electrodes coupled to the volume of phase change material and the first conductor. A method including introducing, over a first conductor on a substrate, a plurality of electrodes coupled to the first conductor, introducing a phase change material over the plurality of electrodes and in electrical communication with the plurality of electrodes, and introducing a second conductor over the phase change material and coupled to the phase change material.
摘要翻译：一种包括设置在基板上的第一导体和第二导体之间的相变材料体积的装置，以及耦合到所述体积的相变材料和所述第一导体的多个电极。一种方法，包括在衬底上的第一导体上引入耦合到所述第一导体的多个电极，在所述多个电极上引入相变材料并与所述多个电极电连通，以及将第二导体相变材料并耦合到相变材料。

2. 发明授权

US07157304B2 Single level metal memory cell using chalcogenide cladding 有权
公开(公告)号：US07157304B2
公开(公告)日：2007-01-02
申请号：US10838966
申请日：2004-05-05
申请人： Tyler A. Lowrey , Manzur Gill
发明人： Tyler A. Lowrey , Manzur Gill
IPC分类号： H01L21/00
CPC分类号： H01L27/2409 , G11C13/0004 , G11C2213/72 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： An apparatus including a volume of phase change material disposed between a first conductor and a second conductor on a substrate, and a plurality of electrodes coupled to the volume of phase change material and the first conductor. A method including introducing, over a first conductor on a substrate, a plurality of electrodes coupled to the first conductor, introducing a phase change material over the plurality of electrodes and in electrical communication with the plurality of electrodes, and introducing a second conductor over the phase change material and coupled to the phase change material.

3. 发明授权

US06836423B2 Single level metal memory cell using chalcogenide cladding 失效
公开(公告)号：US06836423B2
公开(公告)日：2004-12-28
申请号：US10281337
申请日：2002-10-25
申请人： Tyler A. Lowrey , Manzur Gill
发明人： Tyler A. Lowrey , Manzur Gill
IPC分类号： G11C1700
CPC分类号： H01L27/2409 , G11C13/0004 , G11C2213/72 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： An apparatus including a volume of phase change material disposed between a first conductor and a second conductor on a substrate, and a plurality of electrodes coupled to the volume of phase change material and the first conductor. A method including introducing, over a first conductor on a substrate, a plurality of electrodes coupled to the first conductor, introducing a phase change material over the plurality of electrodes and in electrical communication with the plurality of electrodes, and introducing a second conductor over the phase change material and coupled to the phase change material.

4. 发明授权

US06567293B1 Single level metal memory cell using chalcogenide cladding 有权
公开(公告)号：US06567293B1
公开(公告)日：2003-05-20
申请号：US09675285
申请日：2000-09-29
申请人： Tyler A. Lowrey , Manzur Gill
发明人： Tyler A. Lowrey , Manzur Gill
IPC分类号： G11C1700
CPC分类号： H01L27/2409 , G11C13/0004 , G11C2213/72 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： An apparatus including a volume of phase change material disposed between a first conductor and a second conductor on a substrate, and a plurality of electrodes coupled to the volume of phase change material and the first conductor. A method including introducing, over a first conductor on a substrate, a plurality of electrodes coupled to the first conductor, introducing a phase change material over the plurality of electrodes and in electrical communication with the plurality of electrodes, and introducing a second conductor over the phase change material and coupled to the phase change material.

5. 发明授权

US06545907B1 Technique and apparatus for performing write operations to a phase change material memory device 有权
标题翻译：用于对相变材料存储装置执行写入操作的技术和装置
公开(公告)号：US06545907B1
公开(公告)日：2003-04-08
申请号：US10021469
申请日：2001-10-30
申请人： Tyler A. Lowrey , Ward D. Parkinson , Manzur Gill
发明人： Tyler A. Lowrey , Ward D. Parkinson , Manzur Gill
IPC分类号： G11C1100
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2013/0076
摘要： A technique includes, in response to a request to write data to memory cells of a phase change memory device, placing the memory cells in a state that is shared in common among the memory cells. Also, in response to this request, the data is written to the memory cells.
摘要翻译：一种技术包括响应于将数据写入相变存储器件的存储器单元的请求，将存储器单元放置在存储器单元之间共享的状态。此外，响应于该请求，数据被写入存储单元。

6. 发明授权

US06995446B2 Isolating phase change memories with schottky diodes and guard rings 有权
标题翻译：用肖特基二极管和保护环隔离相变存储器
公开(公告)号：US06995446B2
公开(公告)日：2006-02-07
申请号：US10318704
申请日：2002-12-13
申请人： Ilya Karpov , Manzur Gill
发明人： Ilya Karpov , Manzur Gill
IPC分类号： H01L29/76
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L29/872 , H01L45/06
摘要： A phase change memory may be made using an isolation diode in the form of a Shottky diode between a memory cell and a word line. To reduce the leakage currents associated with the Shottky diode, a guard ring may be utilized.
摘要翻译：可以使用在存储器单元和字线之间的肖特基二极管形式的隔离二极管来进行相变存储器。为了减少与肖特基二极管相关的泄漏电流，可以使用保护环。

7. 发明授权

US06791107B2 Silicon on insulator phase change memory 有权
标题翻译：硅绝缘体相变存储器
公开(公告)号：US06791107B2
公开(公告)日：2004-09-14
申请号：US10336171
申请日：2003-01-03
申请人： Manzur Gill , Tyler Lowrey
发明人： Manzur Gill , Tyler Lowrey
IPC分类号： H01L2906
CPC分类号： G11C13/0004 , G11C13/003 , G11C2213/74 , G11C2213/79 , H01L27/12 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1683
摘要： The invention relates to a phase-change memory device that uses SOI in a chalcogenide volume of memory material. Parasitic capacitance, both vertical and lateral, are reduced or eliminated in the inventive structure.
摘要翻译：本发明涉及在存储材料的硫族化物体积中使用SOI的相变存储器件。寄生电容（垂直和横向）在本发明的结构中被减少或消除。

8. 发明授权

US06625054B2 Method and apparatus to program a phase change memory 失效
标题翻译：编程相变存储器的方法和装置
公开(公告)号：US06625054B2
公开(公告)日：2003-09-23
申请号：US10034146
申请日：2001-12-28
申请人： Tyler Lowrey , Manzur Gill
发明人： Tyler Lowrey , Manzur Gill
IPC分类号： G11C1100
CPC分类号： G11C13/0004 , G11C11/56 , G11C11/5678 , G11C13/0069 , G11C2013/0092
摘要： Briefly, in accordance with an embodiment of the invention, a method and an apparatus to program a multi level cell (MLC) phase change material is provided.
摘要翻译：简而言之，根据本发明的实施例，提供了一种编程多级单元（MLC）相变材料的方法和装置。

9. 发明授权

US06531373B2 Method of forming a phase-change memory cell using silicon on insulator low electrode in charcogenide elements 有权
标题翻译：在硫族化物元素中使用绝缘体上硅绝缘体形成相变存储单元的方法
公开(公告)号：US06531373B2
公开(公告)日：2003-03-11
申请号：US09751485
申请日：2000-12-27
申请人： Manzur Gill , Tyler Lowrey
发明人： Manzur Gill , Tyler Lowrey
IPC分类号： H01L2176
CPC分类号： G11C13/0004 , G11C13/003 , G11C2213/74 , G11C2213/79 , H01L27/12 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1683
摘要： The invention relates to a phase-change memory device that uses SOI in a chalcogenide volume of memory material. Parasitic capacitance, both vertical and lateral, are reduced or eliminated in the inventive structure.
摘要翻译：本发明涉及在存储材料的硫族化物体积中使用SOI的相变存储器件。寄生电容（垂直和横向）在本发明的结构中被减少或消除。

10. 发明授权

US5420060A Method of making contract-free floating-gate memory array with silicided buried bitlines and with single-step defined floating gates 失效
标题翻译：具有硅化掩埋位线和单步定义浮动栅极的无契约式浮栅存储器阵列的方法
公开(公告)号：US5420060A
公开(公告)日：1995-05-30
申请号：US140410
申请日：1993-09-13
申请人： Manzur Gill , Howard L. Tigelaar
发明人： Manzur Gill , Howard L. Tigelaar
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L21/70
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between bitlines is by thick field oxide. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The sides of the floating gates are defined with a single patterning step. The resulting structure is a dense cross-point array of programmable memory cells.
摘要翻译：一个无接触的浮栅非易失性存储单元阵列和具有硅化NSAG位线的工艺，以及埋在相对厚的氧化硅之下的源/漏区。位线具有相对较小的电阻，消除了对具有大量位线触点的并行金属导体的需要。阵列具有相对小的位线电容，并且可以构造成具有相对较小的尺寸。位线之间的隔离是通过厚场氧化物。字线可以由具有低电阻率的硅化多晶或其它材料形成。通过将栅极扩展到厚场氧化物上并且可能通过在控制栅极和浮置栅极之间使用具有相对高的介电常数的绝缘体来改善编程和擦除电压到浮栅的耦合。浮动栅极的侧面由单个图案化步骤限定。所得到的结构是可编程存储器单元的密集交叉点阵列。

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