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1. 发明授权

US06995446B2 Isolating phase change memories with schottky diodes and guard rings 有权
标题翻译：用肖特基二极管和保护环隔离相变存储器
公开(公告)号：US06995446B2
公开(公告)日：2006-02-07
申请号：US10318704
申请日：2002-12-13
申请人： Ilya Karpov , Manzur Gill
发明人： Ilya Karpov , Manzur Gill
IPC分类号： H01L29/76
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L29/872 , H01L45/06
摘要： A phase change memory may be made using an isolation diode in the form of a Shottky diode between a memory cell and a word line. To reduce the leakage currents associated with the Shottky diode, a guard ring may be utilized.
摘要翻译：可以使用在存储器单元和字线之间的肖特基二极管形式的隔离二极管来进行相变存储器。为了减少与肖特基二极管相关的泄漏电流，可以使用保护环。

2. 发明授权

US06791107B2 Silicon on insulator phase change memory 有权
标题翻译：硅绝缘体相变存储器
公开(公告)号：US06791107B2
公开(公告)日：2004-09-14
申请号：US10336171
申请日：2003-01-03
申请人： Manzur Gill , Tyler Lowrey
发明人： Manzur Gill , Tyler Lowrey
IPC分类号： H01L2906
CPC分类号： G11C13/0004 , G11C13/003 , G11C2213/74 , G11C2213/79 , H01L27/12 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1683
摘要： The invention relates to a phase-change memory device that uses SOI in a chalcogenide volume of memory material. Parasitic capacitance, both vertical and lateral, are reduced or eliminated in the inventive structure.
摘要翻译：本发明涉及在存储材料的硫族化物体积中使用SOI的相变存储器件。寄生电容（垂直和横向）在本发明的结构中被减少或消除。

3. 发明授权

US06625054B2 Method and apparatus to program a phase change memory 失效
标题翻译：编程相变存储器的方法和装置
公开(公告)号：US06625054B2
公开(公告)日：2003-09-23
申请号：US10034146
申请日：2001-12-28
申请人： Tyler Lowrey , Manzur Gill
发明人： Tyler Lowrey , Manzur Gill
IPC分类号： G11C1100
CPC分类号： G11C13/0004 , G11C11/56 , G11C11/5678 , G11C13/0069 , G11C2013/0092
摘要： Briefly, in accordance with an embodiment of the invention, a method and an apparatus to program a multi level cell (MLC) phase change material is provided.
摘要翻译：简而言之，根据本发明的实施例，提供了一种编程多级单元（MLC）相变材料的方法和装置。

4. 发明授权

US06531373B2 Method of forming a phase-change memory cell using silicon on insulator low electrode in charcogenide elements 有权
标题翻译：在硫族化物元素中使用绝缘体上硅绝缘体形成相变存储单元的方法
公开(公告)号：US06531373B2
公开(公告)日：2003-03-11
申请号：US09751485
申请日：2000-12-27
申请人： Manzur Gill , Tyler Lowrey
发明人： Manzur Gill , Tyler Lowrey
IPC分类号： H01L2176
CPC分类号： G11C13/0004 , G11C13/003 , G11C2213/74 , G11C2213/79 , H01L27/12 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1683
摘要： The invention relates to a phase-change memory device that uses SOI in a chalcogenide volume of memory material. Parasitic capacitance, both vertical and lateral, are reduced or eliminated in the inventive structure.
摘要翻译：本发明涉及在存储材料的硫族化物体积中使用SOI的相变存储器件。寄生电容（垂直和横向）在本发明的结构中被减少或消除。

5. 发明授权

US5420060A Method of making contract-free floating-gate memory array with silicided buried bitlines and with single-step defined floating gates 失效
标题翻译：具有硅化掩埋位线和单步定义浮动栅极的无契约式浮栅存储器阵列的方法
公开(公告)号：US5420060A
公开(公告)日：1995-05-30
申请号：US140410
申请日：1993-09-13
申请人： Manzur Gill , Howard L. Tigelaar
发明人： Manzur Gill , Howard L. Tigelaar
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L21/70
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between bitlines is by thick field oxide. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The sides of the floating gates are defined with a single patterning step. The resulting structure is a dense cross-point array of programmable memory cells.
摘要翻译：一个无接触的浮栅非易失性存储单元阵列和具有硅化NSAG位线的工艺，以及埋在相对厚的氧化硅之下的源/漏区。位线具有相对较小的电阻，消除了对具有大量位线触点的并行金属导体的需要。阵列具有相对小的位线电容，并且可以构造成具有相对较小的尺寸。位线之间的隔离是通过厚场氧化物。字线可以由具有低电阻率的硅化多晶或其它材料形成。通过将栅极扩展到厚场氧化物上并且可能通过在控制栅极和浮置栅极之间使用具有相对高的介电常数的绝缘体来改善编程和擦除电压到浮栅的耦合。浮动栅极的侧面由单个图案化步骤限定。所得到的结构是可编程存储器单元的密集交叉点阵列。

6. 发明授权

US5371031A Method of making EEPROM array with buried N+ windows and with separate erasing and programming regions 失效
标题翻译：制造具有埋入式N +窗口并具有单独擦除和编程区域的EEPROM阵列的方法
公开(公告)号：US5371031A
公开(公告)日：1994-12-06
申请号：US89206
申请日：1993-07-09
申请人： Manzur Gill , Inn K. Lee
发明人： Manzur Gill , Inn K. Lee
IPC分类号： H01L21/8247 , H01L21/70
CPC分类号： H01L27/11521
摘要： An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source region (11) and a drain region (12), with a corresponding channel region between. A Fowler-Nordheim tunnel-window (13a) is located over the source line (17) connected to source (11). The source line (17) consists of alternating buried N+ windows (17a) and source regions (11). A floating gate (13) includes a tunnel-window section. A control gate (14) is disposed over the floating gate (13), insulated by an intervening inter-level dielectric (27). The floating gate (13) and the control gate (14) include a channel section (Ch). The channel section (Ch) is used as a self-alignment implant mask for the source (11) and drain (12) regions, such that the channel-junction edges are aligned with the corresponding edges of the channel section (Ch). The memory cell is programmed by hot-carrier injection from the channel to the floating gate (13), and erased by Fowler-Nordheim tunneling from the floating gate (13) through the tunnel window (13a) to the source-line (17). The program and erase regions of the cells are physically separate from each other, and the characteristics, including the oxides, of each of those regions may be made optimum independently from each other.
摘要翻译：在半导体衬底（22）的表面上成对地形成电可擦除的电可编程的只读存储单元阵列。每个存储单元包括源极区域（11）和漏极区域（12），其间具有相应的沟道区域。福勒 - 诺德海姆隧道窗口（13a）位于连接到源（11）的源极线（17）上。源极线（17）由交替的掩埋N +窗口（17a）和源极区域（11）组成。浮动门（13）包括隧道窗部分。控制栅极（14）设置在浮置栅极（13）上，由中间层间电介质（27）绝缘。浮动栅极（13）和控制栅极（14）包括通道部分（Ch）。通道部分（Ch）用作源（11）和漏极（12）区域的自对准注入掩模，使得沟道结边缘与通道部分（Ch）的相应边缘对齐。存储单元通过从通道的热载流子注入到浮动栅极（13）进行编程，并由Fowler-Nordheim从浮动栅极（13）通过隧道窗口（13a）到源极线（17）的隧道擦除，。单元的程序和擦除区域在物理上彼此分离，并且这些区域中的每一个的特性，包括氧化物可以彼此独立地最优化。

7. 发明授权

US5218568A Electrically-erasable, electrically-programmable read-only memory cell, an array of such cells and methods for making and using the same 失效
标题翻译：电可擦除的电可编程只读存储器单元，这样的单元阵列以及制造和使用它们的方法
公开(公告)号：US5218568A
公开(公告)日：1993-06-08
申请号：US809462
申请日：1991-12-17
申请人： Sung-Wei Lin , Manzur Gill , Inn K. Lee
发明人： Sung-Wei Lin , Manzur Gill , Inn K. Lee
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , G11C16/0433 , H01L27/115 , H01L27/11524
摘要： An electrically-erasable, electrically-programmable read-only memory cell 10 is formed at a face of a layer of semiconductor 30 of a first conductivity type. A first source/drain region 16 and a second source/drain region 20 are formed in the face of layer of semiconductor 30 of a second conductivity type opposite the first conductivity type and spaced by a first channel area 50. A third source/drain region 18 is formed in the face of semiconductor layer 30 of the second conductivity type spaced from second source/drain region 20 by a second channel area 52. A thick insulator region 44 is formed adjacent at least a portion of second source/drain region 20 and includes a lateral margin of sloped thickness overlying a corresponding lateral margin of second source/drain region 20. The corresponding lateral margin of second source/drain region 20 has a graded dopant concentration directly proportionate with the sloped thickness of the overlying lateral margin of thick insulator region 44. A differentially grown insulator region 54 overlies second source/drain region 20 and includes a lateral margin of sloped thickness. A thin insulator tunneling window 62 overlies an area 60 of second source/drain region 20, tunneling window 62 formed between and spacing the lateral margin of the thick insulator region 44 and the lateral margin of differentially grown insulator region 54. A floating gate conductor 26 is disposed adjacent tunneling window 62 and insulatively adjacent second channel area 52. A control gate conductor 28 is disposed insulatively adjacent floating gate conductor 28. A gate conductor 24 is disposed insulatively adjacent first channel area 50.
摘要翻译：电可擦除的电可编程只读存储单元10形成在第一导电类型的半导体层30的表面。第一源极/漏极区域16和第二源极/漏极区域20形成在与第一导电类型相反并且由第一沟道区域50间隔开的第二导电类型的半导体层30的表面中。第三源极/漏极区域 18形成在第二导电类型的半导体层30的表面上，第二导电类型的第二导电类型与第二源极/漏极区域20间隔开第二沟道区域52.邻近第二源极/漏极区域20的至少一部分形成厚的绝缘体区域44，包括覆盖第二源极/漏极区域20的相应横向边缘的倾斜厚度的横向边缘。第二源极/漏极区域20的对应横向边缘具有与厚度绝缘体的上覆侧边缘的倾斜厚度成正比的渐变掺杂剂浓度差分生长的绝缘体区域54覆盖第二源极/漏极区域20并且包括倾斜厚度的侧向边缘。薄的绝缘体隧道窗口62覆盖在第二源极/漏极区域20的区域60之间，形成在厚绝缘体区域44的侧边缘之间并且间隔着厚的绝缘体区域44的侧边缘和差分生长的绝缘体区域54的横向边缘之间的隧道窗口62.浮动栅极导体26 被布置在相邻的隧道窗口62和绝对相邻的第二通道区域52处。控制栅极导体28被隔离地邻近浮置栅极导体28设置。栅极导体24与第一沟道区域50绝缘地邻近设置。

8. 发明授权

US5155055A Method of making an electrically-erasable, electrically-programmable read-only memory cell with self-aligned tunnel 失效
标题翻译：制造具有自对准隧道的电可擦除，电可编程只读存储器单元的方法
公开(公告)号：US5155055A
公开(公告)日：1992-10-13
申请号：US685358
申请日：1991-04-15
申请人： Manzur Gill , Sung-Wei Lin , C. Rinn Cleavelin , David J. McElroy
发明人： Manzur Gill , Sung-Wei Lin , C. Rinn Cleavelin , David J. McElroy
IPC分类号： H01L21/8247 , H01L29/788
CPC分类号： H01L27/11517 , H01L29/7883
摘要： An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small self-aligned tunnel window positioned on the opposite side of the source from the channel and drain, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. In this cell, the bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window area on the outside of the source (spaced from the channel). The tunnel window has a thinner dielectric than the remainder of the floating gate to allow Fowler-Nordheim tunneling.
摘要翻译：使用与浮栅晶体管合并的增强型晶体管构造电可擦除的电可编程ROM或EEPROM，其中浮栅晶体管具有位于源极的相对侧上的小的自对准隧道窗口通道和漏极，无接触电池布局，增强了制造的便利性和减小电池尺寸。在该单元中，位线和源极/漏极区域被埋在相对较厚的氧化硅之下，这允许控制栅极与浮动栅极电容的有利比例。编程和擦除由源外部的隧道窗口区域（与通道间隔开）提供。隧道窗口具有比浮动门的其余部分更薄的电介质，以允许Fowler-Nordheim隧道。

9. 发明授权

US5057446A Method of making an EEPROM with improved capacitive coupling between control gate and floating gate 失效
标题翻译：制造具有改善的控制栅极和浮动栅极之间的电容耦合的EEPROM的方法
公开(公告)号：US5057446A
公开(公告)日：1991-10-15
申请号：US563369
申请日：1990-08-06
申请人： Manzur Gill , David J. McElroy
发明人： Manzur Gill , David J. McElroy
IPC分类号： H01L21/28 , H01L21/8247 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/7883
摘要： According to the invention, an integrated circuit with improved capacitive coupling is provided, and includes a first conductor (20), a second conductor (16), and a third conductor (22). The second conductor (22) and third conductor (16) are disposed adjacent each other, separated by an insulator region (60). The first conductor (20) contacts the third conductor (16) and extends across a portion of the third conductor (22). The first and third conductors are separated by an insulator region (54). A voltage applied to first conductor (20) and second conductor (16) is capacitively coupled to third conductor (22).
摘要翻译：根据本发明，提供了具有改进的电容耦合的集成电路，并且包括第一导体（20），第二导体（16）和第三导体（22）。第二导体（22）和第三导体（16）彼此相邻设置，由绝缘体区域（60）分开。第一导体（20）接触第三导体（16）并延伸穿过第三导体（22）的一部分。第一和第三导体被绝缘体区域（54）隔开。施加到第一导体（20）和第二导体（16）的电压电容耦合到第三导体（22）。

10. 发明授权

US5051796A Cross-point contact-free array with a high-density floating-gate structure 失效
标题翻译：具有高密度浮栅结构的交叉点无接触阵列
公开(公告)号：US5051796A
公开(公告)日：1991-09-24
申请号：US403065
申请日：1989-09-01
申请人： Manzur Gill
发明人： Manzur Gill
IPC分类号： H01L27/115
CPC分类号： H01L27/115
摘要： A contact-free floating-gate non-volatile memory cell array and process with silicated NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines having a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Bitline isolation is by P/N junction or by oxide-filled trench, permitting relatively small spacing between transistors. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The resulting structure is a dense cross-point array of programmable memory cells.
摘要翻译：无接触式浮栅非易失性存储单元阵列和具有硅胶NSAG位线和掩埋在相对厚的氧化硅之下的源/漏区的工艺。位线具有相对较小的电阻，消除了对具有许多位线触点的并行金属导体的需要。阵列具有相对小的位线电容，并且可以构造成具有相对较小的尺寸。位线隔离是通过P / N结或通过氧化物填充沟槽，允许晶体管之间的间隔相对较小。字线可以由具有低电阻率的硅化多晶或其它材料形成。通过在控制栅极和浮置栅极之间使用具有相对较高介电常数的绝缘体来提高编程和擦除电压到浮栅的耦合。所得到的结构是可编程存储器单元的密集交叉点阵列。

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