专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US06242304B1 Method and structure for textured surfaces in floating gate tunneling oxide devices 失效
标题翻译：浮栅隧道氧化器件中纹理化表面的方法
公开(公告)号：US06242304B1
公开(公告)日：2001-06-05
申请号：US09087539
申请日：1998-05-29
申请人： Joseph E. Geusic , Leonard Forbes
发明人： Joseph E. Geusic , Leonard Forbes
IPC分类号： H01L21336
CPC分类号： H01L21/28273 , H01L29/511 , H01L29/7883
摘要： A method and structure for textured surfaces in non volatile floating gate tunneling oxide (FLOTOX) devices, e.g. FLOTOX transistors, are provided. The present invention capitalizes on using “self-structured masks” and a controlled etch to form nanometer scale microtip arrays in the textured surfaces. The microtips in the array of microtips have a more uniform size and shape and higher density (˜1012/cm2) at the substrate/tunnel oxide (Si/SiO2) interface than in current generation FLOTOX transistors. This higher density is four orders of magnitude greater than that which has been in use with FLOTOX transistor technology. In result, the new method and structure produce significantly larger tunneling currents for a given voltage than attained in prior work. The new method and structure are advantageously suited for the much higher density, non volatile FLOTOX transistors desired for use in flash memories and in electronically erasable and programmable read only memories (EEPROMs). These FLOTOX transistors are candidates for replacing the low power operation transistors found in DRAMs.
摘要翻译：非挥发性浮栅隧道氧化物（FLOTOX）器件中的纹理表面的方法和结构，例如。 FLOTOX晶体管。本发明利用“自组织掩模”和受控蚀刻在纹理化表面中形成纳米级微尖头阵列。微尖端阵列中的微尖端在衬底/隧道氧化物（Si / SiO 2）界面处具有比当前一代FLOTOX晶体管更大的尺寸和形状以及更高的密度（〜1012 / cm2）。这种更高的密度比使用FLOTOX晶体管技术的密度高四个数量级。结果，对于给定的电压，新的方法和结构产生明显较大的隧道电流，这在以前的工作中获得。新的方法和结构有利地适用于期望用于闪存和电可擦除和可编程只读存储器（EEPROM）的更高密度，非易失性FLOTOX晶体管。这些FLOTOX晶体管是替代在DRAM中发现的低功率运算晶体管的候选者。

52. 发明授权

US06198168B1 Integrated circuits using high aspect ratio vias through a semiconductor wafer and method for forming same 失效
标题翻译：使用通过半导体晶片的高纵横比通孔的集成电路及其形成方法
公开(公告)号：US06198168B1
公开(公告)日：2001-03-06
申请号：US09009791
申请日：1998-01-20
申请人： Joseph E. Geusic , Kie Y. Ahn , Leonard Forbes
发明人： Joseph E. Geusic , Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L2348
CPC分类号： H01L23/48 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit and method for forming the same. The integrated circuit includes a semiconductor wafer with first and second surfaces. A functional circuit is formed on the first surface of the semiconductor wafer. Further, a metallization layer is formed outwardly from the first surface of the semiconductor wafer. The integrated circuit also includes at least one high aspect ratio via that extends through the layer of semiconductor material. This via provides a connection between a lead and the functional circuit.
摘要翻译：一种集成电路及其形成方法。集成电路包括具有第一和第二表面的半导体晶片。在半导体晶片的第一表面上形成功能电路。此外，从半导体晶片的第一表面向外形成金属化层。集成电路还包括延伸穿过半导体材料层的至少一个高纵横比通孔。该通孔提供引线和功能电路之间的连接。

53. 发明授权

US06143616A Methods of forming coaxial integrated circuitry interconnect lines 失效
标题翻译：形成同轴集成电路互连线的方法
公开(公告)号：US06143616A
公开(公告)日：2000-11-07
申请号：US917449
申请日：1997-08-22
申请人： Joseph E. Geusic , Kie Y. Ahn , Leonard Forbes
发明人： Joseph E. Geusic , Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L21/768 , H01L21/20
CPC分类号： H01L21/76898 , H01L2223/6622
摘要： Methods of forming integrated circuitry lines such as coaxial integrated circuitry interconnect lines, and related integrated circuitry are described. An inner conductive coaxial line component is formed which extends through a substrate. An outer conductive coaxial line component and coaxial dielectric material are formed, with the coaxial dielectric material being formed operably proximate and between the inner and outer conductive coaxial line components. In a preferred implementation, the substrate includes front and back surfaces, and a hole is formed which extends through the substrate and between the front and back surfaces. In one implementation, the outer conductive coaxial line component constitutes doped semiconductive material. In another implementation, such constitutes a layer of metal-comprising material. A layer of dielectric material is formed over and radially inwardly of the outer line component. Conductive material is then formed over and radially inwardly of the dielectric material layer. The latter conductive material constitutes an inner conductive coaxial line component. In a preferred implementation, the inner conductive coaxial line component is formed by forming a first material within the hole. A second conductive material is formed over the first material. Subsequently, the substrate is exposed to conditions which are effective to cause the second material to replace the first material.
摘要翻译：描述形成诸如同轴集成电路互连线和集成电路的集成电路线的方法。形成延伸穿过衬底的内导电同轴线部件。形成外部导电同轴线路部件和同轴电介质材料，其中同轴电介质材料可靠地形成在内部和外部导电同轴线路部件之间。在优选的实施方案中，衬底包括前表面和后表面，并且形成了延伸穿过衬底并且在前表面和后表面之间的孔。在一个实施方案中，外导电同轴线组件构成掺杂的半导体材料。在另一个实施方案中，这样构成一层含金属的材料。介电材料层形成在外线部件的上部和内部。然后在电介质材料层的上部和内部形成导电材料。后一导电材料构成内导电同轴线组件。在优选的实施方案中，内导电同轴线部件通过在孔内形成第一材料而形成。在第一材料上形成第二导电材料。随后，将基板暴露于有效地使第二材料替代第一材料的条件。

54. 发明授权

US6025627A Alternate method and structure for improved floating gate tunneling devices 失效
标题翻译：改进浮栅隧道装置的替代方法和结构
公开(公告)号：US6025627A
公开(公告)日：2000-02-15
申请号：US87473
申请日：1998-05-29
申请人： Leonard Forbes , Joseph E. Geusic
发明人： Leonard Forbes , Joseph E. Geusic
IPC分类号： H01L21/28 , H01L29/51 , H01L29/788
CPC分类号： H01L21/28194 , H01L21/28273 , H01L29/51 , H01L29/7883 , Y10S438/964
摘要： A method and structure for textured surfaces in non volatile floating gate tunneling oxide (FLOTOX) devices, e.g. FLOTOX transistors, are provided. The present invention capitalizes on using "self-structured masks" and a controlled etch to form nanometer scale microtip arrays to form the textured surfaces. The present invention further employs atomic layer epitaxy (ALE) to create a very conformal tunnel oxide layer which complements the nanometer scale microtip arrays. The resulting structure provides a higher tunneling current than currently exists in FLOTOX technology. The improved tunneling currents at low voltages can make these FLOTOX devices suitable for replacing DRAMS.
摘要翻译：非挥发性浮栅隧道氧化物（FLOTOX）器件中的纹理表面的方法和结构，例如。 FLOTOX晶体管。本发明利用“自我结构的掩模”和受控的蚀刻来形成纳米尺度的微尖头阵列以形成纹理表面。本发明还采用原子层外延（ALE）来形成与纳米级微尖头阵列相互补充的非常适形的隧道氧化物层。所得到的结构提供比FLOTOX技术中目前存在的更高的隧道电流。在低电压下改进的隧道电流可以使这些FLOTOX器件适合替代DRAMS。

55. 发明授权

US5981350A Method for forming high capacitance memory cells 失效
标题翻译：用于形成高电容存储单元的方法
公开(公告)号：US5981350A
公开(公告)日：1999-11-09
申请号：US87480
申请日：1998-05-29
申请人： Joseph E. Geusic , Leonard Forbes , Kie Y. Ahn
发明人： Joseph E. Geusic , Leonard Forbes , Kie Y. Ahn
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： B82Y10/00 , B82Y30/00 , H01L27/1087 , Y10S977/888 , Y10S977/943
摘要： A method and structure for high capacitance memory cells is provided. The method includes forming a trench capacitor in a semiconductor substrate. A self-structured mask is formed on the interior surface of the trench. The interior surface of the trench is etched to form an array of silicon pillars. The self-structured mask is removed. Then an insulator layer is formed on the array of silicon pillars. A polycrystalline semiconductor plate extends outwardly from the insulator layer in the trench.
摘要翻译：提供了一种用于高电容存储单元的方法和结构。该方法包括在半导体衬底中形成沟槽电容器。在沟槽的内表面上形成自我结构的掩模。蚀刻沟槽的内表面以形成硅柱阵列。去除自我结构的面具。然后在硅柱阵列上形成绝缘体层。多晶半导体板从沟槽中的绝缘体层向外延伸。

56. 发明授权

US07196929B1 Method for operating a memory device having an amorphous silicon carbide gate insulator 有权
标题翻译：用于操作具有非晶碳化硅栅极绝缘体的存储器件的方法
公开(公告)号：US07196929B1
公开(公告)日：2007-03-27
申请号：US09135413
申请日：1998-08-14
申请人： Leonard Forbes , Joseph E. Geusic , Kie Y. Ahn
发明人： Leonard Forbes , Joseph E. Geusic , Kie Y. Ahn
IPC分类号： G11C16/04
CPC分类号： G11C16/0416
摘要： A floating gate transistor has a reduced barrier energy at an interface with an adjacent amorphous silicon carbide (a-SiC) gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.
摘要翻译：浮栅晶体管在与相邻的非晶碳化硅（a-SiC）栅极绝缘体的界面处具有减小的势垒能，允许在较低电压下更快地跨栅极绝缘体的电荷传输。数据作为电荷存储在浮动栅极上。浮动栅极上的数据电荷保留时间减少。存储在浮动门上的数据被动态刷新。浮栅晶体管提供了适用于诸如用于动态随机存取存储器（DRAM）或动态刷新的快闪EEPROM存储器的密集且平面的动态电可更改和可编程只读存储器（DEAPROM）单元。浮栅晶体管提供高增益存储单元和低电压工作。

57. 发明授权

US06995443B2 Integrated circuits using optical fiber interconnects formed through a semiconductor wafer 失效
标题翻译：使用通过半导体晶片形成的光纤互连的集成电路
公开(公告)号：US06995443B2
公开(公告)日：2006-02-07
申请号：US10772606
申请日：2004-02-05
申请人： Joseph E. Geusic , Kie Y. Ahn , Leonard Forbes
发明人： Joseph E. Geusic , Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L31/0232
CPC分类号： G02B6/43 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit with a number of optical fibers that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical fibers include a cladding layer and a core formed in the high aspect ratio hole. These optical fibers are used to transmit signals between functional circuits on the semiconductor wafer and functional circuits on the back of the wafer or beneath the wafer.
摘要翻译：具有形成在高纵横比孔中的多根光纤的集成电路。高纵横比孔延伸穿过半导体晶片。光纤包括形成在高纵横比孔中的包覆层和芯。这些光纤用于在半导体晶片上的功能电路和晶片背面或晶片之下的功能电路之间传输信号。

58. 发明授权

US06950585B2 Hollow core photonic bandgap optical fiber 有权
标题翻译：空心光子带隙光纤
公开(公告)号：US06950585B2
公开(公告)日：2005-09-27
申请号：US10804421
申请日：2004-03-19
申请人： Leonard Forbes , Joseph E. Geusic
发明人： Leonard Forbes , Joseph E. Geusic
IPC分类号： C03B37/012 , C03B37/15 , G02B6/02 , G02B6/16
CPC分类号： G02B6/02328 , C03B37/01205 , C03B37/0124 , C03B37/15 , C03B2203/14 , C03B2203/16 , C03B2203/42 , G02B6/02347 , G02B6/02371
摘要： A photonic crystal optical fiber made up of an array of conventional hollow core optical fibers is disclosed. The array of optical fibers omits at least one fiber to form a central hollow core. The fiber works on the principle of two-dimensional photonic crystals to confine the radiation in a guided wave within the central hollow core. The fiber has a true photonic bandgap in which radiation of a particular energy or wavelength is totally forbidden, thereby providing a very high reflection coefficient to radiation incident the walls of the central hollow core over a select range of angles. The central hollow core allows for radiation propagation with minimal absorption.
摘要翻译：公开了一种由常规空心芯光纤阵列组成的光子晶体光纤。光纤阵列省略至少一根光纤以形成中心空心芯。纤维以二维光子晶体的原理工作，将辐射限制在中心空心芯内的导波中。光纤具有真正的光子带隙，其中特定能量或波长的辐射被完全禁止，从而在选择的角度范围内对入射到中心空心芯的壁的辐射提供非常高的反射系数。中心空心芯允许最小吸收的辐射传播。

59. 发明授权

US06929984B2 Gettering using voids formed by surface transformation 失效
公开(公告)号：US06929984B2
公开(公告)日：2005-08-16
申请号：US10623794
申请日：2003-07-21
申请人： Leonard Forbes , Joseph E. Geusic
发明人： Leonard Forbes , Joseph E. Geusic
IPC分类号： H01L21/322 , H01L21/324 , H01L29/78 , H01L21/335 , H01L21/8232
CPC分类号： H01L27/105 , H01L21/3223 , H01L21/324 , H01L27/108 , H01L29/78 , Y10S257/913
摘要： One aspect of this disclosure relates to a method for creating a gettering site in a semiconductor wafer. In various embodiments, a predetermined arrangement of a plurality of holes is formed in the semiconductor wafer through a surface of the wafer. The wafer is annealed such that the wafer undergoes a surface transformation to transform the arrangement of the plurality of holes into a predetermined arrangement of at least one empty space of a predetermined size within the wafer to form the gettering site. One aspect relates to a semiconductor wafer. In various embodiments, the wafer includes at least one device region, and at least one gettering region located proximate to the at least one device region. The gettering region includes a precisely-determined arrangement of a plurality of precisely-formed voids that are formed within the wafer using a surface transformation process. Other aspects and embodiments are provided herein.

60. 发明授权

US06927122B2 Method and structure for high capacitance memory cells 有权
标题翻译：高电容存储单元的方法和结构
公开(公告)号：US06927122B2
公开(公告)日：2005-08-09
申请号：US10929253
申请日：2004-08-30
申请人： Joseph E. Geusic , Leonard Forbes , Kie Y. Ahn
发明人： Joseph E. Geusic , Leonard Forbes , Kie Y. Ahn
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： B82Y10/00 , B82Y30/00 , H01L27/1087 , Y10S977/888 , Y10S977/943
摘要： A method and structure for high capacitance memory cells is provided. The method includes forming a trench capacitor in a semiconductor substrate. A self-structured mask is formed on the interior surface of the trench. The interior surface of the trench is etched to form an array of silicon pillars. The self-structured mask is removed. Then an insulator layer is formed on the array of silicon pillars. A polycrystalline semiconductor plate extends outwardly from the insulator layer in the trench.
摘要翻译：提供了一种用于高电容存储单元的方法和结构。该方法包括在半导体衬底中形成沟槽电容器。在沟槽的内表面上形成自我结构的掩模。蚀刻沟槽的内表面以形成硅柱阵列。去除自我结构的面具。然后在硅柱阵列上形成绝缘体层。多晶半导体板从沟槽中的绝缘体层向外延伸。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式