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1. 发明授权

US07547954B2 Electronic systems using optical waveguide interconnects formed through a semiconductor wafer 有权
标题翻译：使用通过半导体晶片形成的光波导互连的电子系统
公开(公告)号：US07547954B2
公开(公告)日：2009-06-16
申请号：US11653501
申请日：2007-01-16
申请人： Joseph E. Geusic , Kie Y. Ahn , Leonard Forbes
发明人： Joseph E. Geusic , Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L31/0232
CPC分类号： G02B6/032 , G02B6/12002 , G02B6/136 , G02B6/42 , G02B6/43
摘要： An integrated circuit with a number of optical waveguides that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical waveguides include a highly reflective material that is deposited so as to line an inner surface of the high aspect ratio holes which may be filled with air or a material with an index of refraction that is greater than 1. These metal confined waveguides are used to transmit signals between functional circuits on the semiconductor wafer and functional circuits on the back of the wafer or beneath the wafer.
摘要翻译：具有形成在高纵横比孔中的多个光波导的集成电路。高纵横比孔延伸穿过半导体晶片。光波导包括高反射材料，其被沉积以便可以填充空气的高纵横比孔的内表面或具有大于1的折射率的材料。这些金属限制波导被使用以在半导体晶片上的功能电路和晶片的背面或晶片之下的功能电路之间传输信号。

2. 发明授权

US07164156B2 Electronic systems using optical waveguide interconnects formed throught a semiconductor wafer 有权
标题翻译：使用通过半导体晶片形成的光波导互连的电子系统
公开(公告)号：US07164156B2
公开(公告)日：2007-01-16
申请号：US11342940
申请日：2006-01-30
申请人： Joseph E. Geusic , Kie Y. Ahn , Leonard Forbes
发明人： Joseph E. Geusic , Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L27/15 , H01L31/12 , H01L31/153 , H01L33/00
CPC分类号： G02B6/032 , G02B6/12002 , G02B6/136 , G02B6/42 , G02B6/43
摘要： An integrated circuit with a number of optical waveguides that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical waveguides include a highly reflective material that is deposited so as to line an inner surface of the high aspect ratio holes which may be filled with air or a material with an index of refraction that is greater than 1. These metal confined waveguides are used to transmit signals between functional circuits on the semiconductor wafer and functional circuits on the back of the wafer or beneath the wafer.
摘要翻译：具有形成在高纵横比孔中的多个光波导的集成电路。高纵横比孔延伸穿过半导体晶片。光波导包括高反射材料，其被沉积以便可以填充空气的高纵横比孔的内表面或具有大于1的折射率的材料。这些金属限制波导被使用以在半导体晶片上的功能电路和晶片的背面或晶片之下的功能电路之间传输信号。

3. 发明授权

US07084451B2 Circuits with a trench capacitor having micro-roughened semiconductor surfaces 失效
标题翻译：具有具有微粗糙化半导体表面的沟槽电容器的电路
公开(公告)号：US07084451B2
公开(公告)日：2006-08-01
申请号：US09467992
申请日：1999-12-20
申请人： Leonard Forbes , Joseph E. Geusic , Kie Y. Ahn
发明人： Leonard Forbes , Joseph E. Geusic , Kie Y. Ahn
IPC分类号： H01L27/108
CPC分类号： H01L27/10861 , H01L28/82 , H01L29/66181
摘要： A method for forming a trench capacitor. The method includes forming a trench in a semiconductor substrate. A conformal layer of semiconductor material is deposited in the trench. The surface of the conformal layer of semiconductor material is roughened. An insulator layer is formed outwardly from the roughened, conformal layer of semiconductor material. A polycrystalline semiconductor plate is formed outwardly from the insulator layer in the trench.
摘要翻译：一种形成沟槽电容器的方法。该方法包括在半导体衬底中形成沟槽。半导体材料的保形层沉积在沟槽中。半导体材料的共形层的表面被粗糙化。从粗糙化的半导体材料的保形层向外形成绝缘体层。多晶半导体板从沟槽中的绝缘体层向外形成。

4. 发明授权

US06723577B1 Method of forming an optical fiber interconnect through a semiconductor wafer 失效
标题翻译：通过半导体晶片形成光纤互连的方法
公开(公告)号：US06723577B1
公开(公告)日：2004-04-20
申请号：US09650569
申请日：2000-08-30
申请人： Joseph E. Geusic , Kie Y. Ahn , Leonard Forbes
发明人： Joseph E. Geusic , Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L2100
CPC分类号： G02B6/43 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit with a number of optical fibers that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical fibers include a cladding layer and a core formed in the high aspect ratio hole. These optical fibers are used to transmit signals between functional circuits on the semiconductor wafer and functional circuits on the back of the wafer or beneath the wafer.
摘要翻译：具有形成在高纵横比孔中的多根光纤的集成电路。高纵横比孔延伸穿过半导体晶片。光纤包括形成在高纵横比孔中的包覆层和芯。这些光纤用于在半导体晶片上的功能电路和晶片背面或晶片之下的功能电路之间传输信号。

5. 发明授权

US06518615B1 Method and structure for high capacitance memory cells 有权
公开(公告)号：US06518615B1
公开(公告)日：2003-02-11
申请号：US09137896
申请日：1998-08-20
申请人： Joseph E. Geusic , Leonard Forbes , Kie Y. Ahn
发明人： Joseph E. Geusic , Leonard Forbes , Kie Y. Ahn
IPC分类号： H01L27108
CPC分类号： B82Y10/00 , B82Y30/00 , H01L27/1087 , Y10S977/888 , Y10S977/943
摘要： A method and structure for high capacitance memory cells is provided. The method includes forming a trench capacitor in a semiconductor substrate. A self-structured mask is formed on the interior surface of the trench. The interior surface of the trench is etched to form an array of silicon pillars. The self-structured mask is removed. Then an insulator layer is formed on the array of silicon pillars. A polycrystalline semiconductor plate extends outwardly from the insulator layer in the trench.

6. 发明授权

US06496370B2 Structure and method for an electronic assembly 有权
标题翻译：电子组件的结构和方法
公开(公告)号：US06496370B2
公开(公告)日：2002-12-17
申请号：US09836564
申请日：2001-04-17
申请人： Joseph E. Geusic , Leonard Forbes , Kie Y. Ahn
发明人： Joseph E. Geusic , Leonard Forbes , Kie Y. Ahn
IPC分类号： H05K720
CPC分类号： H01L23/473 , H01L2924/0002 , H05K1/0272 , H01L2924/00
摘要： An electronic assembly is provided. The electronic assembly includes a semiconductor interposer having first and second surfaces. The semiconductor interposer also has cooling channels passing through the interposer between the first and second surfaces. The electronic assembly has at least one semiconductor chip disposed outwardly from the first surface of the semiconductor interposer and at least one semiconductor chip disposed outwardly from the second surface of the semiconductor interposer. The electronic assembly also has a number of electrical connections through the semiconductor interposer wherein the number of electrical connections couple the semiconductor chips disposed outwardly from the first and second surfaces of the semiconductor interposer.
摘要翻译：提供电子组件。电子组件包括具有第一和第二表面的半导体插入器。半导体插入器还具有通过第一和第二表面之间的插入件的冷却通道。电子组件具有从半导体插入件的第一表面向外设置的至少一个半导体芯片和从半导体插入器的第二表面向外设置的至少一个半导体芯片。电子组件还具有通过半导体插入器的多个电连接，其中电连接的数量耦合从半导体插入器的第一和第二表面向外设置的半导体芯片。

7. 发明授权

US07300821B2 Integrated circuit cooling and insulating device and method 有权
公开(公告)号：US07300821B2
公开(公告)日：2007-11-27
申请号：US10930252
申请日：2004-08-31
申请人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
发明人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
IPC分类号： H01L21/00
CPC分类号： H01L23/427 , G01R31/2817 , H01L2924/0002 , H01L2924/00
摘要： A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.

8. 发明授权

US06950338B1 Method for operating a memory device having an amorphous silicon carbide gate insulator 失效
公开(公告)号：US06950338B1
公开(公告)日：2005-09-27
申请号：US09135413
申请日：1998-08-14
申请人： Leonard Forbes , Joseph E. Geusic , Kie Y. Ahn
发明人： Leonard Forbes , Joseph E. Geusic , Kie Y. Ahn
摘要： A floating gate transistor has a reduced barrier energy at an interface with an adjacent amorphous silicon carbide (a-SiC) gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.

9. 发明授权

US06777715B1 Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same 有权
标题翻译：使用通过半导体晶片形成的光波导互连的集成电路及其形成方法
公开(公告)号：US06777715B1
公开(公告)日：2004-08-17
申请号：US09618648
申请日：2000-07-18
申请人： Joseph E. Geusic , Kie Y. Ahn , Leonard Forbes
发明人： Joseph E. Geusic , Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L2715
CPC分类号： G02B6/032 , G02B6/12002 , G02B6/136 , G02B6/42 , G02B6/43
摘要： An integrated circuit with a number of optical waveguides that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical waveguides include a highly reflective material that is deposited so as to line an inner surface of the high aspect ratio holes which may be filled with air or a material with an index of refraction that is greater than 1. These metal confined waveguides are used to transmit signals between functional circuits on the semiconductor wafer and functional circuits on the back of the wafer or beneath the wafer.
摘要翻译：具有形成在高纵横比孔中的多个光波导的集成电路。高纵横比孔延伸穿过半导体晶片。光波导包括高反射材料，其被沉积以便可以填充空气的高纵横比孔的内表面或具有大于1的折射率的材料。这些金属限制波导被使用以在半导体晶片上的功能电路和晶片的背面或晶片之下的功能电路之间传输信号。

10. 发明授权

US06309907B1 Method of fabricating transistor with silicon oxycarbide gate 有权
标题翻译：用硅碳化硅栅制造晶体管的方法
公开(公告)号：US06309907B1
公开(公告)日：2001-10-30
申请号：US09138294
申请日：1998-08-21
申请人： Leonard Forbes , Joseph E. Geusic , Kie Y. Ahn
发明人： Leonard Forbes , Joseph E. Geusic , Kie Y. Ahn
IPC分类号： H01L2100
CPC分类号： H01L29/66825 , H01L21/28088 , H01L21/28273 , H01L29/42324 , H01L29/4966 , H01L31/113
摘要： A CMOS-compatible FET has a reduced electron affinity polycrystalline or microcrystalline silicon oxycarbide (SiOC) gate that is electrically isolated (floating) or interconnected. The SiOC material composition is selected to establish a desired barrier energy between the SiOC gate and a gate insulator. In a memory application, such as a flash EEPROM, the SiOC composition is selected to establish a lower barrier energy to reduce write and erase voltages and times or accommodate the particular data charge retention time needed for the particular application. In a light detector or imaging application, the SiOC composition is selected to provide sensitivity to the desired wavelength of light. Unlike conventional photodetectors, light is absorbed in the floating gate, thereby ejecting previously stored electrons therefrom. Also unlike conventional photodetectors, the light detector according to the present invention is actually more sensitive to lower energy photons as the semiconductor bandgap is increased.
摘要翻译： CMOS兼容的FET具有电隔离（浮置）或互连的减少的电子亲和性多晶或微晶硅氧化碳（SiOC）栅极。选择SiOC材料组成以在SiOC栅极和栅极绝缘体之间建立期望的势垒能。在诸如闪存EEPROM的存储器应用中，选择SiOC组合以建立较低的势垒能量以减少写入和擦除电压和时间或适应特定应用所需的特定数据电荷保留时间。在光检测器或成像应用中，选择SiOC组合以提供对期望波长的光的灵敏度。与常规光电探测器不同，光在浮动栅极中被吸收，从而从其中喷射预先存储的电子。与常规光电探测器不同，当半导体带隙增加时，根据本发明的光检测器实际上对较低能量的光子更敏感。

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