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51. 发明授权

US5907776A Method of forming a semiconductor structure having reduced threshold voltage and high punch-through tolerance 失效
标题翻译：形成具有降低的阈值电压和高穿透公差的半导体结构的方法
公开(公告)号：US5907776A
公开(公告)日：1999-05-25
申请号：US891546
申请日：1997-07-11
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/1095
摘要： A power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device formed on a semiconductor substrate having a body region of a first conductivity type diffused in a semiconductor substrate with an epitaxial layer of a second conductivity type. There is also a source region of a second conductivity type formed in the body region. A portion of the body region adjacent to the source region is compensated by ion implanting a material of the second conductivity type in the portion of the body region such that the impurity concentration of the body region at the portion is reduced. As a consequence, with reduced impurity charge in the body region adjacent to the source, the threshold voltage of the MOSFET device is lowered but at no comprise in punch-through tolerance because the reduction in charge is remote from the origin of the depletion layer which is located at the boundary between the body region and the epitaxial layer.
摘要翻译：一种在半导体衬底上形成的功率MOSFET（金属氧化物半导体场效应晶体管）器件，其具有扩散在具有第二导电类型的外延层的半导体衬底中的第一导电类型的体区。还有在身体区域中形成的第二导电类型的源区。通过在身体区域的部分中离子注入第二导电类型的材料来补偿与源极区域相邻的身体区域的一部分，使得该部分处的体区域的杂质浓度降低。因此，随着与源极相邻的体区中的杂质电荷减少，MOSFET器件的阈值电压降低，但不包括穿通公差，因为电荷的减少远离耗尽层的原点，位于体区和外延层之间的边界处。

52. 发明授权

US07052982B2 Method for manufacturing a superjunction device with wide mesas 失效
标题翻译：制造具有宽台面的超级结装置的方法
公开(公告)号：US07052982B2
公开(公告)日：2006-05-30
申请号：US11017468
申请日：2004-12-20
申请人： Fwu-Iuan Hshieh , Koon Chong So , Brian D. Pratt
发明人： Fwu-Iuan Hshieh , Koon Chong So , Brian D. Pratt
IPC分类号： H01L21/425
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/66143 , H01L29/66712 , H01L29/66734 , H01L29/7811 , H01L29/7813 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device includes providing semiconductor substrate having trenches and mesas. At least one mesa has first and second sidewalls. The method includes angularly implanting a dopant of a second conductivity into the first sidewall, and angularly implanting a dopant of a second conductivity into the second sidewall. The at least one mesa is converted to a pillar by diffusing the dopants into the at least one mesa. The pillar is then converted to a column by angularly implanting a dopant of the first conductivity into a first sidewall of the pillar, and by angularly implanting the dopant of the first conductivity type into a second sidewall of the pillar. The dopants are then diffused into the pillar to provide a P-N junction of the first and second doped regions located along the depth direction of the adjoining trench. Finally, the trenches are filled with an insulating material.
摘要翻译：制造半导体器件的方法包括提供具有沟槽和台面的半导体衬底。至少一个台面具有第一和第二侧壁。该方法包括将第二导电性的掺杂剂角度地注入到第一侧壁中，并将第二导电性的掺杂剂角度地注入第二侧壁。通过将掺杂剂扩散到至少一个台面中，将至少一个台面转变成柱。然后通过将第一导电性的掺杂剂角度地注入到柱的第一侧壁中，并且将第一导电类型的掺杂剂角度地注入到柱的第二侧壁中，将柱转换成列。然后将掺杂剂扩散到柱中以提供沿相邻沟槽的深度方向定位的第一和第二掺杂区的P-N结。最后，沟槽填充绝缘材料。

53. 发明授权

US06777745B2 Symmetric trench MOSFET device and method of making same 有权
标题翻译：对称沟槽MOSFET器件及其制造方法
公开(公告)号：US06777745B2
公开(公告)日：2004-08-17
申请号：US09881254
申请日：2001-06-14
申请人： Fwu-Iuan Hshieh , Koon Chong So , Richard A. Blanchard
发明人： Fwu-Iuan Hshieh , Koon Chong So , Richard A. Blanchard
IPC分类号： H01L2976
CPC分类号： H01L29/66666 , H01L21/823487 , H01L27/088 , H01L29/42376 , H01L29/51 , H01L29/7827
摘要： A trench MOSFET transistor device and method of making the same are provided. The trench MOSFET transistor device comprises: (a) a drain region of first conductivity type; (b) a body region of a second conductivity type provided over the drain region, such that the drain region and the body region form a first junction; (c) a source region of the first conductivity type provided over the body region, such that the source region and the body region form a second junction; (d) source metal disposed on an upper surface of the source region; (e) a trench extending through the source region, through the body region and into the drain region; and (f) a gate region comprising (i) an insulating layer, which lines at least a portion of the trench and (ii) a conductive region, which is disposed within the trench adjacent the insulating layer. The body region in this device is separated from the source metal. Moreover, the doping profile within the body region and within at least a portion of the source and drain regions, when taken along a line normal to upper and lower surfaces of the device, is such that the doping profile on one side of a centerplane of the body region is symmetric with the doping profile on an opposite side of the centerplane.
摘要翻译：提供了一种沟槽MOSFET晶体管器件及其制造方法。沟槽MOSFET晶体管器件包括：（a）第一导电类型的漏极区; （b）设置在漏区上的第二导电类型的体区，使得漏区和体区形成第一结; （c）提供在身体区域上的第一导电类型的源区，使得源区和体区形成第二结; （d）设置在源极区域的上表面上的源极金属; （e）延伸穿过源区域的沟槽，穿过本体区域并进入漏极区域; 和（f）栅极区域，其包括（i）绝缘层，其在沟槽中的至少一部分上划线，以及（ii）导电区域，其设置在邻近绝缘层的沟槽内。该设备中的身体区域与源金属分离。此外，当沿着垂直于器件的上表面和下表面的线截取时，体区内和源极和漏极区域的至少一部分内的掺杂分布使得在中心平面的一侧的掺杂分布身体区域与中心平面的相对侧上的掺杂分布对称。

54. 发明授权

US06770548B2 Trench schottky rectifier 有权
公开(公告)号：US06770548B2
公开(公告)日：2004-08-03
申请号：US10429817
申请日：2003-05-05
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L2128
CPC分类号： H01L29/417 , H01L27/0817 , H01L27/095 , H01L29/42364 , H01L29/66143 , H01L29/872 , H01L29/8725
摘要： A Schottky rectifier is provided. The Schottky rectifier comprises: (a) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region of first conductivity type adjacent the first face and a drift region of the first conductivity type adjacent the second face, and with the drift region having a lower net doping concentration than that of the cathode region; (b) one or more trenches extending from the second face into the semiconductor region and defining one or more mesas within the semiconductor region; (c) an insulating region adjacent the semiconductor region in lower portions of the trench; (d) and an anode electrode that is (i) adjacent to and forms a Schottky rectifying contact with the semiconductor at the second face, (ii) adjacent to and forms a Schottky rectifying contact with the semiconductor region within upper portions of the trench and (iii) adjacent to the insulating region within the lower portions of the trench.

55. 发明授权

US06657256B2 Trench DMOS transistor having a zener diode for protection from electro-static discharge 有权
公开(公告)号：US06657256B2
公开(公告)日：2003-12-02
申请号：US09862541
申请日：2001-05-22
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L2994
CPC分类号： H01L29/7813 , H01L29/4916 , H01L29/7808 , H01L2924/0002 , H01L2924/00
摘要： A trench DMOS transistor having overvoltage protection includes a substrate of a first conductivity type and a body region of a second conductivity type formed over the substrate. At least one trench extends through the body region and the substrate. An insulating layer lines the trench and overlies the body region. A conductive electrode is deposited in the trench so that it overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench. An undoped polysilicon layer overlies a portion of the insulating layer. A plurality of cathode regions of the first conductivity type are formed in the undoped polysilicon layer. At least one anode region is in contact with adjacent ones of the plurality of cathode regions.

56. 发明授权

US06645815B2 Method for forming trench MOSFET device with low parasitic resistance 有权
公开(公告)号：US06645815B2
公开(公告)日：2003-11-11
申请号：US10010483
申请日：2001-11-20
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Brian D. Pratt
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Brian D. Pratt
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L21/823487 , H01L29/1095 , Y10S148/126
摘要： A method is provided for forming shallow and deep dopant implants adjacent source regions of a first conductivity type within an upper portion of an epitaxial layer in a trench MOSFET device. The method comprises: (a) forming a patterned implantation mask over the epitaxial layer, wherein the patterned implantation mask comprises a patterned insulating region and covers at least a portion of the source regions, and wherein the patterned implantation mask has apertures over at least portions of the epitaxial layer adjacent the source regions; (b) forming shallow dopant regions by a process comprising: (1) implanting a first dopant of a second conductivity type at a first energy level within an upper portion of the epitaxial layer through the apertures and (2) diffusing the first dopant at elevated temperatures to a first depth from an upper surface of the epitaxial layer; (c) forming deep dopant regions by a process comprising: (1) implanting a second dopant of the second conductivity type at a second energy level within an upper portion of the epitaxial layer through the apertures and (2) diffusing the second dopant at elevated temperatures to a second depth from the upper surface of the epitaxial layer; and (d) enlarging apertures in the patterned insulating region. In this method, the second energy level is greater than the first energy level, the second depth is greater than the first depth, and the first and second dopants can be the same or different. The method of the present invention can be used, for example, to form a device that comprises a plurality of trench MOSFET cells.

57. 发明授权

US06580141B2 Trench schottky rectifier 有权
公开(公告)号：US06580141B2
公开(公告)日：2003-06-17
申请号：US09872926
申请日：2001-06-01
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L2947
CPC分类号： H01L29/417 , H01L27/0817 , H01L27/095 , H01L29/42364 , H01L29/66143 , H01L29/872 , H01L29/8725
摘要： A Schottky rectifier is provided. The Schottky rectifier comprises: (a) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region of first conductivity type adjacent the first face and a drift region of the first conductivity type adjacent the second face, and with the drift region having a lower net doping concentration than that of the cathode region; (b) one or more trenches extending from the second face into the semiconductor region and defining one or more mesas within the semiconductor region; (c) an insulating region adjacent the semiconductor region in lower portions of the trench; (d) and an anode electrode that is (i) adjacent to and forms a Schottky rectifying contact with the semiconductor at the second face, (ii) adjacent to and forms a Schottky rectifying contact with the semiconductor region within upper portions of the trench and (iii) adjacent to the insulating region within the lower portions of the trench.

58. 发明授权

US06545315B2 Trench DMOS transistor having reduced punch-through 失效
标题翻译：沟槽DMOS晶体管减少了穿通
公开(公告)号：US06545315B2
公开(公告)日：2003-04-08
申请号：US09798451
申请日：2001-03-02
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4916
摘要： A method of forming a trench DMOS transistor is provides which reduces punch-through. The method begins by providing a substrate of a first conductivity type. A body region, which has a second conductivity type, is formed on the substrate. A masking layer is formed which defines at least one trench. Next, the trench and an insulating layer that lines the trench are formed. A conductive electrode is then formed in the trench, which overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench. The step of forming the trench includes the steps of etching the trench and smoothing the sidewalls of the trench with a sacrificial oxide layer before removal of the masking layer that defines the trench.
摘要翻译：提供了形成沟槽DMOS晶体管的方法，其减少了穿通。该方法开始于提供第一导电类型的衬底。在基板上形成具有第二导电类型的主体区域。形成限定至少一个沟槽的掩模层。接下来，形成沟槽和对沟槽进行排列的绝缘层。然后在沟槽中形成导电电极，其覆盖绝缘层。第一导电类型的源区形成在与沟槽相邻的体区中。形成沟槽的步骤包括以下步骤：在去除限定沟槽的掩模层之前，用牺牲氧化物层蚀刻沟槽并平滑沟槽的侧壁。

59. 发明授权

US06518128B2 Trench MOSFET with double-diffused body profile 失效
标题翻译：具有双扩散体轮廓的沟槽MOSFET
公开(公告)号：US06518128B2
公开(公告)日：2003-02-11
申请号：US09881253
申请日：2001-06-14
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/7811
摘要： A trench MOSFET device and process for making the same are described. The trench MOSFET has a substrate of a first conductivity type, an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate, a plurality of trenches within the epitaxial layer, a first insulating layer, such as an oxide layer, lining the trenches, a conductive region, such as a polycrystalline silicon region, within the trenches adjacent to the first insulating layer, and one or more trench body regions and one or more termination body regions provided within an upper portion of the epitaxial layer, the termination body regions extending into the epitaxial layer to a greater depth than the trench body regions. Each trench body region and each termination body region has a first region of a second conductivity type, the second conductivity type being opposite the first conductivity type, and a second region of the second conductivity type adjacent the first region, the second region having a greater majority carrier concentration than the first region, and the second region being disposed above the first region and adjacent and extending to an outer wall of one of said plurality of trenches. A plurality of source regions of the first conductivity type are positioned adjacent the trenches within upper portions the trench.
摘要翻译：描述了沟槽MOSFET器件及其制造方法。沟槽MOSFET具有第一导电类型的衬底，在衬底上的第一导电类型的外延层，外延层具有比衬底更低的多数载流子浓度，外延层内的多个沟槽，第一绝缘层，诸如沟槽衬里的氧化物层，在与第一绝缘层相邻的沟槽内的导电区域，例如多晶硅区域，以及一个或多个沟槽体区域和设置在上部的一个或多个端接体区域外延层的一部分，终端体区域延伸到外延层中比沟槽体区域更深的深度。每个沟槽体区域和每个终端体区域具有第二导电类型的第一区域，第二导电类型与第一导电类型相反，第二导电类型的第二区域与第一区域相邻，第二区域具有更大的多数载流子浓度比第一区域多，第二区域设置在第一区域上方并且相邻并延伸到所述多个沟槽中的一个沟槽的外壁。第一导电类型的多个源极区域在沟槽的上部内邻近沟槽定位。

60. 发明授权

US06281547B1 Power transistor cells provided with reliable trenched source contacts connected to narrower source manufactured without a source mask 失效
标题翻译：功率晶体管单元提供可靠的沟槽源触点，连接到较窄的源，而不需要源掩码
公开(公告)号：US06281547B1
公开(公告)日：2001-08-28
申请号：US08853150
申请日：1997-05-08
申请人： Koon Chong So , Fwu-Iuan Hshieh
发明人： Koon Chong So , Fwu-Iuan Hshieh
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/0649 , H01L29/0696 , H01L29/402 , H01L29/407 , H01L29/41741
摘要： The present invention discloses a DMOS transistor cell, supported on a substrate of a first conductivity type. The DMOS transistor cell includes a body region of a second conductivity type disposed in the substrate defining a central portion of the cell. This DMOS transistor cell further includes a trench gate filled with polysilicon therein surrounding the body region and defining a boundary of the cell. This DMOS transistor cell further includes a source of the first conductivity type defined by a narrow strip of source region disposed in the body region along an edge thereof adjacent to the trench gate. This transistor cell further includes a source contact defined by a cross-shaped trench filled with polysilicon disposed in the body region and a trench edge source extension extending laterally between the narrow strip of source region and in electric contact thereto for providing area for electrically connecting to a source contact to be formed thereon whereby the source contact can be more conveniently manufactured provided with reliable good contact to the narrow strip of source region while achieving cost savings without requiring the use of a source mask.
摘要翻译：本发明公开了一种负载在第一导电类型的衬底上的DMOS晶体管单元。 DMOS晶体管单元包括设置在衬底中的限定电池的中心部分的第二导电类型的体区。该DMOS晶体管单元还包括填充有多晶硅的沟槽栅极，其围绕主体区域并且限定电池的边界。该DMOS晶体管单元还包括由邻近沟槽栅极的边缘设置在主体区域中的源区的窄条限定的第一导电类型的源。该晶体管单元还包括由填充有设置在主体区域中的多晶硅的十字形沟槽限定的源极接触，以及在狭窄的源区域之间横向延伸并与其电接触的沟槽边缘源延伸部，用于提供用于电连接到在其上形成的源极接触件，其中可以更方便地制造源极接触件，其提供与狭窄的源极区域的可靠的良好接触，同时实现成本节约而不需要使用源极掩模。

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