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1. 发明授权

US07364994B2 Method for manufacturing a superjunction device with wide mesas 失效
标题翻译：制造具有宽台面的超级结装置的方法
公开(公告)号：US07364994B2
公开(公告)日：2008-04-29
申请号：US11420490
申请日：2006-05-26
申请人： Fwu-Iuan Hshieh , Koon Chong So , Brian D. Pratt
发明人： Fwu-Iuan Hshieh , Koon Chong So , Brian D. Pratt
IPC分类号： H01L21/425 , H01L21/336 , H01L21/332 , H01L21/44 , H01L23/58
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/66143 , H01L29/66712 , H01L29/66734 , H01L29/7811 , H01L29/7813 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device includes providing semiconductor substrate having trenches and mesas. At least one mesa has first and second sidewalls. The method includes angularly implanting a dopant of a second conductivity into the first sidewall, and angularly implanting a dopant of a second conductivity into the second sidewall. The at least one mesa is converted to a pillar by diffusing the dopants into the at least one mesa. The pillar is then converted to a column by angularly implanting a dopant of the first conductivity into a first sidewall of the pillar, and by angularly implanting the dopant of the first conductivity type into a second sidewall of the pillar. The dopants are then diffused into the pillar to provide a P-N junction of the first and second doped regions located along the depth direction of the adjoining trench. Finally, the trenches are filled with an insulating material.
摘要翻译：制造半导体器件的方法包括提供具有沟槽和台面的半导体衬底。至少一个台面具有第一和第二侧壁。该方法包括将第二导电性的掺杂剂角度地注入到第一侧壁中，并将第二导电性的掺杂剂角度地注入第二侧壁。通过将掺杂剂扩散到至少一个台面中，将至少一个台面转变成柱。然后通过将第一导电性的掺杂剂角度地注入到柱的第一侧壁中，并且将第一导电类型的掺杂剂角度地注入到柱的第二侧壁中，将柱转换成列。然后将掺杂剂扩散到柱中以提供沿相邻沟槽的深度方向定位的第一和第二掺杂区的P-N结。最后，沟槽填充绝缘材料。

2. 发明授权

US07015125B2 Trench MOSFET device with polycrystalline silicon source contact structure 失效
公开(公告)号：US07015125B2
公开(公告)日：2006-03-21
申请号：US10983490
申请日：2004-11-08
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
IPC分类号： H01L21/4763 , H01L21/336 , H01L21/8242
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/456
摘要： A trench MOSFET transistor device and a method of making the same. The device comprises: (a) a silicon substrate of first conductivity type; (b) a silicon epitaxial layer of first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type provided within an upper portion of the body region and adjacent the trench; (h) an upper region of second conductivity type within an upper portion of the body region and adjacent the source region, the upper region having a higher majority carrier concentration than the body region; and (i) a source contact region disposed on the epitaxial layer upper surface, wherein the source contact region comprises a doped polycrystalline silicon contact region in electrical contact with the source region as well as an adjacent metal contact region in electrical contact with the source region and with the upper region.

3. 发明授权

US06884683B2 Trench DMOS transistor having a zener diode for protection from electro-static discharge 有权
标题翻译：沟槽DMOS晶体管具有用于防止静电放电的齐纳二极管
公开(公告)号：US06884683B2
公开(公告)日：2005-04-26
申请号：US10714807
申请日：2003-11-18
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L27/04 , H01L21/336 , H01L21/822 , H01L21/8234 , H01L27/06 , H01L29/49 , H01L29/78 , H01L29/866
CPC分类号： H01L29/7813 , H01L29/4916 , H01L29/7808 , H01L2924/0002 , H01L2924/00
摘要： A trench DMOS transistor having overvoltage protection includes a substrate of a first conductivity type and a body region of a second conductivity type formed over the substrate. At least one trench extends through the body region and the substrate. An insulating layer lines the trench and overlies the body region. A conductive electrode is deposited in the trench so that it overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench. An undoped polysilicon layer overlies a portion of the insulating layer. A plurality of cathode regions of the first conductivity type are formed in the undoped polysilicon layer. At least one anode region is in contact with adjacent ones of the plurality of cathode regions.
摘要翻译：具有过电压保护的沟槽DMOS晶体管包括形成在衬底上的第一导电类型的衬底和第二导电类型的体区。至少一个沟槽延伸穿过身体区域和衬底。绝缘层在沟槽上划线并覆盖在身体区域上。导电电极沉积在沟槽中，使其覆盖绝缘层。第一导电类型的源区形成在与沟槽相邻的体区中。未掺杂的多晶硅层覆盖绝缘层的一部分。在未掺杂多晶硅层中形成第一导电类型的多个阴极区。至少一个阳极区域与多个阴极区域中的相邻阳极区域接触。

4. 发明授权

US06762098B2 Trench DMOS transistor with embedded trench schottky rectifier 有权
标题翻译：沟槽DMOS晶体管采用嵌入式沟道肖特基整流器
公开(公告)号：US06762098B2
公开(公告)日：2004-07-13
申请号：US10448791
申请日：2003-05-30
申请人： Fwu-Iuan Hshieh , Yan Man Tsui , Koon Chong So
发明人： Fwu-Iuan Hshieh , Yan Man Tsui , Koon Chong So
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L27/0629 , H01L29/7806 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit having a plurality of trench Schottky barrier rectifiers within one or more rectifier regions and a plurality of trench DMOS transistors within one or more transistor regions. The integrated circuit comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of the first conductivity type over the substrate, wherein the epitaxial layer has a lower doping level than the substrate; (c) a plurality of body regions of a second conductivity type within the epitaxial layer in the transistor regions; (d) a plurality of trenches within the epitaxial layer in both the transistor regions and the rectifier regions; (e) a first insulating layer that lines the trenches; (f) a polysilicon conductor within the trenches and overlying the first insulating layer; (g) a plurality of source regions of the first conductivity type within the body regions at a location adjacent to the trenches; (h) a second insulating layer over the doped polysilicon layer in the transistor regions; and (i) an electrode layer over both the transistor regions and the rectifier regions.
摘要翻译：一种在一个或多个整流器区域内具有多个沟道肖特基势垒整流器的集成电路以及一个或多个晶体管区域内的多个沟槽DMOS晶体管。集成电路包括：（a）第一导电类型的衬底; （b）在所述衬底上的第一导电类型的外延层，其中所述外延层具有比所述衬底更低的掺杂水平; （c）晶体管区域中的外延层内的第二导电类型的多个体区; （d）在所述晶体管区域和所述整流器区域中的所述外延层内的多个沟槽;（e）对所述沟槽进行排列的第一绝缘层; （f）沟槽内的多晶硅导体并覆盖第一绝缘层; （g）在与所述沟槽相邻的位置处的所述主体区域内的所述第一导电类型的多个源极区域; （h）晶体管区域上的掺杂多晶硅层上的第二绝缘层; 和（i）在晶体管区域和整流器区域上的电极层。

5. 发明授权

US06657254B2 Trench MOSFET device with improved on-resistance 有权
公开(公告)号：US06657254B2
公开(公告)日：2003-12-02
申请号：US09999116
申请日：2001-11-21
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/0878
摘要： A trench MOSFET device and method of making the same. The trench MOSFET device comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of the first conductivity type over the substrate, wherein the epitaxial layer has a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial region from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a doped region of the first conductivity type formed within the epitaxial layer between a bottom portion of the trench and the substrate, wherein the doped region has a majority carrier concentration that is lower than that of the substrate and higher than that of the epitaxial layer; (g) a body region of a second conductivity type formed within an upper portion of the epitaxial layer and adjacent the trench, wherein the body region extends to a lesser depth from the upper surface of the epitaxial layer than does the trench; and (h) a source region of the first conductivity type formed within an upper portion of the body region and adjacent the trench. The presence of the doped region lying between the bottom portion of the trench and the substrate (also referred to herein as a “trench bottom implant”) serves to reduce the on-resistance of the device.

6. 发明授权

US06627951B2 High speed trench DMOS 有权
标题翻译：高速沟DMOS
公开(公告)号：US06627951B2
公开(公告)日：2003-09-30
申请号：US09882117
申请日：2001-06-15
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/4232 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4916 , H01L29/4925 , H01L29/4933
摘要： A method for making trench DMOS is provided that utilizes polycide and refractory techniques to make trench DMOS which exhibit low gate resistance, low gate capacitance, reduced distributed RC gate propagation delay, and improved switching speeds for high frequency applications.
摘要翻译：提供了制造沟槽DMOS的方法，其利用多硅化物和难熔技术来制造出具有低栅极电阻，低栅极电容，降低的分布式RC栅极传播延迟以及用于高频应用的改进的开关速度的沟槽DMOS。

7. 发明授权

US06518152B2 Method of forming a trench schottky rectifier 失效
标题翻译：形成沟槽肖特基整流器的方法
公开(公告)号：US06518152B2
公开(公告)日：2003-02-11
申请号：US10043633
申请日：2002-01-10
申请人： Fwu-Iuan Hshieh , Max Chen , Koon Chong So , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Max Chen , Koon Chong So , Yan Man Tsui
IPC分类号： H01L2128
CPC分类号： H01L29/8725 , H01L29/872
摘要： A Schottky rectifier is provided. The Schottky rectifier comprises: (a) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region of first conductivity type adjacent the first face and a drift region of the first conductivity type adjacent the second face, and with the drift region having a lower net doping concentration than that of the cathode region; (b) one or more trenches extending from the second face into the semiconductor region and defining one or more mesas within the semiconductor region; (c) an insulating region adjacent the semiconductor region in lower portions of the trench; (d) and an anode electrode that is (i) adjacent to and forms a Schottky rectifying contact with the semiconductor at the second face, (ii) adjacent to and forms a Schottky rectifying contact with the semiconductor region within upper portions of the trench and (iii) adjacent to the insulating region within the lower portions of the trench.
摘要翻译：提供肖特基整流器。肖特基整流器包括：（a）具有第一和第二相对面的半导体区域，半导体区域包括邻近第一面的第一导电类型的阴极区域和与第二面相邻的第一导电类型的漂移区域，以及漂移区具有比阴极区更低的净掺杂浓度; （b）从所述第二面延伸到所述半导体区域并限定所述半导体区域内的一个或多个台面的一个或多个沟槽; （c）与沟槽下部的半导体区相邻的绝缘区; （d）和阳极电极（i）在第二面处与半导体相邻并形成肖特基整流接触，（ii）与沟槽上部的半导体区域相邻并形成肖特基整流接触，以及（iii）与沟槽下部的绝缘区域相邻。

8. 发明授权

US06472678B1 Trench MOSFET with double-diffused body profile 有权
标题翻译：具有双扩散体轮廓的沟槽MOSFET
公开(公告)号：US06472678B1
公开(公告)日：2002-10-29
申请号：US09595486
申请日：2000-06-16
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/7811
摘要： A trench MOSFET device and process for making the same are described. The trench MOSFET has a substrate of a first conductivity type, an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate, a plurality of trenches within the epitaxial layer, a first insulating layer, such as an oxide layer, lining the trenches, a conductive region, such as a polycrystalline silicon region, within the trenches adjacent to the first insulating layer, and one or more trench body regions and one or more termination body regions provided within an upper portion of the epitaxial layer, the termination body regions extending into the epitaxial layer to a greater depth than the trench body regions. Each trench body region and each termination body region has a first region of a second conductivity type, the second conductivity type being opposite the first conductivity type, and a second region of the second conductivity type adjacent the first region, the second region having a greater majority carrier concentration than the first region, and the second region being disposed above the first region and adjacent and extending to an outer wall of each of the plurality of trenches. A plurality of source regions of the first conductivity type are positioned adjacent the trenches within upper portions the trench body regions.
摘要翻译：描述了沟槽MOSFET器件及其制造方法。沟槽MOSFET具有第一导电类型的衬底，在衬底上的第一导电类型的外延层，外延层具有比衬底更低的多数载流子浓度，外延层内的多个沟槽，第一绝缘层，诸如沟槽衬里的氧化物层，在与第一绝缘层相邻的沟槽内的导电区域，例如多晶硅区域，以及一个或多个沟槽体区域和设置在上部的一个或多个端接体区域外延层的一部分，终端体区域延伸到外延层中比沟槽体区域更深的深度。每个沟槽体区域和每个终端体区域具有第二导电类型的第一区域，第二导电类型与第一导电类型相反，第二导电类型的第二区域与第一区域相邻，第二区域具有更大的多数载流子浓度比第一区域多，并且第二区域设置在第一区域上方并且相邻并延伸到多个沟槽中的每一个的外壁。第一导电类型的多个源极区域位于沟槽体区域的上部内的沟槽附近。

9. 发明授权

US5895951A MOSFET structure and fabrication process implemented by forming deep and narrow doping regions through doping trenches 失效
标题翻译：通过掺杂沟槽形成深而窄的掺杂区域来实现MOSFET结构和制造工艺
公开(公告)号：US5895951A
公开(公告)日：1999-04-20
申请号：US628493
申请日：1996-04-05
申请人： Koon Chong So , Yan Man Tsui , Fwu-Iuan Hshieh , True-Lon Lin , Danny Chi Nim
发明人： Koon Chong So , Yan Man Tsui , Fwu-Iuan Hshieh , True-Lon Lin , Danny Chi Nim
IPC分类号： H01L21/336 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/40 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/407 , H01L29/0696 , H01L29/0847
摘要： This invention discloses a MOSFET device which includes a plurality of vertical cells each includes a source, a drain, and a channel for conducting source-to-drain current therethrough. Each of the vertical cells is surrounded by a polysilicon layer acting as a gate for controlling the source-to-drain current through the channel. The MOSFET device further include a plurality of doping trenches filled with trench-filling materials, The MOSFET device further includes a plurality of deep-doped regions disposed underneath the doping trenches wherein the deep-doped region extends downwardly to a depth which is substantially a sum of an implant depth of the deep-doped region and a vertical diffusion depth below a bottom of the doping trenches.
摘要翻译：本发明公开了一种MOSFET器件，其包括多个垂直单元，每个垂直单元包括源极，漏极和用于通过其传导源极 - 漏极电流的沟道。每个垂直单元被用作控制通过通道的源极 - 漏极电流的栅极的多晶硅层包围。 MOSFET器件还包括填充有沟槽填充材料的多个掺杂沟槽。MOSFET器件还包括设置在掺杂沟槽下方的多个深掺杂区域，其中深掺杂区域向下延伸到基本上为总和的深度的深掺杂区域的注入深度和在掺杂沟槽的底部下方的垂直扩散深度。

10. 发明授权

US5883416A Gate-contact structure to prevent contact metal penetration through gate layer without affecting breakdown voltage 失效
标题翻译：栅极接触结构，防止接触金属穿过栅极层而不影响击穿电压
公开(公告)号：US5883416A
公开(公告)日：1999-03-16
申请号：US792226
申请日：1997-01-31
申请人： True-Lon Lin , Koon Chong So , Fwu-Iuan Hshieh , Yan Man Tsui
发明人： True-Lon Lin , Koon Chong So , Fwu-Iuan Hshieh , Yan Man Tsui
IPC分类号： H01L29/06 , H01L29/423 , H01L29/78 , H01L23/485 , H01L23/48
CPC分类号： H01L29/42368 , H01L29/7811 , H01L29/0696 , H01L29/42372 , H01L29/4238 , H01L2924/0002
摘要： The present invention discloses a power transistor disposed on a substrate. The power device includes a core cell area comprising a plurality of power transistor cells each having drain and a source. Each of the power transistor cells further having a polycrystalline silicon gate formed on the substrate as part of a polycrystalline silicon gate layer overlaying the substrate. The polycrystalline silicon gate layer includes a plurality of polycrystalline gate-layer-extension extending to gate contact areas for forming gate contacts with a contact metal disposed thereon. The power transistor further includes a plurality of contact-metal-resistant pad each includes a thick oxide pad disposed below the gate contact areas underneath the polycrystalline gate layer extension whereby the contact-metal resistant pads resists the contact metal from penetrating therethrough and short to the substrate disposed thereunder.
摘要翻译：本发明公开了一种设置在基板上的功率晶体管。功率器件包括核心单元区域，其包括多个功率晶体管单元，每个功率晶体管单元具有漏极和源极。每个功率晶体管单元还具有形成在衬底上的多晶硅栅极，作为覆盖衬底的多晶硅栅极层的一部分。多晶硅栅极层包括延伸到栅极接触区域的多个多晶栅极层延伸部分，用于与设置在其上的接触金属形成栅极接触。功率晶体管还包括多个耐接触金属焊盘，每个包括设置在多晶栅极层延伸下方的栅极接触区下方的厚氧化物焊盘，由此接触金属电阻焊盘抵抗接触金属穿透其中并且短于底物置于其下。

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