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1. 发明授权

US06977203B2 Method of forming narrow trenches in semiconductor substrates 有权
标题翻译：在半导体衬底中形成窄沟槽的方法
公开(公告)号：US06977203B2
公开(公告)日：2005-12-20
申请号：US10010162
申请日：2001-11-20
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Brian D. Pratt
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Brian D. Pratt
IPC分类号： H01L21/28 , H01L21/3065 , H01L21/308 , H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/12 , H01L29/423 , H01L29/49 , H01L29/78 , H01L21/311 , H01L21/3205
CPC分类号： H01L21/3088 , H01L21/3086
摘要： A method of forming a trench within a semiconductor substrate. The method comprises, for example, the following: (a) providing a semiconductor substrate; (b) providing a patterned first CVD-deposited masking material layer having a first aperture over the semiconductor substrate; (c) depositing a second CVD-deposited masking material layer over the first masking material layer; (d) etching the second masking material layer until a second aperture that is narrower than the first aperture is created in the second masking material within the first aperture; and (e) etching the semiconductor substrate through the second aperture such that a trench is formed in the semiconductor substrate. In preferred embodiments, the method of the present invention is used in the formation of trench MOSFET devices.
摘要翻译：一种在半导体衬底内形成沟槽的方法。该方法例如包括以下：（a）提供半导体衬底; （b）提供在半导体衬底上具有第一孔的图案化的第一CVD沉积掩模材料层; （c）在所述第一掩蔽材料层上沉积第二CVD沉积的掩模材料层; （d）蚀刻所述第二掩模材料层，直到在所述第一孔径内的所述第二掩模材料中产生比所述第一孔径窄的第二孔径; 以及（e）通过所述第二孔蚀刻所述半导体衬底，使得在所述半导体衬底中形成沟槽。在优选实施例中，本发明的方法用于形成沟槽MOSFET器件。

2. 发明授权

US06645815B2 Method for forming trench MOSFET device with low parasitic resistance 有权
公开(公告)号：US06645815B2
公开(公告)日：2003-11-11
申请号：US10010483
申请日：2001-11-20
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Brian D. Pratt
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Brian D. Pratt
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L21/823487 , H01L29/1095 , Y10S148/126
摘要： A method is provided for forming shallow and deep dopant implants adjacent source regions of a first conductivity type within an upper portion of an epitaxial layer in a trench MOSFET device. The method comprises: (a) forming a patterned implantation mask over the epitaxial layer, wherein the patterned implantation mask comprises a patterned insulating region and covers at least a portion of the source regions, and wherein the patterned implantation mask has apertures over at least portions of the epitaxial layer adjacent the source regions; (b) forming shallow dopant regions by a process comprising: (1) implanting a first dopant of a second conductivity type at a first energy level within an upper portion of the epitaxial layer through the apertures and (2) diffusing the first dopant at elevated temperatures to a first depth from an upper surface of the epitaxial layer; (c) forming deep dopant regions by a process comprising: (1) implanting a second dopant of the second conductivity type at a second energy level within an upper portion of the epitaxial layer through the apertures and (2) diffusing the second dopant at elevated temperatures to a second depth from the upper surface of the epitaxial layer; and (d) enlarging apertures in the patterned insulating region. In this method, the second energy level is greater than the first energy level, the second depth is greater than the first depth, and the first and second dopants can be the same or different. The method of the present invention can be used, for example, to form a device that comprises a plurality of trench MOSFET cells.

3. 发明授权

US06657255B2 Trench DMOS device with improved drain contact 有权
标题翻译：沟槽DMOS器件具有改善的漏极接触
公开(公告)号：US06657255B2
公开(公告)日：2003-12-02
申请号：US10021419
申请日：2001-10-30
申请人： Fwu-Iuan Hshieh , Koon Chong So , William John Nelson , John E. Amato
发明人： Fwu-Iuan Hshieh , Koon Chong So , William John Nelson , John E. Amato
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/41741 , H01L29/41766 , H01L29/7809 , H01L29/7811
摘要： A trench DMOS transistor device that comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of first conductivity type over the substrate, wherein the epitaxial layer has a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of a second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type within an upper portion of the body region and adjacent the trench; and (h) one or more low resistivity deep regions extending into the device from an upper surface of the epitaxial layer. The low resistivity deep region acts to provide electrical contact with the substrate, which is a common drain region for the device. By constructing a trench DMOS transistor device in this fashion, source, drain and gate contacts can all be provided on a single surface of the device.
摘要翻译：一种沟槽DMOS晶体管器件，其包括：（a）第一导电类型的衬底; （b）在所述衬底上的第一导电类型的外延层，其中所述外延层具有比所述衬底更低的载流子浓度; （c）从外延层的上表面延伸到外延层中的沟槽; （d）衬在所述沟槽的至少一部分上的绝缘层; （e）邻近绝缘层的沟槽内的导电区域; （f）设置在所述外延层的上部并且与所述沟槽相邻的第二导电类型的体区; （g）第一导电类型的源区域，位于本体区域的上部并且与沟槽相邻; 和（h）从外延层的上表面延伸到器件中的一个或多个低电阻率深区域。低电阻率深区用于与衬底电接触，衬底是衬底的共用漏极区。通过以这种方式构造沟槽DMOS晶体管器件，源极，漏极和栅极触点都可以设置在器件的单个表面上。

4. 发明授权

US07015125B2 Trench MOSFET device with polycrystalline silicon source contact structure 失效
公开(公告)号：US07015125B2
公开(公告)日：2006-03-21
申请号：US10983490
申请日：2004-11-08
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
IPC分类号： H01L21/4763 , H01L21/336 , H01L21/8242
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/456
摘要： A trench MOSFET transistor device and a method of making the same. The device comprises: (a) a silicon substrate of first conductivity type; (b) a silicon epitaxial layer of first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type provided within an upper portion of the body region and adjacent the trench; (h) an upper region of second conductivity type within an upper portion of the body region and adjacent the source region, the upper region having a higher majority carrier concentration than the body region; and (i) a source contact region disposed on the epitaxial layer upper surface, wherein the source contact region comprises a doped polycrystalline silicon contact region in electrical contact with the source region as well as an adjacent metal contact region in electrical contact with the source region and with the upper region.

5. 发明授权

US06657254B2 Trench MOSFET device with improved on-resistance 有权
公开(公告)号：US06657254B2
公开(公告)日：2003-12-02
申请号：US09999116
申请日：2001-11-21
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/0878
摘要： A trench MOSFET device and method of making the same. The trench MOSFET device comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of the first conductivity type over the substrate, wherein the epitaxial layer has a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial region from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a doped region of the first conductivity type formed within the epitaxial layer between a bottom portion of the trench and the substrate, wherein the doped region has a majority carrier concentration that is lower than that of the substrate and higher than that of the epitaxial layer; (g) a body region of a second conductivity type formed within an upper portion of the epitaxial layer and adjacent the trench, wherein the body region extends to a lesser depth from the upper surface of the epitaxial layer than does the trench; and (h) a source region of the first conductivity type formed within an upper portion of the body region and adjacent the trench. The presence of the doped region lying between the bottom portion of the trench and the substrate (also referred to herein as a “trench bottom implant”) serves to reduce the on-resistance of the device.

6. 发明授权

US06822288B2 Trench MOSFET device with polycrystalline silicon source contact structure 失效
标题翻译：沟槽MOSFET器件，具有多晶硅源接触结构
公开(公告)号：US06822288B2
公开(公告)日：2004-11-23
申请号：US10010484
申请日：2001-11-20
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/456
摘要： A trench MOSFET transistor device and a method of making the same. The device comprises: (a) a silicon substrate of first conductivity type; (b) a silicon epitaxial layer of first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type provided within an upper portion of the body region and adjacent the trench; (h) an upper region of second conductivity type within an upper portion of the body region and adjacent the source region, the upper region having a higher majority carrier concentration than the body region; and (i) a source contact region disposed on the epitaxial layer upper surface, wherein the source contact region comprises a doped polycrystalline silicon contact region in electrical contact with the source region as well as an adjacent metal contact region in electrical contact with the source region and with the upper region.
摘要翻译：沟槽MOSFET晶体管器件及其制造方法。该装置包括：（a）第一导电类型的硅衬底; （b）在衬底上的第一导电类型的硅外延层，所述外延层具有比衬底更低的载流子浓度; （c）从外延层的上表面延伸到外延层中的沟槽; （d）衬在所述沟槽的至少一部分上的绝缘层; （e）邻近绝缘层的沟槽内的导电区域; （f）第二导电类型的体区，设置在所述外延层的上部并且与所述沟槽相邻; （g）第一导电类型的源极区域，设置在所述主体区域的上部并且邻近所述沟槽; （h）第二导电类型的上部区域，在所述主体区域的上部并且邻近所述源极区域，所述上部区域具有比所述身体区域更高的载流子浓度; 和（i）设置在所述外延层上表面上的源极接触区域，其中所述源极接触区域包括与所述源极区域电接触的掺杂多晶硅接触区域以及与所述源极区域电接触的相邻金属接触区域和上部区域。

7. 发明授权

US06630402B2 Integrated circuit resistant to the formation of cracks in a passivation layer 失效
标题翻译：集成电路可抵抗钝化层中裂纹的形成
公开(公告)号：US06630402B2
公开(公告)日：2003-10-07
申请号：US09990460
申请日：2001-11-21
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato
IPC分类号： H01L2100
CPC分类号： H01L21/76838 , H01L23/3171 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： In integrated circuits produced by etching and damascene techniques, it is common for cracking to occur in dielectric material surrounding an interconnect metal layer integrated into the device, presumably as a result of the transfer of stresses from the interconnect metal layer to the surrounding dielectric material. The present invention addresses this problem by providing an interconnect metal layer that comprises rounded comers which are believed to reduce the stresses transferred to a surrounding dielectric layer.
摘要翻译：在通过蚀刻和镶嵌技术制造的集成电路中，通常在集成到器件中的互连金属层周围的电介质材料中发生破裂，这可能是由于互连金属层到周围电介质材料的应力传递的结果。本发明通过提供一种互连金属层来解决这个问题，该互连金属层包括被认为能够减少传递到周围电介质层的应力的圆角。

8. 发明授权

US07049194B2 Trench DMOS device with improved drain contact 有权
公开(公告)号：US07049194B2
公开(公告)日：2006-05-23
申请号：US10725326
申请日：2003-12-01
申请人： Fwu-Iuan Hshieh , Koon Chong So , William John Nelson , John E. Amato
发明人： Fwu-Iuan Hshieh , Koon Chong So , William John Nelson , John E. Amato
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/41741 , H01L29/41766 , H01L29/7809 , H01L29/7811
摘要： A trench DMOS transistor device that comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of first conductivity type over the substrate, wherein the epitaxial layer has a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of a second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type within an upper portion of the body region and adjacent the trench; and (h) one or more low resistivity deep regions extending into the device from an upper surface of the epitaxial layer. The low resistivity deep region acts to provide electrical contact with the substrate, which is a common drain region for the device. By constructing a trench DMOS transistor device in this fashion, source, drain and gate contacts can all be provided on a single surface of the device.

9. 发明授权

US06558984B2 Trench schottky barrier rectifier and method of making the same 有权
标题翻译：沟槽肖特基势垒整流器及其制作方法
公开(公告)号：US06558984B2
公开(公告)日：2003-05-06
申请号：US10078994
申请日：2002-02-19
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato
IPC分类号： H01L21332
CPC分类号： H01L29/66143 , H01L29/417 , H01L29/872
摘要： A trench Schottky barrier and a method of making the same in which the rectifier has a semiconductor region having first and second opposing faces; the semiconductor region having a drift region of a first conductivity type adjacent the first face and a cathode region of the first conductivity type adjacent the second face; the drift region having a lower net doping concentration than that of the cathode region. The rectifier also has a plurality of trenches extending into the semiconductor region from the first face; the trenches defining a plurality of mesas within the semiconductor region, and the trenches forming a plurality of trench intersections. The rectifier further includes an oxide layer covering the semiconductor region on the bottoms of the trenches and on lower portions of sidewalls of the trenches, a polysilicon region disposed over the oxide layer within the trenches, and insulating regions at the trench intersections that cover a portion of the polysilicon region and a portion of the oxide layer.
摘要翻译：沟槽肖特基势垒及其制造方法，其中整流器具有具有第一和第二相对面的半导体区域; 所述半导体区域具有与所述第一面相邻的第一导电类型的漂移区域和与所述第二面部相邻的所述第一导电类型的阴极区域; 漂移区具有比阴极区更低的净掺杂浓度。整流器还具有从第一面延伸到半导体区域中的多个沟槽; 所述沟槽限定所述半导体区域内的多个台面，并且所述沟槽形成多个沟槽交叉点。整流器还包括覆盖沟槽底部的半导体区域和沟槽侧壁的下部的氧化物层，设置在沟槽内的氧化物层上的多晶硅区域以及覆盖部分的沟槽交点处的绝缘区域的多晶硅区域和氧化物层的一部分。

10. 发明授权

US06420768B1 Trench schottky barrier rectifier and method of making the same 有权
标题翻译：沟槽肖特基势垒整流器及其制作方法
公开(公告)号：US06420768B1
公开(公告)日：2002-07-16
申请号：US09737357
申请日：2000-12-15
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato
IPC分类号： H01L27095
CPC分类号： H01L29/66143 , H01L29/417 , H01L29/872
摘要： A trench Schottky barrier rectifier and a method of making the same in which the rectifier has a semiconductor region having first and second opposing faces; the semiconductor region having a drift region of first conductivity type adjacent the first face and a cathode region of the first conductivity type adjacent the second face; the drift region having a lower net doping concentration than that of the cathode region. The rectifier also has a plurality of trenches extending into the semiconductor region from the first face; the trenches defining a plurality of mesas within the semiconductor region, and the trenches forming a plurality of trench intersections. The rectifier further includes an oxide layer covering the semiconductor region on bottoms of the trenches and on lower portions of sidewalls of the trenches, a polysilicon region disposed over the oxide layer within the trenches, and insulating regions at the trench intersections that cover a portion of the polysilicon region and a portion of the oxide layer.
摘要翻译：沟槽肖特基势垒整流器及其制造方法，其中整流器具有具有第一和第二相对面的半导体区域; 所述半导体区域具有与所述第一面相邻的第一导电类型的漂移区域和与所述第二面部相邻的所述第一导电类型的阴极区域; 漂移区具有比阴极区更低的净掺杂浓度。整流器还具有从第一面延伸到半导体区域中的多个沟槽; 所述沟槽限定所述半导体区域内的多个台面，并且所述沟槽形成多个沟槽交叉点。整流器还包括覆盖沟槽底部的半导体区域和沟槽的侧壁的下部的氧化物层，设置在沟槽内的氧化物层上的多晶硅区域以及覆盖部分的沟槽交点处的绝缘区域多晶硅区域和氧化物层的一部分。

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