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51. 发明申请

US20050227402A1 [METHOD OF MANUFACTURING PHOTODIODE] 有权
标题翻译： [制作光致变色剂的方法]
公开(公告)号：US20050227402A1
公开(公告)日：2005-10-13
申请号：US10710732
申请日：2004-07-30
申请人： Ko-Hsing Chang , Su-Yuan Chang
发明人： Ko-Hsing Chang , Su-Yuan Chang
IPC分类号： H01L21/00 , H01L31/101 , H01L31/103 , H01L31/18
CPC分类号： H01L31/1804 , H01L31/103 , H01L31/1864 , Y02E10/547
摘要： A method of manufacturing of a photodiode is provided. The photodiode is formed on a substrate of a first conductive type. First, an isolation structure is formed in the substrate to define a photosensitive area in the substrate. Thereafter, trenches are formed in the substrate. Next, a doped layer of a second conductive type is formed on the substrate. The doped layer covers at least the inner wall of the trenches and a top portion of the substrate. The method of fabricating the photodiode can reduce overall processing time and cost and improve production efficiency.
摘要翻译：提供了一种制造光电二极管的方法。光电二极管形成在第一导电类型的衬底上。首先，在衬底中形成隔离结构以在衬底中限定光敏区域。此后，在衬底中形成沟槽。接下来，在基板上形成第二导电类型的掺杂层。掺杂层至少覆盖沟槽的内壁和衬底的顶部。制造光电二极管的方法可以缩短整体处理时间和成本，提高生产效率。

52. 发明授权

US06869842B2 Method for manufacturing non-volatile memory cell 有权
标题翻译：制造非易失性存储单元的方法
公开(公告)号：US06869842B2
公开(公告)日：2005-03-22
申请号：US10707418
申请日：2003-12-12
申请人： Ko-Hsing Chang , Cheng-Yuan Hsu
发明人： Ko-Hsing Chang , Cheng-Yuan Hsu
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L21/336 , H01L21/331
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/7883
摘要： A non-volatile memory cell having a symmetric cell structure is disclosed. The non-volatile memory cell includes a substrate, a tunnel oxide layer, two floating gates, a dielectric layer, a plurality of spacers, a control gate, and two split gates. The substrate has at least two sources and a drain that is located between the sources. The floating gates are formed on the tunneling oxide layer, and each of floating gates is located between each source and the drain. The dielectric layer is formed on the floating gates. The control gate is formed over the drain and is between the floating gates. The split gates are located adjacent to outward sidewalls of the floating gates, respectively. Therefore, each of the split gates is opposite to the control gate through each of the floating gates.
摘要翻译：公开了具有对称单元结构的非易失性存储单元。非易失性存储单元包括衬底，隧道氧化物层，两个浮动栅极，电介质层，多个间隔物，控制栅极和两个分离栅极。衬底具有至少两个源和位于源之间的漏极。浮动栅极形成在隧道氧化物层上，每个浮栅位于每个源极和漏极之间。电介质层形成在浮栅上。控制栅极形成在漏极之上并且在浮动栅极之间。分流门分别位于浮动门的外侧壁附近。因此，每个分离门通过每个浮动栅极与控制栅极相对。

53. 发明授权

US06821849B2 Split gate flash memory cell and manufacturing method thereof 有权
标题翻译：分流式闪存单元及其制造方法
公开(公告)号：US06821849B2
公开(公告)日：2004-11-23
申请号：US10709309
申请日：2004-04-28
申请人： Ko-Hsing Chang , Hann-Jye Hsu
发明人： Ko-Hsing Chang , Hann-Jye Hsu
IPC分类号： H01L218247
CPC分类号： H01L27/11553 , H01L27/11556 , H01L29/42324 , H01L29/7883
摘要： A split gate flash memory cell includes a substrate having a trench, a stack structure disposed on the substrate, wherein the stack structure includes a tunneling dielectric layer, a floating gate and a cap layer; a first inter-gate dielectric layer and a second inter-gate dielectric layer disposed on the sidewalls of the stack structure, wherein the first inter-gate dielectric layer is contiguous to the top of the trench; a selective gate disposed on the sidwalls of the first inter-gate dielectric layer and the trench; a selective gate dielectric layer disposed between the selective gate and the substrate; a source region configured in the substrate beside the side of the stack structure with the second inter-gate dielectric layer; and a drain region configured at the bottom of the trench beside one side of the selective gate.
摘要翻译：分离栅闪存单元包括具有沟槽的衬底，设置在衬底上的堆叠结构，其中所述堆叠结构包括隧道电介质层，浮动栅极和盖层; 设置在所述堆叠结构的侧壁上的第一栅极间电介质层和第二栅极间电介质层，其中所述第一栅极间电介质层与所述沟槽的顶部邻接; 设置在第一栅极间电介质层和沟槽的侧壁上的选择栅; 设置在选择栅极和衬底之间的选择栅极介电层; 源极区域，其被配置在与所述第二栅极间电介质层的所述堆叠结构的旁边的所述衬底中; 以及漏极区域，其配置在所述沟槽的底部，在所述选择栅极的一侧旁边。

54. 发明授权

US06635533B1 Method of fabricating flash memory 有权
标题翻译：制造闪存的方法
公开(公告)号：US06635533B1
公开(公告)日：2003-10-21
申请号：US10249256
申请日：2003-03-27
申请人： Ko-Hsing Chang , Cheng-Yuan Hsu
发明人： Ko-Hsing Chang , Cheng-Yuan Hsu
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42328
摘要： A method of fabricating a flash memory is provided. A pad layer and a mask layer are formed over the substrate, and then the mask layer is patterned for forming an opening therein. The pad layer exposed by the opening is removed. After a tunneling dielectric layer is formed on the bottom of the opening, a floating gate is formed on the sidewall of the opening. The top of the floating gate is lower than a surface of the mask layer. A source region is formed in the substrate. Thereafter, an inter-gate dielectric layer is formed in the opening and a control gate is filled in the opening. The mask layer is removed and then a gate dielectric layer is formed on the substrate and a spacer is formed on the sidewall of the floating gate and the control gate. A select gate is formed on the sidewall of the spacer. A drain region is formed in the substrate on one side of the select gate.
摘要翻译：提供一种制造闪速存储器的方法。在衬底上形成焊盘层和掩模层，然后对掩模层进行图案化以在其中形成开口。去除由开口暴露的垫层。在开口底部形成隧道电介质层之后，在开口的侧壁上形成浮栅。浮动栅极的顶部低于掩模层的表面。源极区域形成在衬底中。此后，在开口中形成栅极间电介质层，并且在开口中填充控制栅。去除掩模层，然后在衬底上形成栅极电介质层，并且在浮动栅极和控制栅极的侧壁上形成间隔物。选择栅极形成在间隔件的侧壁上。漏极区域形成在选择栅极一侧的衬底中。

55. 发明授权

US6026028A Hot carrier injection programming and negative gate voltage channel erase flash EEPROM structure 失效
标题翻译：热载波注入编程和负栅极电压通道擦除闪存EEPROM结构
公开(公告)号：US6026028A
公开(公告)日：2000-02-15
申请号：US123305
申请日：1998-07-28
申请人： Chen-Hsi Lin , Chih-Ming Chen , Ling-Sung Wang , Horng-Ming Lee , Ko-Hsing Chang
发明人： Chen-Hsi Lin , Chih-Ming Chen , Ling-Sung Wang , Horng-Ming Lee , Ko-Hsing Chang
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： H01L29/7885
摘要： A flash electrical erasable programmable read only memory structure that utilizes hot carrier injection for programming and negative gate voltage to carry out channel erase operations. Characteristic of the memory structure includes a triple well structure having a P-well and an N-well located within a P-type substrate, wherein the N-well isolated the P-well from the P-type substrate. Therefore, an independently isolated triple well structure is established during memory erase operation.
摘要翻译：闪存电可擦除可编程只读存储器结构，其利用热载流子注入用于编程和负栅极电压来执行通道擦除操作。存储器结构的特征包括具有P阱和位于P型衬底内的N阱的三阱结构，其中N阱从P型衬底隔离P阱。因此，在存储器擦除操作期间建立独立隔离的三重阱结构。

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