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51. 发明申请

US20110225445A1 MEMORY INTERFACE HAVING EXTENDED STROBE BURST FOR READ TIMING CALIBRATION 有权
标题翻译：具有扩展STROBE BURST的存储接口进行读取时序校准
公开(公告)号：US20110225445A1
公开(公告)日：2011-09-15
申请号：US12723885
申请日：2010-03-15
申请人： Kevin C. Gower , Kyu-hyoun Kim
发明人： Kevin C. Gower , Kyu-hyoun Kim
IPC分类号： G06F12/00 , G06F1/04
CPC分类号： G06F1/04 , G06F12/00 , G06F13/161 , G06F13/1689
摘要： Methods and systems for calibrating parameters for communication between a controller and a memory device. A memory controller may be configured to calibrate one or more of the read latency and/or the latency window of a memory controller such that a data signal and a data strobe signal are received by the memory controller within the latency window of the memory controller.
摘要翻译：用于校准控制器和存储器件之间通信的参数的方法和系统。存储器控制器可以被配置为校准存储器控制器的读延迟和/或等待时间窗口中的一个或多个，使得存储器控制器在存储器控制器的延迟窗口内接收数据信号和数据选通信号。

52. 发明申请

US20110225444A1 MEMORY INTERFACE HAVING EXTENDED STROBE BURST FOR WRITE TIMING CALIBRATION 有权
标题翻译：具有扩展STRBE BURST的存储接口进行写时序校准
公开(公告)号：US20110225444A1
公开(公告)日：2011-09-15
申请号：US12723843
申请日：2010-03-15
申请人： Kevin C. Gower , Kyu-hyoun Kim
发明人： Kevin C. Gower , Kyu-hyoun Kim
IPC分类号： G06F12/00 , G06F1/04
CPC分类号： G06F1/04 , G06F13/1694 , G11C7/1093 , G11C2207/2254
摘要： Methods and systems for calibrating parameters for communication between a controller and a memory device. A memory controller may be configured to calibrate one or more of the write latency and/or the latency window of a memory device such that a data signal and a data strobe signal are received by the memory device within the latency window of the memory device.
摘要翻译：用于校准控制器和存储器件之间通信的参数的方法和系统。存储器控制器可以被配置为校准存储器件的写延迟和/或等待时间窗口中的一个或多个，使得数据信号和数据选通信号在存储器件的延迟窗口内由存储器件接收。

53. 发明授权

US07979759B2 Test and bring-up of an enhanced cascade interconnect memory system 有权
标题翻译：增强级联互连存储器系统的测试和启动
公开(公告)号：US07979759B2
公开(公告)日：2011-07-12
申请号：US12350306
申请日：2009-01-08
申请人： Michael J. Carnevale , Elianne A. Bravo , Kevin C. Gower , Gary A. Van Huben , Donald J. Ziebarth
发明人： Michael J. Carnevale , Elianne A. Bravo , Kevin C. Gower , Gary A. Van Huben , Donald J. Ziebarth
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G11C5/04 , G11C29/16
摘要： A memory hub device with test logic is configured to communicate with memory devices via multiple hub device ports, and is also configured to communicate on one or more busses in an upstream and downstream direction. The test logic includes a built-in self test apparatus providing logic to simultaneously and independently test the memory devices interfaced to one or more of the hub device ports using read and write data patterns. The test logic also includes configuration registers to hold fault and diagnostic information, and to initiate one or more tests. The memory hub device can further include command collision detection logic, a trace array, buffer transmit mode logic, trigger logic, clock adjustment logic, transparent mode logic, and a configured command sequencer, as well as additional features.
摘要翻译：具有测试逻辑的存储器集线器设备被配置为经由多个集线器设备端口与存储器设备通信，并且还被配置为在上游和下游方向上的一个或多个总线上进行通信。测试逻辑包括内置的自我测试装置，其提供使用读取和写入数据模式同时且独立地测试与一个或多个中枢设备端口连接的存储器件的逻辑。测试逻辑还包括配置寄存器来保存故障和诊断信息，并启动一个或多个测试。存储器集线器设备还可以包括命令冲突检测逻辑，跟踪阵列，缓冲器发送模式逻辑，触发逻辑，时钟调整逻辑，透明模式逻辑和配置的命令定序器，以及附加特征。

54. 发明授权

US07930469B2 System to provide memory system power reduction without reducing overall memory system performance 失效
标题翻译：系统提供内存系统功耗降低，而不会降低整体内存系统性能
公开(公告)号：US07930469B2
公开(公告)日：2011-04-19
申请号：US12018952
申请日：2008-01-24
申请人： Mark A. Brittain , Kevin C. Gower , Warren E. Maule
发明人： Mark A. Brittain , Kevin C. Gower , Warren E. Maule
IPC分类号： G06F12/00
CPC分类号： G11C5/04 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F13/4243 , G11C8/18 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/159
摘要： A memory system is provided that provides memory system power reduction without reducing overall memory system performance. The memory system comprises a memory hub device integrated in a memory module. The memory hub device comprises a command queue that receives a memory access command from an memory controller via a memory channel at a first operating frequency. The memory system also comprises a memory hub controller integrated in the memory hub device. The memory hub controller reads the memory access command from the command queue at a second operating frequency. By receiving the memory access command at the first operating frequency and reading the memory access command at the second operating frequency an asynchronous boundary is implemented. Using the asynchronous boundary, the memory channel operates at a maximum designed operating bandwidth while the second operating frequency is independently decreased to reduce power being consumed by the set of memory devices.
摘要翻译：提供了一种提供存储器系统功率降低而不降低整体存储器系统性能的存储器系统。存储器系统包括集成在存储器模块中的存储器集线器设备。存储器集线器设备包括命令队列，其经由存储器通道以第一工作频率从存储器控制器接收存储器访问命令。存储器系统还包括集成在存储器集线器设备中的存储器集线器控制器。存储器集线器控制器以第二工作频率从命令队列读取存储器访问命令。通过以第一工作频率接收存储器访问命令并且以第二工作频率读取存储器访问命令，实现异步边界。使用异步边界，存储器通道以最大设计的工作带宽工作，而第二工作频率被独立地降低以减少由该组存储器件消耗的功率。

55. 发明授权

US07925825B2 System to support a full asynchronous interface within a memory hub device 有权
标题翻译：系统支持内存集线器设备中的完整异步接口
公开(公告)号：US07925825B2
公开(公告)日：2011-04-12
申请号：US12019071
申请日：2008-01-24
申请人： Mark A. Brittain , Kevin C. Gower , Warren E. Maule
发明人： Mark A. Brittain , Kevin C. Gower , Warren E. Maule
IPC分类号： G06F12/00
CPC分类号： G06F13/4243
摘要： A memory system is provided that implements an asynchronous boundary in a memory module. The memory system comprises a memory hub device integrated in a memory module. The memory system also comprises a set of memory devices coupled to the memory hub device. The memory hub device comprises a command queue that receives a memory access command from an external memory controller via a memory channel at a first operating frequency. The memory system further comprises a memory hub controller integrated in the memory hub device. The memory hub controller reads the memory access command from the command queue at a second operating frequency. By receiving the memory access command at the first operating frequency and reading the memory access command at the second operating frequency an asynchronous boundary is implemented within the memory hub device of the memory module.
摘要翻译：提供了一种在存储器模块中实现异步边界的存储器系统。存储器系统包括集成在存储器模块中的存储器集线器设备。存储器系统还包括耦合到存储器集线器设备的一组存储器件。存储器集线器设备包括命令队列，其经由存储器通道以第一工作频率从外部存储器控制器接收存储器访问命令。存储器系统还包括集成在存储器集线器设备中的存储器集线器控制器。存储器集线器控制器以第二工作频率从命令队列读取存储器访问命令。通过以第一工作频率接收存储器访问命令并且以第二工作频率读取存储器访问命令，在存储器模块的存储器集线器设备内实现异步边界。

56. 发明申请

US20110075740A1 Configurable Differential to Single Ended IO 有权
标题翻译：可配置差分至单端IO
公开(公告)号：US20110075740A1
公开(公告)日：2011-03-31
申请号：US12568765
申请日：2009-09-29
申请人： Frank D. Ferraiolo , Kevin C. Gower , Robert B. Tremaine , Kenneth L. Wright
发明人： Frank D. Ferraiolo , Kevin C. Gower , Robert B. Tremaine , Kenneth L. Wright
IPC分类号： H04B3/00
CPC分类号： H04L25/0272 , Y02D30/30
摘要： An electronic system having a power efficient differential signal between a first and second electronic unit. A controller uses information, such as compliance with data transmission rate requirement and bit error rate (BER) versus a BER threshold to control power modes such that a minimal amount of power is required. Amplitude of transmission and single ended or differential transmission of data are examples of the power modes. The controller also factors in a failing phase in a differential signal in selecting a minimal power mode that satisfies the transmission rate requirement of the BER threshold.
摘要翻译：一种在第一和第二电子单元之间具有功率有效的差分信号的电子系统。控制器使用诸如符合数据传输速率要求和误码率（BER）与BER阈值的信息来控制功率模式，使得需要最小量的功率。传输幅度和数据的单端或差分传输是功率模式的例子。控制器还在选择满足BER阈值的传输速率要求的最小功率模式时，在差分信号中导致故障相位。

57. 发明申请

US20110055671A1 ADVANCED MEMORY DEVICE HAVING IMPROVED PERFORMANCE, REDUCED POWER AND INCREASED RELIABILITY 有权
标题翻译：具有改进性能，降低功耗和提高可靠性的高级存储设备
公开(公告)号：US20110055671A1
公开(公告)日：2011-03-03
申请号：US12553400
申请日：2009-09-03
申请人： Kyu-Hyoun Kim , George L. Chiu , Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Warren E. Maule
发明人： Kyu-Hyoun Kim , George L. Chiu , Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Warren E. Maule
IPC分类号： G11C7/00 , G11C8/18 , H03M13/09 , G06F11/07 , G06F11/10
CPC分类号： G11C7/1078 , G06F11/1028 , G11C7/04 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/109 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/406 , G11C11/40611 , G11C11/40615 , G11C11/40626 , G11C11/4076 , G11C11/4096 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.
摘要翻译：具有改进性能，降低功耗和增加可靠性的高级内存。存储器件包括存储器阵列，用于接收命令和相关联的数据的接收器，用于对接收到的命令执行错误控制检查的差错控制编码电路以及用于防止相关联的数据被响应地写入存储器阵列的数据屏蔽电路对错误控制编码电路检测接收到的命令中的错误。另一个存储器件包括可编程序序。另一存储器件包括快速退出自刷新模式。另一种存储装置包括由特征装置控制的自动刷新功能。另一存储器件包括由存储器件的特性控制的自动刷新功能。

58. 发明授权

US07844771B2 System, method and storage medium for a memory subsystem command interface 失效
标题翻译：用于内存子系统命令界面的系统，方法和存储介质
公开(公告)号：US07844771B2
公开(公告)日：2010-11-30
申请号：US12059164
申请日：2008-03-31
申请人： Kevin C. Gower , Warren E. Maule
发明人： Kevin C. Gower , Warren E. Maule
IPC分类号： G06F12/00 , G06F13/38 , G06F13/42
CPC分类号： G06F13/1684
摘要： A system for implementing a memory subsystem command interface, the system including a cascaded interconnect system including one or more memory modules, a memory controller and a memory bus. The memory controller generates a data frame that includes a plurality of commands. The memory controller and the memory module are interconnected by a packetized multi-transfer interface via the memory bus and the frame is transmitted to the memory modules via the memory bus.
摘要翻译：一种用于实现存储器子系统命令接口的系统，该系统包括包括一个或多个存储器模块，存储器控制器和存储器总线的级联互连系统。存储器控制器生成包括多个命令的数据帧。存储器控制器和存储器模块通过存储器总线通过分组化的多传输接口互连，并且帧经由存储器总线传送到存储器模块。

59. 发明申请

US20100162037A1 Memory System having Spare Memory Devices Attached to a Local Interface Bus 审中-公开
标题翻译：具有连接到本地接口总线的备用内存设备的内存系统
公开(公告)号：US20100162037A1
公开(公告)日：2010-06-24
申请号：US12341472
申请日：2008-12-22
申请人： Warren Edward Maule , Kevin C. Gower , Kenneth Lee Wright
发明人： Warren Edward Maule , Kevin C. Gower , Kenneth Lee Wright
IPC分类号： G06F12/00 , G06F11/20
CPC分类号： G06F13/1684 , G06F11/106 , G11C5/04 , G11C29/83 , Y02D10/14
摘要： A memory system includes a memory controller, one or more memory channel(s), and a memory subsystem having a memory interface device (e.g. a hub or buffer device) located on a memory subsystem (e.g. a DIMM) coupled to the memory channel to communicate with the memory device(s) array. This buffered DIMM is provided with one or more spare chips on the DIMM, wherein the data bits sourced from the spare chips are connected to the memory hub device and the bus to the DIMM includes only those data bits used for normal operation. The buffered DIMM with one or more spare chips on the DIMM has the spare memory shared among all the ranks, and the memory hub device includes separate control bus(es) for the spare memory device to allow the spare memory device(s) to be utilized to replace one or more failing bits and/or devices within any rank of memory in the memory subsystem.
摘要翻译：存储器系统包括存储器控制器，一个或多个存储器通道和存储器子系统，该存储器子系统具有位于耦合到存储器通道的存储器子系统（例如，DIMM）上的存储器接口设备（例如，集线器或缓冲设备）与存储器件阵列通信。该缓冲DIMM在DIMM上提供一个或多个备用芯片，其中从备用芯片获取的数据位连接到存储器集线器设备，并且到DIMM的总线仅包括用于正常操作的那些数据位。在DIMM上具有一个或多个备用芯片的缓冲DIMM具有在所有等级中共享的备用存储器，并且存储器集线器设备包括用于备用存储器设备的单独的控制总线，以允许备用存储器设备用于替换存储器子系统中的任何等级的存储器内的一个或多个故障位和/或设备。

60. 发明申请

US20100162020A1 Power Management of a Spare DRAM on a Buffered DIMM by Issuing a Power On/Off Command to the DRAM Device 失效
标题翻译：通过向DRAM器件发出电源开/关命令，对缓冲DIMM上的备用DRAM进行电源管理
公开(公告)号：US20100162020A1
公开(公告)日：2010-06-24
申请号：US12341515
申请日：2008-12-22
申请人： Warren Edward Maule , Kevin C. Gower , Kyu-hyoun Kim , Dustin James VanStee
发明人： Warren Edward Maule , Kevin C. Gower , Kyu-hyoun Kim , Dustin James VanStee
IPC分类号： G06F1/32 , G06F12/06
CPC分类号： G11C5/06 , G11C5/04 , G11C5/14 , G11C11/4074
摘要： A computer memory, having one or more of a semiconductor memory device having an internal memory array comprising a plurality of semiconductor dynamic random access memory (DRAM) cells arranged in a matrix of rows and columns, and provided as a memory module rank of such memory devices arranged in an array on a DIMM of one or more of said semiconductor memory device on a substrate which can be coupled via a memory device data interface to a memory system as a memory subsystem, each of said memory device having a low power shut-down state that can be activated using a common memory data interface. Control of power to a DRAM issues over the data interface two commands to a DRAM power control command decode, a power-state program signal and a power-state reset signal as a power-state control commands to control the power state of said DRAM, and to activate for READ/WRITE a memory cell as a normal active or spare device.
摘要翻译：一种具有一个或多个具有内部存储器阵列的半导体存储器件的计算机存储器，所述内部存储器阵列包括排列成行和列的矩阵的多个半导体动态随机存取存储器（DRAM）单元，并被提供为这种存储器的存储器模块等级在基板上的一个或多个所述半导体存储器件的DIMM上布置的阵列中的器件，其可以经由存储器件数据接口耦合到作为存储器子系统的存储器系统，每个所述存储器件具有低功率闭合 - 可以使用公共存储器数据接口激活。通过数据接口对DRAM的功率的控制问题DRAM功率控制命令的两个命令解码，功率状态程序信号和功率状态复位信号作为功率状态控制命令来控制所述DRAM的功率状态，并激活用于将存储器单元作为正常的有源或备用设备读/写。

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