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1. 发明申请

US20100174955A1 TEST AND BRING-UP OF AN ENHANCED CASCADE INTERCONNECT MEMORY SYSTEM 有权
标题翻译：增强的CASCADE互连存储系统的测试和启动
公开(公告)号：US20100174955A1
公开(公告)日：2010-07-08
申请号：US12350306
申请日：2009-01-08
申请人： Michael J. Carnevale , Elianne A. Bravo , Kevin C. Gower , Gary A. Van Huben , Donald J. Ziebarth
发明人： Michael J. Carnevale , Elianne A. Bravo , Kevin C. Gower , Gary A. Van Huben , Donald J. Ziebarth
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/56 , G11C5/04 , G11C29/16
摘要： A memory hub device with test logic is configured to communicate with memory devices via multiple hub device ports, and is also configured to communicate on one or more busses in an upstream and downstream direction. The test logic includes a built-in self test apparatus providing logic to simultaneously and independently test the memory devices interfaced to one or more of the hub device ports using read and write data patterns. The test logic also includes configuration registers to hold fault and diagnostic information, and to initiate one or more tests. The memory hub device can further include command collision detection logic, a trace array, buffer transmit mode logic, trigger logic, clock adjustment logic, transparent mode logic, and a configured command sequencer, as well as additional features.
摘要翻译：具有测试逻辑的存储器集线器设备被配置为经由多个集线器设备端口与存储器设备通信，并且还被配置为在上游和下游方向上的一个或多个总线上进行通信。测试逻辑包括内置的自我测试装置，其提供使用读取和写入数据模式同时且独立地测试与一个或多个中枢设备端口连接的存储器件的逻辑。测试逻辑还包括配置寄存器来保存故障和诊断信息，并启动一个或多个测试。存储器集线器设备还可以包括命令冲突检测逻辑，跟踪阵列，缓冲器发送模式逻辑，触发逻辑，时钟调整逻辑，透明模式逻辑和配置的命令定序器，以及附加特征。

2. 发明授权

US07979759B2 Test and bring-up of an enhanced cascade interconnect memory system 有权
标题翻译：增强级联互连存储器系统的测试和启动
公开(公告)号：US07979759B2
公开(公告)日：2011-07-12
申请号：US12350306
申请日：2009-01-08
申请人： Michael J. Carnevale , Elianne A. Bravo , Kevin C. Gower , Gary A. Van Huben , Donald J. Ziebarth
发明人： Michael J. Carnevale , Elianne A. Bravo , Kevin C. Gower , Gary A. Van Huben , Donald J. Ziebarth
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G11C5/04 , G11C29/16
摘要： A memory hub device with test logic is configured to communicate with memory devices via multiple hub device ports, and is also configured to communicate on one or more busses in an upstream and downstream direction. The test logic includes a built-in self test apparatus providing logic to simultaneously and independently test the memory devices interfaced to one or more of the hub device ports using read and write data patterns. The test logic also includes configuration registers to hold fault and diagnostic information, and to initiate one or more tests. The memory hub device can further include command collision detection logic, a trace array, buffer transmit mode logic, trigger logic, clock adjustment logic, transparent mode logic, and a configured command sequencer, as well as additional features.
摘要翻译：具有测试逻辑的存储器集线器设备被配置为经由多个集线器设备端口与存储器设备通信，并且还被配置为在上游和下游方向上的一个或多个总线上进行通信。测试逻辑包括内置的自我测试装置，其提供使用读取和写入数据模式同时且独立地测试与一个或多个中枢设备端口连接的存储器件的逻辑。测试逻辑还包括配置寄存器来保存故障和诊断信息，并启动一个或多个测试。存储器集线器设备还可以包括命令冲突检测逻辑，跟踪阵列，缓冲器发送模式逻辑，触发逻辑，时钟调整逻辑，透明模式逻辑和配置的命令定序器，以及附加特征。

3. 发明授权

US07181659B2 Memory built-in self test engine apparatus and method with trigger on failure and multiple patterns per load capability 失效
标题翻译：内存自检引擎装置和方法，具有故障触发和每种负载能力的多种模式
公开(公告)号：US07181659B2
公开(公告)日：2007-02-20
申请号：US11055195
申请日：2005-02-10
申请人： Elianne A. Bravo , Kenneth Y. Chan , Kevin C. Gower , Dustin J. VanStee
发明人： Elianne A. Bravo , Kenneth Y. Chan , Kevin C. Gower , Dustin J. VanStee
IPC分类号： G11C29/00
CPC分类号： G11C29/16 , G11C11/401
摘要： A memory built-in self test (MBIST) apparatus and method for testing dynamic random access memory (DRAM) arrays, the DRAM arrays in communication with a memory interface device that includes interface logic and mainline chip logic. The MBIST apparatus includes a finite state machine including a command generator and logic for incrementing data and addresses under test and a command scheduler in communication with the finite state machine. The command scheduler includes resource allocation logic for spacing commands to memory dynamically utilizing DRAM timing parameters. The MBIST apparatus also includes a test memory storing subtests of an MBIST test. Each of the subtests provides a full pass through a configured address range. The MBIST apparatus further includes a subtest pointer in communication with the test memory and the finite state machine. The finite state machine implements subtest sequencing of each of the subtests via the subtest pointer.
摘要翻译：用于测试动态随机存取存储器（DRAM）阵列的存储器内置自检（MBIST）装置和方法，所述DRAM阵列与包括接口逻辑和主线芯片逻辑的存储器接口装置通信。 MBIST装置包括有限状态机，其包括用于递增待测数据和地址的命令发生器和逻辑，以及与有限状态机通信的命令调度器。命令调度器包括用于动态地利用DRAM时序参数将命令间隔到存储器的资源分配逻辑。 MBIST设备还包括存储MBIST测试的分测验的测试存储器。每个分测验提供完整的配置地址范围。 MBIST装置还包括与测试存储器和有限状态机通信的子测试指针。有限状态机通过子测验指针实现每个子测验的子测序。

4. 发明授权

US07979616B2 System and method for providing a configurable command sequence for a memory interface device 失效
标题翻译：为存储器接口设备提供可配置命令序列的系统和方法
公开(公告)号：US07979616B2
公开(公告)日：2011-07-12
申请号：US11767118
申请日：2007-06-22
申请人： Elianne A. Bravo , Kevin C. Gower , Dustin J. VanStee
发明人： Elianne A. Bravo , Kevin C. Gower , Dustin J. VanStee
IPC分类号： G06F13/00 , G06F3/00 , G06F5/00 , G06F11/00 , G06F12/00 , G06F13/28
CPC分类号： G06F13/1684
摘要： A system and method for providing a configurable command sequence for a memory interface device (MID). The system includes a MID intended for use in a cascade interconnect system and in communication with one or more memory devices. The MID includes a first connection to a high speed bus operating at a first data rate, a second connection to the high speed bus, an alternate communication means and logic. The first connection to the high speed bus includes receiver circuitry operating at the first data rate. The alternate communication means operates at a second data rate that is slower than the first data rate. The logic facilitates receiving commands via the first connection from the high speed bus operating at the first data rate and using a first command sequence. The logic also facilitates receiving the commands via the alternate communication means using a second command sequence which differs from the first command sequence in the speed in which the commands are transferred. The logic further facilitates processing the commands if the commands are directed to the MID and redriving the commands via the second connection onto the high speed bus.
摘要翻译：一种用于为存储器接口设备（MID）提供可配置命令序列的系统和方法。该系统包括MID，其用于级联互连系统并与一个或多个存储器件通信。 MID包括与以第一数据速率操作的高速总线的第一连接，到高速总线的第二连接，备用通信装置和逻辑。与高速总线的第一连接包括以第一数据速率工作的接收器电路。备用通信装置以比第一数据速率慢的第二数据速率工作。该逻辑有助于通过第一连接从第一数据速率的高速总线接收命令并使用第一命令序列。逻辑还通过使用与命令传送的速度不同的第一命令序列的第二命令序列，便于经由备用通信装置接收命令。如果命令指向MID并通过第二连接将命令重新转移到高速总线上，则该逻辑进一步有助于处理命令。

5. 发明申请

US20080320191A1 SYSTEM AND METHOD FOR PROVIDING A CONFIGURABLE COMMAND SEQUENCE FOR A MEMORY INTERFACE DEVICE 失效
标题翻译：用于为存储器接口设备提供可配置命令序列的系统和方法
公开(公告)号：US20080320191A1
公开(公告)日：2008-12-25
申请号：US11767118
申请日：2007-06-22
申请人： Elianne A. Bravo , Kevin C. Gower , Dustin J. VanStee
发明人： Elianne A. Bravo , Kevin C. Gower , Dustin J. VanStee
IPC分类号： G06F13/00
CPC分类号： G06F13/1684
摘要： A system and method for providing a configurable command sequence for a memory interface device (MID). The system includes a MID intended for use in a cascade interconnect system and in communication with one or more memory devices. The MID includes a first connection to a high speed bus operating at a first data rate, a second connection to the high speed bus, an alternate communication means and logic. The first connection to the high speed bus includes receiver circuitry operating at the first data rate. The alternate communication means operates at a second data rate that is slower than the first data rate. The logic facilitates receiving commands via the first connection from the high speed bus operating at the first data rate and using a first command sequence. The logic also facilitates receiving the commands via the alternate communication means using a second command sequence which differs from the first command sequence in the speed in which the commands are transferred. The logic further facilitates processing the commands if the commands are directed to the MID and redriving the commands via the second connection onto the high speed bus.
摘要翻译：一种用于为存储器接口设备（MID）提供可配置命令序列的系统和方法。该系统包括MID，其用于级联互连系统并与一个或多个存储器件通信。 MID包括与以第一数据速率操作的高速总线的第一连接，到高速总线的第二连接，备用通信装置和逻辑。与高速总线的第一连接包括以第一数据速率工作的接收器电路。备用通信装置以比第一数据速率慢的第二数据速率工作。该逻辑有助于通过第一连接从第一数据速率的高速总线接收命令并使用第一命令序列。逻辑还通过使用与命令传送的速度不同的第一命令序列的第二命令序列，便于经由备用通信装置接收命令。如果命令指向MID并通过第二连接将命令重新转移到高速总线上，则该逻辑进一步有助于处理命令。

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