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1. 发明申请

US20100162037A1 Memory System having Spare Memory Devices Attached to a Local Interface Bus 审中-公开
标题翻译：具有连接到本地接口总线的备用内存设备的内存系统
公开(公告)号：US20100162037A1
公开(公告)日：2010-06-24
申请号：US12341472
申请日：2008-12-22
申请人： Warren Edward Maule , Kevin C. Gower , Kenneth Lee Wright
发明人： Warren Edward Maule , Kevin C. Gower , Kenneth Lee Wright
IPC分类号： G06F12/00 , G06F11/20
CPC分类号： G06F13/1684 , G06F11/106 , G11C5/04 , G11C29/83 , Y02D10/14
摘要： A memory system includes a memory controller, one or more memory channel(s), and a memory subsystem having a memory interface device (e.g. a hub or buffer device) located on a memory subsystem (e.g. a DIMM) coupled to the memory channel to communicate with the memory device(s) array. This buffered DIMM is provided with one or more spare chips on the DIMM, wherein the data bits sourced from the spare chips are connected to the memory hub device and the bus to the DIMM includes only those data bits used for normal operation. The buffered DIMM with one or more spare chips on the DIMM has the spare memory shared among all the ranks, and the memory hub device includes separate control bus(es) for the spare memory device to allow the spare memory device(s) to be utilized to replace one or more failing bits and/or devices within any rank of memory in the memory subsystem.
摘要翻译：存储器系统包括存储器控制器，一个或多个存储器通道和存储器子系统，该存储器子系统具有位于耦合到存储器通道的存储器子系统（例如，DIMM）上的存储器接口设备（例如，集线器或缓冲设备）与存储器件阵列通信。该缓冲DIMM在DIMM上提供一个或多个备用芯片，其中从备用芯片获取的数据位连接到存储器集线器设备，并且到DIMM的总线仅包括用于正常操作的那些数据位。在DIMM上具有一个或多个备用芯片的缓冲DIMM具有在所有等级中共享的备用存储器，并且存储器集线器设备包括用于备用存储器设备的单独的控制总线，以允许备用存储器设备用于替换存储器子系统中的任何等级的存储器内的一个或多个故障位和/或设备。

2. 发明授权

US08639874B2 Power management of a spare DRAM on a buffered DIMM by issuing a power on/off command to the DRAM device 失效
标题翻译：通过向DRAM设备发出电源开/关命令，对缓冲DIMM上的备用DRAM进行电源管理
公开(公告)号：US08639874B2
公开(公告)日：2014-01-28
申请号：US12341515
申请日：2008-12-22
申请人： Warren Edward Maule , Kevin C. Gower , Kyu-hyoun Kim , Dustin James VanStee
发明人： Warren Edward Maule , Kevin C. Gower , Kyu-hyoun Kim , Dustin James VanStee
IPC分类号： G06F12/06
CPC分类号： G11C5/06 , G11C5/04 , G11C5/14 , G11C11/4074
摘要： A computer memory, having one or more of a semiconductor memory device having an internal memory array comprising a plurality of semiconductor dynamic random access memory (DRAM) cells arranged in a matrix of rows and columns, and provided as a memory module rank of such memory devices arranged in an array on a DIMM of one or more of said semiconductor memory device on a substrate which can be coupled via a memory device data interface to a memory system as a memory subsystem, each of said memory device having a low power shut-down state that can be activated using a common memory data interface. Control of power to a DRAM issues over the data interface two commands to a DRAM power control command decode, a power-state program signal and a power-state reset signal as a power-state control commands to control the power state of said DRAM, and to activate for READ/WRITE a memory cell as a normal active or spare device.
摘要翻译：一种具有一个或多个具有内部存储器阵列的半导体存储器件的计算机存储器，所述内部存储器阵列包括排列成行和列的矩阵的多个半导体动态随机存取存储器（DRAM）单元，并被提供为这种存储器的存储器模块等级在基板上的一个或多个所述半导体存储器件的DIMM上布置的阵列中的器件，其可以经由存储器件数据接口耦合到作为存储器子系统的存储器系统，每个所述存储器件具有低功率闭合 - 可以使用公共存储器数据接口激活。通过数据接口对DRAM的功率的控制问题DRAM功率控制命令的两个命令解码，功率状态程序信号和功率状态复位信号作为功率状态控制命令来控制所述DRAM的功率状态，并激活用于将存储器单元作为正常的有源或备用设备读/写。

3. 发明申请

US20100162020A1 Power Management of a Spare DRAM on a Buffered DIMM by Issuing a Power On/Off Command to the DRAM Device 失效
标题翻译：通过向DRAM器件发出电源开/关命令，对缓冲DIMM上的备用DRAM进行电源管理
公开(公告)号：US20100162020A1
公开(公告)日：2010-06-24
申请号：US12341515
申请日：2008-12-22
申请人： Warren Edward Maule , Kevin C. Gower , Kyu-hyoun Kim , Dustin James VanStee
发明人： Warren Edward Maule , Kevin C. Gower , Kyu-hyoun Kim , Dustin James VanStee
IPC分类号： G06F1/32 , G06F12/06
CPC分类号： G11C5/06 , G11C5/04 , G11C5/14 , G11C11/4074
摘要： A computer memory, having one or more of a semiconductor memory device having an internal memory array comprising a plurality of semiconductor dynamic random access memory (DRAM) cells arranged in a matrix of rows and columns, and provided as a memory module rank of such memory devices arranged in an array on a DIMM of one or more of said semiconductor memory device on a substrate which can be coupled via a memory device data interface to a memory system as a memory subsystem, each of said memory device having a low power shut-down state that can be activated using a common memory data interface. Control of power to a DRAM issues over the data interface two commands to a DRAM power control command decode, a power-state program signal and a power-state reset signal as a power-state control commands to control the power state of said DRAM, and to activate for READ/WRITE a memory cell as a normal active or spare device.
摘要翻译：一种具有一个或多个具有内部存储器阵列的半导体存储器件的计算机存储器，所述内部存储器阵列包括排列成行和列的矩阵的多个半导体动态随机存取存储器（DRAM）单元，并被提供为这种存储器的存储器模块等级在基板上的一个或多个所述半导体存储器件的DIMM上布置的阵列中的器件，其可以经由存储器件数据接口耦合到作为存储器子系统的存储器系统，每个所述存储器件具有低功率闭合 - 可以使用公共存储器数据接口激活。通过数据接口对DRAM的功率的控制问题DRAM功率控制命令的两个命令解码，功率状态程序信号和功率状态复位信号作为功率状态控制命令来控制所述DRAM的功率状态，并激活用于将存储器单元作为正常的有源或备用设备读/写。

4. 发明授权

US08892821B2 Method and system for thread-based memory speculation in a memory subsystem of a data processing system 有权
标题翻译：在数据处理系统的存储器子系统中线程内存推测的方法和系统
公开(公告)号：US08892821B2
公开(公告)日：2014-11-18
申请号：US10733953
申请日：2003-12-10
申请人： Ravi Kumar Arimilli , Sanjeev Ghai , Warren Edward Maule
发明人： Ravi Kumar Arimilli , Sanjeev Ghai , Warren Edward Maule
IPC分类号： G06F12/00 , G06F12/08 , G06F12/02
CPC分类号： G06F12/0215 , G06F12/0831 , G06F2212/507
摘要： A data processing system includes a system memory, one or more processing cores, and a memory controller that controls access to a system memory. The memory controller includes a memory speculation mechanism that stores historical information regarding prior memory accesses. In response to a memory access request, the memory controller speculatively initiates access to the system memory based upon the historical information in the memory speculation mechanism in advance of receipt of a coherency message indicating that the memory access request is to be serviced by reference to the system memory.
摘要翻译：数据处理系统包括系统存储器，一个或多个处理核心以及控制对系统存储器的访问的存储器控制器。存储器控制器包括存储器推测机制，其存储关于先前存储器访问的历史信息。响应于存储器访问请求，存储器控制器基于存储器推测机制中的历史信息推测地启动对系统存储器的访问，在接收到指示将通过参考的存储器访问请求被服务的一致性消息之前系统内存

5. 发明授权

US07516264B2 Programmable bank/timer address folding in memory devices 失效
标题翻译：可编程存储器/定时器地址折叠存储器件
公开(公告)号：US07516264B2
公开(公告)日：2009-04-07
申请号：US11054066
申请日：2005-02-09
申请人： Mark Andrew Brittain , Warren Edward Maule , Gary Alan Morrison , Jeffrey Adam Stuecheli
发明人： Mark Andrew Brittain , Warren Edward Maule , Gary Alan Morrison , Jeffrey Adam Stuecheli
IPC分类号： G06F12/06
CPC分类号： G06F13/1647 , G11C5/04 , Y02D10/14
摘要： A set of N copies of bank control logic are provided for tracking the banks within the memory modules (DRAMS). When the total number of banks within the memory module(s) is greater than N, the addresses of particular banks are folded into a single grouping. The banks are represented by the N copies of the bank control logic even when the total number of banks is greater than N. Each bank within the group is tagged as being busy when any one of the banks in the group is the target of a memory access request. The algorithm folds the addresses of the banks in an order that substantially minimizes the likelihood that a bank that is in a busy or false busy state will be the target of another memory access request. Power and logic savings are recognized as only N copies of bank control logic have to be supported.
摘要翻译：提供了一组用于跟踪存储器模块（DRAMS）内的存储体的银行控制逻辑的副本。当存储器模块中的总线数大于N时，特定存储体的地址被折叠成单个组。即使当银行总数大于N时，银行也由银行控制逻辑的N个副本表示。当组中的任何一个银行是存储器的目标时，组内的每个银行被标记为忙碌访问请求。该算法按照使得处于忙或伪忙状态的存储体将成为另一个存储器访问请求的目标的可能性基本上最小化的顺序来折叠存储体的地址。功率和逻辑节省被认为只需要支持银行控制逻辑的N个副本。

6. 发明授权

US07493456B2 Memory queue with supplemental locations for consecutive addresses 有权
标题翻译：具有连续地址的补充位置的存储器队列
公开(公告)号：US07493456B2
公开(公告)日：2009-02-17
申请号：US11549429
申请日：2006-10-13
申请人： Mark Andrew Brittain , Warren Edward Maule , Eric Eugene Retter
发明人： Mark Andrew Brittain , Warren Edward Maule , Eric Eugene Retter
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/1642
摘要： A memory controller includes an address queue with address queue locations that may expand to store address commands that point to consecutive locations in memory. In this manner, multiple address commands may combine together in a common expanded address queue location. In one embodiment, each address queue location includes a main information portion and a supplemental information portion. The supplemental information portion is smaller than the main information portion. The main information portion stores the target address information of a first address command. When the address queue receives an address command with a target address that is consecutive to the target address of the first command, then the supplemental address portion stores a subset of the target address of the second command.
摘要翻译：存储器控制器包括具有地址队列位置的地址队列，其可以扩展以存储指向存储器中的连续位置的地址命令。以这种方式，多个地址命令可以在公共扩展地址队列位置中组合在一起。在一个实施例中，每个地址队列位置包括主信息部分和补充信息部分。辅助信息部分小于主信息部分。主信息部分存储第一地址命令的目标地址信息。当地址队列接收到具有与第一命令的目标地址连续的目标地址的地址命令时，补充地址部分存储第二命令的目标地址的子集。

7. 发明授权

US07467323B2 Data processing system and method for efficient storage of metadata in a system memory 失效
标题翻译：用于在系统存储器中有效存储元数据的数据处理系统和方法
公开(公告)号：US07467323B2
公开(公告)日：2008-12-16
申请号：US11055640
申请日：2005-02-10
申请人： James Stephen Fields, Jr. , Sanjeev Ghai , Warren Edward Maule , Jeffrey Adam Stuecheli
发明人： James Stephen Fields, Jr. , Sanjeev Ghai , Warren Edward Maule , Jeffrey Adam Stuecheli
IPC分类号： G06F11/00 , G06F12/00 , G11C29/00
CPC分类号： G06F11/1064 , G06F12/0831
摘要： A cache coherent data processing system includes a plurality of processing units each having at least an associated cache, a system memory, and a memory controller that is coupled to and controls access to the system memory. The system memory includes a plurality of storage locations for storing a memory block of data, where each of the plurality of storage locations is sized to store a sub-block of data. The system memory further includes metadata storage for storing metadata, such as a domain indicator, describing the memory block. In response to a failure of a storage location for a particular sub-block among the plurality of sub-blocks, the memory controller overwrites at least a portion of the metadata in the metadata storage with the particular sub-block of data.
摘要翻译：高速缓存一致性数据处理系统包括多个处理单元，每个处理单元至少具有相关联的高速缓存，系统存储器和存储器控制器，其耦合到并控制对系统存储器的访问。系统存储器包括用于存储数据的存储块的多个存储位置，其中多个存储位置中的每一个被设置为存储数据的子块。系统存储器还包括用于存储描述存储器块的诸如域指示符的元数据的元数据存储。响应于多个子块中的特定子块的存储位置的故障，存储器控制器使用特定的数据子块来覆盖元数据存储器中的元数据的至少一部分。

8. 发明授权

US08185800B2 System for error control coding for memories of different types and associated methods 有权
标题翻译：用于不同类型和相关方法的存储器的错误控制编码系统
公开(公告)号：US08185800B2
公开(公告)日：2012-05-22
申请号：US12023408
申请日：2008-01-31
申请人： Paul W. Coteus , Luis A. Lastras-Montano , Warren Edward Maule , Barry M. Trager , Shmuel Winograd
发明人： Paul W. Coteus , Luis A. Lastras-Montano , Warren Edward Maule , Barry M. Trager , Shmuel Winograd
IPC分类号： G11C29/00
CPC分类号： H03M13/1545 , G06F11/1048 , H03M13/1515 , H03M13/154 , H03M13/35 , H03M13/353 , H03M13/3707 , H03M13/6511 , H03M13/6516
摘要： A system to improve error control coding. An example system includes memory chips of at least two different kinds. The system also includes error control encoder circuitry to substantially encode data for storage in any memory rank. The system further includes error control decoder circuitry to substantially decode encoded data received from any memory rank. The error decoder circuitry is comprised of a slow decoder and a fast decoder.
摘要翻译：一种改进错误控制编码的系统。示例系统包括至少两种不同类型的存储器芯片。该系统还包括错误控制编码器电路，用于基本上编码数据以存储在任何存储器级中。该系统还包括错误控制解码器电路，以基本上解码从任何存储器等级接收的编码数据。错误解码器电路由慢解码器和快速解码器组成。

9. 发明授权

US07130967B2 Method and system for supplier-based memory speculation in a memory subsystem of a data processing system 失效
标题翻译：数据处理系统存储子系统中供应商内存推测的方法和系统
公开(公告)号：US07130967B2
公开(公告)日：2006-10-31
申请号：US10733948
申请日：2003-12-10
申请人： Ravi Kumar Arimilli , Sanjeev Ghai , Warren Edward Maule
发明人： Ravi Kumar Arimilli , Sanjeev Ghai , Warren Edward Maule
IPC分类号： G06F12/00
CPC分类号： G06F9/383 , G06F9/3832 , G06F9/3851 , G06F12/0215
摘要： A data processing system includes one or more processing cores, a system memory having multiple rows of data storage, and a memory controller that controls access to the system memory and performs supplier-based memory speculation. The memory controller includes a memory speculation table that stores historical information regarding prior memory accesses. In response to a memory access request, the memory controller directs an access to a selected row in the system memory to service the memory access request. The memory controller speculatively directs that the selected row will continue to be energized following the access based upon the historical information in the memory speculation table, so that access latency of an immediately subsequent memory access is reduced.
摘要翻译：数据处理系统包括一个或多个处理核心，具有多行数据存储的系统存储器，以及控制对系统存储器的访问并执行基于供应商的存储器推测的存储器控制器。存储器控制器包括存储有关先前存储器访问的历史信息的存储器推测表。响应于存储器访问请求，存储器控制器引导对系统存储器中的所选行的访问以服务存储器访问请求。存储器控制器推测地指示在基于存储器推测表中的历史信息的访问之后，所选择的行将继续被通电，使得紧随其后的存储器访问的访问等待时间减少。

10. 发明授权

US5954825A Method for isolating faults on a clocked synchronous bus 失效
标题翻译：在时钟同步总线上隔离故障的方法
公开(公告)号：US5954825A
公开(公告)日：1999-09-21
申请号：US837183
申请日：1997-04-11
申请人： John Michael Kaiser , Warren Edward Maule
发明人： John Michael Kaiser , Warren Edward Maule
IPC分类号： G06F11/30 , G06F11/22 , G06F13/00 , G06F11/00
CPC分类号： G06F11/2268
摘要： A shift register is used to latch the bus-driver-enable signal for each potential bus driver during each system clock cycle. The shift register clock will freeze upon receipt of a "check stop" signal. Once frozen, the shift register can be scanned for fault isolation analysis.
摘要翻译：移位寄存器用于在每个系统时钟周期期间为每个潜在总线驱动器锁存总线驱动器使能信号。移位寄存器时钟将在收到“检查停止”信号时冻结。一旦冻结，可以扫描移位寄存器进行故障隔离分析。

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