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51. 发明授权

US5716885A Method for manufacturing NAND type mask-ROM having improved cell current 失效
标题翻译：制造具有改善的电池电流的NAND型掩模ROM的方法
公开(公告)号：US5716885A
公开(公告)日：1998-02-10
申请号：US494845
申请日：1995-06-26
申请人： Byeung-Chul Kim , Jung-Dal Choi
发明人： Byeung-Chul Kim , Jung-Dal Choi
IPC分类号： H01L27/10 , H01L21/8246 , H01L27/112
CPC分类号： H01L27/11266 , H01L27/112
摘要： A method for manufacturing a mask-ROM comprises a first process of forming a spacer on a side wall of a gate electrode; a second process of eliminating the spacer disposed on the side wall of the gate electrode of an on-cell; and a third process of doping impurity on the entire surface of a semiconductor substrate formed in the preceding process.
摘要翻译：掩模ROM的制造方法包括在栅电极的侧壁上形成间隔物的第一工序; 消除设置在电池单元的栅电极的侧壁上的间隔物的第二过程; 以及在前述工艺中形成的半导体衬底的整个表面上掺杂杂质的第三工序。

52. 发明授权

US5015886A Programmable sequential-code recognition circuit 失效
标题翻译：可编程顺序码识别电路
公开(公告)号：US5015886A
公开(公告)日：1991-05-14
申请号：US356172
申请日：1989-05-24
申请人： Jung-Dal Choi , Hyung-Kyu Yim , Jae-Young Do , Jin-Ki Kim
发明人： Jung-Dal Choi , Hyung-Kyu Yim , Jae-Young Do , Jin-Ki Kim
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3185 , G06F7/02 , G06F11/28 , H03M7/00
CPC分类号： G06F11/28 , G01R31/31701 , G06F7/02
摘要： There is disclosed a programmable sequential code recognition circuit comprising an individual code recognition circuit for recognizing each input code, and a sequence recognition circuit for recognizing the sequency given for individual codes obtained by combination of input signals, so that a specific mode may be selected by the input combination sequentially inputted.
摘要翻译：公开了一种包括用于识别每个输入代码的单独代码识别电路的可编程序序代码识别电路，以及用于识别通过输入信号组合而获得的各个代码给出的顺序的序列识别电路，从而可以通过顺序地输入输入组合。

53. 发明授权

US09450049B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09450049B2
公开(公告)日：2016-09-20
申请号：US14276421
申请日：2014-05-13
申请人： Tae-Yong Kwon , Sang-Su Kim , Jung-Gil Yang , Jung-Dal Choi
发明人： Tae-Yong Kwon , Sang-Su Kim , Jung-Gil Yang , Jung-Dal Choi
IPC分类号： H01L27/00 , H01L29/10 , H01L29/205 , H01L29/78 , H01L29/165 , H01L27/088 , H01L21/8238 , H01L21/84 , H01L29/66 , H01L27/092 , H01L27/12
CPC分类号： H01L29/1054 , H01L21/823821 , H01L21/845 , H01L27/088 , H01L27/0924 , H01L27/1211 , H01L29/165 , H01L29/20 , H01L29/205 , H01L29/66522 , H01L29/6681 , H01L29/78 , H01L29/7842 , H01L29/785
摘要： A semiconductor device includes a substrate, a compound semiconductor layer, and first and second semiconductor patterns. The substrate includes first and second regions. The first semiconductor pattern is on the compound semiconductor layer of the first region and includes an element semiconductor. The second semiconductor pattern is on the compound semiconductor layer of the second region and includes a Group III-V semiconductor material.
摘要翻译：半导体器件包括衬底，化合物半导体层以及第一和第二半导体图案。衬底包括第一和第二区域。第一半导体图案在第一区域的化合物半导体层上，并且包括元件半导体。第二半导体图案在第二区域的化合物半导体层上，并且包括III-V族半导体材料。

54. 发明授权

US09373664B2 Variable resistance memory devices and methods of manufacturing the same 有权
标题翻译：可变电阻存储器件及其制造方法
公开(公告)号：US09373664B2
公开(公告)日：2016-06-21
申请号：US14682506
申请日：2015-04-09
申请人： Dong-Jun Seong , Youn-Seon Kang , Seung-Jae Jung , Jung-Dal Choi
发明人： Dong-Jun Seong , Youn-Seon Kang , Seung-Jae Jung , Jung-Dal Choi
IPC分类号： H01L29/06 , H01L27/24 , H01L45/00
CPC分类号： H01L27/2463 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/08 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： A variable resistance memory device, and methods of manufacturing the same, include a plurality of first conductive structures extending in a first direction, a plurality of second conductive structures extending in a second direction crossing the first direction over the first conductive structures, the second conductive structures, and a plurality of memory cells that are formed at intersections at which the first conductive structures and the second conductive structures overlap each other, and each includes a selection element and a variable resistance element sequentially stacked. An upper surface of each of the first conductive structures has a width in the second direction less than a width of a bottom surface of each of the selection elements.
摘要翻译：可变电阻存储器件及其制造方法包括沿第一方向延伸的多个第一导电结构，沿与第一导电结构相交的第一方向的第二方向延伸的多个第二导电结构，第二导电结构和形成在第一导电结构和第二导电结构彼此重叠的交点处的多个存储单元，并且每个存储单元包括依次堆叠的选择元件和可变电阻元件。每个第一导电结构的上表面在第二方向上的宽度小于每个选择元件的底表面的宽度。

55. 发明授权

US08228738B2 NAND flash memory device having dummy memory cells and methods of operating same 有权
标题翻译：具有虚拟存储单元的NAND闪存器件及其操作方法
公开(公告)号：US08228738B2
公开(公告)日：2012-07-24
申请号：US12977419
申请日：2010-12-23
申请人： Ki-Tae Park , Jung-Dal Choi , Jong-Sun Sel , Yoo-Cheol Shin
发明人： Ki-Tae Park , Jung-Dal Choi , Jong-Sun Sel , Yoo-Cheol Shin
IPC分类号： G11C16/04 , G11C16/06 , G11C16/10
CPC分类号： G11C16/0483 , G11C16/107 , G11C16/12 , G11C16/3445
摘要： A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.
摘要翻译： NAND闪速存储器件包括控制电路，其被配置为在编程操作期间将第一字线电压施加到多个串联存储器单元中的未选择的电压，第二字线电压大于第一字线电压到多个存储单元中的一个选择的一个，以及比第一字线电压低的第三字线电压到与多个存储单元串联连接的虚拟存储单元。在其他实施例中，控制电路被配置为在与每个擦除操作之间的每个擦除操作之前和/或之后对与其串联的多个存储器单元进行编程。在其他实施例中，控制电路被配置为在擦除与其串联连接的多个存储器单元时，放弃擦除伪存储器单元。

56. 发明申请

US20120068245A1 NON-VOLATILE MEMORY DEVICES INCLUDING BLOCKING INSULATION PATTERNS WITH SUB-LAYERS HAVING DIFFERENT ENERGY BAND GAPS 有权
标题翻译：非易失性存储器件，包括具有不同能量带GAAS的子层的阻塞绝缘图案
公开(公告)号：US20120068245A1
公开(公告)日：2012-03-22
申请号：US13305930
申请日：2011-11-29
申请人： Ju-Hyung Kim , Sung-Il Chang , Chang-Seok Kang , Jung-Dal Choi
发明人： Ju-Hyung Kim , Sung-Il Chang , Chang-Seok Kang , Jung-Dal Choi
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11517 , H01L27/11529 , H01L27/11563 , H01L27/11568 , H01L29/42324 , H01L29/4234 , H01L29/42348 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/7883
摘要： A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed.
摘要翻译：非易失性存储器件可以包括半导体衬底和半导体衬底上的隔离层，其中隔离层限定半导体衬底的有源区。可以在半导体衬底的有源区上设置隧道绝缘层，并且可以在隧道绝缘层上设置电荷存储图案。可以在电荷存储图案上提供界面层图案，并且可以在界面层图案上提供阻挡绝缘图案。此外，块绝缘图案可以包括高k介电材料，并且界面层图案和阻挡绝缘图案可以包括不同的材料。可以在阻挡绝缘层上设置控制栅电极，使得阻挡绝缘图案位于界面层图案和控制栅电极之间。还讨论了相关方法。

57. 发明授权

US08085607B2 3-level non-volatile semiconductor memory device and method of driving the same 失效
标题翻译： 3级非易失性半导体存储器件及其驱动方法
公开(公告)号：US08085607B2
公开(公告)日：2011-12-27
申请号：US12830464
申请日：2010-07-06
申请人： Ki-Tae Park , Jung-Dal Choi , Sung-Kyu Jo
发明人： Ki-Tae Park , Jung-Dal Choi , Sung-Kyu Jo
IPC分类号： G11C7/00
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/24
摘要： A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch data to the first memory cell, and a second latch block coupled to the second bitline and the first latch block, and configured to transfer a second latch data to the second memory cell.
摘要翻译：用于非易失性半导体存储器件的页面缓冲器包括被配置为将耦合到第一存储器单元的第一位线耦合到耦合到第二存储器单元的第二位线的开关，耦合到第一位线并被配置为传送的第一锁存块向第一存储器单元提供第一锁存数据，以及耦合到第二位线和第一锁存块的第二锁存块，并且被配置为将第二锁存数据传送到第二存储器单元。

58. 发明授权

US08072804B2 Multi-bit flash memory devices and methods of programming and erasing the same 有权
标题翻译：多位闪存设备及其编程和擦除方法
公开(公告)号：US08072804B2
公开(公告)日：2011-12-06
申请号：US12471729
申请日：2009-05-26
申请人： Se-Hoon Lee , Choong-Ho Lee , Jung-Dal Choi
发明人： Se-Hoon Lee , Choong-Ho Lee , Jung-Dal Choi
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C2211/5641
摘要： A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit is provided, which is configured to program a first page of non-volatile memory cells in the array as M-bit cells during a first programming operation and further configured to program the first page of non-volatile memory cells as N-bit cells during a second programming operation. The first and second programming operations are separated in time by at least one operation to erase the first page of non-volatile memory cells. M and N are unequal integers greater than zero.
摘要翻译：非易失性存储器件包括被配置为支持单位和多位编程状态的非易失性存储器单元的阵列。提供了一种控制电路，其被配置为在第一编程操作期间将阵列中的第一页非易失性存储单元编程为M位单元，并且还被配置为将第一页非易失性存储单元编程为N- 在第二次编程操作期间。第一和第二编程操作通过至少一个擦除非易失性存储器单元的第一页的操作在时间上被分离。 M和N是不等于零的整数。

59. 发明授权

US08035151B2 Semiconductor device capable of suppressing short channel effect and method of fabricating the same 有权
标题翻译：能够抑制短路效应的半导体装置及其制造方法
公开(公告)号：US08035151B2
公开(公告)日：2011-10-11
申请号：US12382385
申请日：2009-03-16
申请人： Chang-Hyun Lee , Jung-Dal Choi
发明人： Chang-Hyun Lee , Jung-Dal Choi
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/26586 , H01L27/11526 , H01L27/11529 , H01L27/11568 , H01L27/11573 , H01L29/1083
摘要： A semiconductor device includes a semiconductor substrate including at least one memory channel region and at least one memory source/drain region, the memory channel region and the memory source/drain region being arranged alternately, and at least one word line on the memory channel region, wherein the memory source/drain region has a higher net impurity concentration than the memory channel region.
摘要翻译：半导体器件包括半导体衬底，该半导体衬底包括至少一个存储器沟道区和至少一个存储源/漏区，存储器沟道区和存储源/漏区被交替排列，以及存储器沟道区上的至少一个字线其中，所述存储器源极/漏极区域具有比所述存储器沟道区域更高的净杂质浓度。

60. 发明申请

US20110217835A1 METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH SIDEWALL CONDUCTIVE PATTERNS 有权
标题翻译：用导电模式制作半导体器件的方法
公开(公告)号：US20110217835A1
公开(公告)日：2011-09-08
申请号：US13110113
申请日：2011-05-18
申请人： Jong-Sun Sel , Jung-Dal Choi , Joon-Hee Lee , Hwa-Kyung Shin
发明人： Jong-Sun Sel , Jung-Dal Choi , Joon-Hee Lee , Hwa-Kyung Shin
IPC分类号： H01L21/28
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/105 , H01L27/11529
摘要： A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive pattern. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.
摘要翻译：公开了一种栅极图案，其包括半导体衬底，下导电图案，上导电图案和侧壁导电图案。下导电图案在基板上。绝缘图案位于下导电图案上。上导电图案位于与下导电图案相对的绝缘图案上。侧壁导电图案位于上导电图案和下导电图案的侧壁的至少一部分上。侧壁导电图形电连接上导电图案和下导电图案。下导电图案的上边缘部分可以相对于下导电图案的下边缘部分凹进，以在其上限定凸缘。侧壁导电图案可以直接在下导电图案的凹陷的上边缘部分的凸缘和侧壁上。

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