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51. 发明授权

US07577793B2 Patrol snooping for higher level cache eviction candidate identification 失效
标题翻译：巡逻窥探高级缓存驱逐候选人识别
公开(公告)号：US07577793B2
公开(公告)日：2009-08-18
申请号：US11335765
申请日：2006-01-19
申请人： John Michael Borkenhagen , Brian T. Vanderpool
发明人： John Michael Borkenhagen , Brian T. Vanderpool
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/128 , G06F12/0897
摘要： A computer system having patrol snoop sequencer that sequences through addresses of cache lines held in a higher level cache, making snoop reads using those addresses to a lower level cache. If a particular cache line held in the higher level cache is not held in the lower level cache, the particular cache line is identified as an eviction candidate in the higher level cache when a new cache line must be loaded into the higher level cache.
摘要翻译：具有巡逻窥探音序器的计算机系统，其通过保持在较高级别高速缓存中的高速缓存行的地址进行排序，使得使用这些地址进行窥探读取到较低级别的高速缓存。如果保持在较高级别高速缓存中的特定高速缓存行不被保持在较低级高速缓存中，则当新的高速缓存行必须被加载到更高级高速缓存中时，特定高速缓存行被标识为较高级高速缓存中的逐出候选。

52. 发明授权

US07546410B2 Self timed memory chip having an apportionable data bus 失效
标题翻译：具有可分配数据总线的自定时存储芯片
公开(公告)号：US07546410B2
公开(公告)日：2009-06-09
申请号：US11459947
申请日：2006-07-26
申请人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , Andrew Benson Maki , Mark Owen Maxson
发明人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , Andrew Benson Maki , Mark Owen Maxson
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F13/4243 , G06F13/4256
摘要： A self timed memory chip having an apportionable data bus. Access timing to an array on the memory chip is dynamically determined by circuitry on the memory chip. A ring oscillator on the memory chip has a frequency that is indicative of how fast an array on the memory chip can be accessed. The ring oscillator includes a bit line that is periodically charged and a memory element that subsequently discharges the bit line. The memory chip has a data bus interface having a number of bits. The data bus interface has a first number of bits apportioned to write data and a second number of bits apportioned to read data. The first number of bits and the second number of bits is programmable.
摘要翻译：具有可分配数据总线的自定时存储芯片。存储器芯片上的阵列的访问定时由存储器芯片上的电路动态地确定。存储器芯片上的环形振荡器具有表示可以访问存储器芯片上的阵列的速度的频率。环形振荡器包括周期性充电的位线和随后对位线进行放电的存储元件。该存储器芯片具有数位总线接口，该数据总线接口具有多个位。数据总线接口具有分配给写入数据的第一数量位和分配为读取数据的第二数量的位。第一位数和第二位数是可编程的。

53. 发明授权

US07490186B2 Memory system having an apportionable data bus and daisy chained memory chips 有权
标题翻译：具有分配数据总线和菊花链存储器芯片的存储器系统
公开(公告)号：US07490186B2
公开(公告)日：2009-02-10
申请号：US11459959
申请日：2006-07-26
申请人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , Andrew Benson Maki , Mark Owen Maxson
发明人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , Andrew Benson Maki , Mark Owen Maxson
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/1684
摘要： A memory system having a memory controller and a daisy chain of memory chips. The memory controller is coupled to memory chips in the daisy chain of memory chips by an address/command bus chain. The memory controller is coupled to memory chips in the daisy chain of memory chips by a data bus chain having a number of data bus bits. The data bus chain has a first portion of data bus bits dedicated to transmitting write data from the memory controller to a memory chip. The data bus chain has a second portion of data bus bits dedicated to transmitting read data from a memory chip to the memory controller. Apportionment of data bus bits between the first portion and the second portion is programmable. Programming is done by pin connection, scanning of a value, or by request from a processor coupled to the memory controller.
摘要翻译：一种具有存储器控制器和存储器芯片的菊花链的存储器系统。存储器控制器通过地址/命令总线链耦合到存储器芯片的菊花链中的存储器芯片。存储器控制器通过具有多个数据总线位的数据总线链耦合到存储器芯片的菊花链中的存储器芯片。数据总线链具有专用于从存储器控制器向存储器芯片发送写数据的数据总线位的第一部分。数据总线链具有专用于从存储器芯片向存储器控制器发送读取数据的数据总线位的第二部分。数据总线位在第一部分和第二部分之间的分配是可编程的。编程通过引脚连接，值的扫描，或者通过与存储器控制器耦合的处理器的请求来完成。

54. 发明申请

US20090006790A1 High Capacity Memory Subsystem Architecture Storing Interleaved Data for Reduced Bus Speed 有权
标题翻译：高容量存储器子系统架构存储用于减少总线速度的交错数据
公开(公告)号：US20090006790A1
公开(公告)日：2009-01-01
申请号：US11768995
申请日：2007-06-27
申请人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
发明人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
IPC分类号： G06F12/06
CPC分类号： G06F13/1684 , G06F13/1689
摘要： A high-capacity memory subsystem architecture utilizes multiple memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving
摘要翻译：高容量存储器子系统架构利用布置在一个或多个簇中的多个存储器模块，每个存储器模块连接到相应的集线器，该集线器又连接到存储器控制器。在集群内，数据被交织，以便每个数据访问命令访问集群的所有模块。集线器以较低的总线频率与存储器模块通信，但是在多个模块之间分配数据使集群能够保持存储器 - 控制器到集线器总线的复合数据速率。优选地，存储器系统采用具有双模操作的缓冲存储器芯片，其中之一支持数据被交错的集群配置，并且通信总线以减小的总线宽度和/或减小的总线频率进行操作以匹配交织电平

55. 发明申请

US20090006775A1 Dual-Mode Memory Chip for High Capacity Memory Subsystem 有权
标题翻译：用于大容量存储器子系统的双模存储芯片
公开(公告)号：US20090006775A1
公开(公告)日：2009-01-01
申请号：US11769011
申请日：2007-06-27
申请人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
发明人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
IPC分类号： G06F12/00
CPC分类号： G06F13/1684 , G06F12/0607 , G06F13/1694 , Y02D10/13 , Y02D10/14
摘要： A dual-mode memory chip supports a first operation mode in which received data access commands contain chip select data to identify the chip addressed by the command, and control logic in the memory chip determines whether the command is addressed to the chip, and a second operation mode in which the received data access command addresses a set of multiple chips. Preferably, the first mode supports a daisy-chained configuration of memory chips. Preferably the second mode supports a hierarchical interleaved memory subsystem, in which each addressable set of chips is configured as a tree, command and write data being propagated down the tree, the number of chips increasing at each succeeding level of the tree.
摘要翻译：双模存储器芯片支持第一操作模式，其中接收的数据访问命令包含芯片选择数据以识别由命令寻址的芯片，并且存储器芯片中的控制逻辑确定命令是否寻址到芯片，第二操作模式操作模式，其中所接收的数据访问命令寻址一组多个芯片。优选地，第一模式支持存储芯片的菊花链配置。优选地，第二模式支持分层交错存储器子系统，其中每个可寻址的芯片集合被配置为树，命令和写入数据在树下传播，在树的每个后续级别增加的码片数量。

56. 发明申请

US20090006715A1 Memory Chip for High Capacity Memory Subsystem Supporting Multiple Speed Bus 有权
标题翻译：用于支持多速总线的大容量存储器子系统的存储器芯片
公开(公告)号：US20090006715A1
公开(公告)日：2009-01-01
申请号：US11769006
申请日：2007-06-27
申请人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
发明人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
IPC分类号： G06F12/00
CPC分类号： G06F13/4243
摘要： A memory module contains an interface for receiving memory access commands from an external source, in which a first portion of the interface receives memory access data at a first bus frequency and a second portion of the interface receives memory access data at a second different bus frequency. Preferably, the memory module contains a second interface for re-transmitting memory access data, also operating at dual frequency. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports dual-speed buses for receiving and re-transmitting different parts of data access commands, and another of which supports conventional daisy-chaining.
摘要翻译：存储器模块包含用于从外部源接收存储器访问命令的接口，其中接口的第一部分以第一总线频率接收存储器访问数据，并且接口的第二部分以第二不同总线频率接收存储器访问数据。优选地，存储器模块包含第二接口，用于重新传输也以双频操作的存储器访问数据。存储器模块优选地用于以树形结构组织的高容量存储器子系统，其中数据访问是交错的。优选地，存储器模块具有多模式操作，其中之一支持用于接收和重新传送数据访问命令的不同部分的双速总线，另一个支持常规的菊花链。

57. 发明申请

US20090006705A1 Hub for Supporting High Capacity Memory Subsystem 有权
标题翻译：支持高容量内存子系统的集线器
公开(公告)号：US20090006705A1
公开(公告)日：2009-01-01
申请号：US11769019
申请日：2007-06-27
申请人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
发明人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
IPC分类号： G06F13/36
CPC分类号： G06F13/4243
摘要： A high-capacity memory subsystem architecture utilizes multiple memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving
摘要翻译：高容量存储器子系统架构利用布置在一个或多个簇中的多个存储器模块，每个存储器模块连接到相应的集线器，该集线器又连接到存储器控制器。在集群内，数据被交织，以便每个数据访问命令访问集群的所有模块。集线器以较低的总线频率与存储器模块通信，但是在多个模块之间分配数据使集群能够保持存储器 - 控制器到集线器总线的复合数据速率。优选地，存储器系统采用具有双模操作的缓冲存储器芯片，其中之一支持数据被交错的集群配置，并且通信总线以减小的总线宽度和/或减小的总线频率进行操作以匹配交织电平

58. 发明申请

US20080040529A1 Memory Chip Having an Apportionable Data Bus 有权
标题翻译：具有可分配数据总线的存储芯片
公开(公告)号：US20080040529A1
公开(公告)日：2008-02-14
申请号：US11459943
申请日：2006-07-26
申请人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , Andrew Benson Maki , Mark Owen Maxson
发明人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , Andrew Benson Maki , Mark Owen Maxson
IPC分类号： G06F13/40 , G06F12/00
CPC分类号： G06F13/4243
摘要： A memory chip having a data bus having a plurality of bits. The number of bits is apportioned between a read portion and a write portion. The write portion is dedicated to receiving data that is to be written into an array on the memory chip; the read portion is dedicated to driving data that has been read from the array on the memory chip. The apportionment is programmable. Apportionment can be specified by programming signal pins on the memory chip, connecting the signal pins to appropriate logical values. The apportionment can alternatively be specified by scanning apportionment information into the memory chip at bring up time. The apportionment and also alternatively be specified by receiving apportionment information in an address/command word.
摘要翻译：一种具有数据总线的存储器芯片，具有多个位。比特数在读取部分和写入部分之间分配。写入部分专用于接收要写入存储器芯片中的阵列的数据; 读取部分专用于驱动已经从存储器芯片上的阵列读取的数据。分配是可编程的。分配可以通过编程存储器芯片上的信号引脚指定，将信号引脚连接到适当的逻辑值。可以通过在启动时间内将分配信息扫描到存储器芯片来指定分配。分配也可以通过在地址/命令字中接收分配信息来指定。

59. 发明授权

US06754858B2 SDRAM address error detection method and apparatus 失效
标题翻译： SDRAM地址错误检测方法和装置
公开(公告)号：US06754858B2
公开(公告)日：2004-06-22
申请号：US09820436
申请日：2001-03-29
申请人： John Michael Borkenhagen , Brian T. Vanderpool
发明人： John Michael Borkenhagen , Brian T. Vanderpool
IPC分类号： G11C2900
CPC分类号： G11C11/408 , G11C7/24
摘要： Synchronous dynamic random access memory (SDRAM) method and apparatus are provided for implementing address error detection. Addressing errors are detected on the memory interface independent of data ECC, with reduced memory read access latency and improved processor performance. Addressing errors are detected while allowing differentiation between memory addressing failures that are required to stop the system and memory cell failures that allow continued operation. A predefined pattern is generated for a write burst to the SDRAM. The predefined pattern is dependent on a write address. A bit of the predefined pattern is sequentially stored into the SDRAM on each burst transfer of the write burst to the SDRAM. An expected pattern is generated from a read address for a read burst. The stored predefined pattern is retrieved during a read burst. The retrieved predefined pattern is compared to the generated expected pattern for identifying a type of an addressing error.
摘要翻译：提供同步动态随机存取存储器（SDRAM）方法和装置，用于实现地址错误检测。在存储器接口上检测到寻址错误，独立于数据ECC，具有减少的存储器读访问延迟和改进的处理器性能。检测到寻址错误，同时允许区分停止系统所需的存储器寻址故障和允许继续操作的存储器单元故障。为SDRAM的写突发生成预定义的模式。预定义模式取决于写入地址。在写入突发的每次突发传送到SDRAM时，预定义模式的一部分被顺序地存储到SDRAM中。从读取脉冲串的读取地址产生预期模式。在读突发期间检索存储的预定义模式。将检索到的预定义模式与生成的期望模式进行比较，以识别寻址错误的类型。

60. 发明授权

US06697935B1 Method and apparatus for selecting thread switch events in a multithreaded processor 失效
标题翻译：用于在多线程处理器中选择线程切换事件的方法和装置
公开(公告)号：US06697935B1
公开(公告)日：2004-02-24
申请号：US08958716
申请日：1997-10-23
申请人： John Michael Borkenhagen , Richard James Eickemeyer , William Thomas Flynn , Andrew Henry Wottreng
发明人： John Michael Borkenhagen , Richard James Eickemeyer , William Thomas Flynn , Andrew Henry Wottreng
IPC分类号： G06F1500
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.
摘要翻译：用于在数据处理系统中执行计算机处理操作的系统和方法包括多线程处理器和线程切换逻辑。多线程处理器能够在可独立执行的两条或更多条指令线之间进行切换。每个线程根据执行状态在线程状态寄存器中具有相应的状态。线程开关逻辑包含一个线程切换控制寄存器，用于存储发生线程切换的条件。线程开关逻辑具有超时寄存器，当多线程处理器中的活动线程的执行超过可编程时间段时，强制执行线程切换。线程开关逻辑还具有前进进程计数寄存器，以防止多线程处理器中的线程之间的重复线程切换。线程切换逻辑还响应于能够改变不同线程的优先级并从而取代线程切换事件的软件管理器。

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