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51. 发明授权

US07993968B2 Assembling substrates that can form 3-D structures 失效
标题翻译：组装可形成3-D结构的底物
公开(公告)号：US07993968B2
公开(公告)日：2011-08-09
申请号：US12825380
申请日：2010-06-29
申请人： Thaddeus John Gabara
发明人： Thaddeus John Gabara
IPC分类号： H01L21/00
CPC分类号： B01L3/502707 , B01L3/502715 , B01L2200/028 , B01L2200/10 , B01L2200/143 , B01L2300/0816 , B01L2300/0861 , B81C3/004 , B81C2203/051 , G01P15/125 , G01P15/18 , H01L23/06 , H01L24/48 , H01L24/73 , H01L24/95 , H01L25/18 , H01L25/50 , H01L2224/13021 , H01L2224/16235 , H01L2224/32145 , H01L2224/32225 , H01L2224/451 , H01L2224/48145 , H01L2224/48227 , H01L2224/73265 , H01L2224/83121 , H01L2224/95092 , H01L2224/95145 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/15311 , H01L2924/16195 , H01L2924/19041 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01Q9/0407 , H01Q9/14 , H01Q9/16 , H01S5/183 , H01S5/4025 , Y10T29/49126 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： A system is described that connects the surface of a first substrate to the edge of a second substrate. The surfaces of additional substrates can be placed on the remaining edges of the second substrate to form a 3-D structure. Rigid support substrates can be connected to the first substrate to provide support for the first and additional substrates. The second substrate can be used to carry heat, fluids, electrical power or signals between first and additional substrates besides providing a mechanical support.
摘要翻译：描述了将第一基板的表面连接到第二基板的边缘的系统。附加基板的表面可以放置在第二基板的剩余边缘上以形成3-D结构。刚性支撑基底可以连接到第一基底以为第一和另外的基底提供支撑。除了提供机械支撑之外，第二基板可用于承载第一和另外的基板之间的热，流体，电力或信号。

52. 发明授权

US07511588B2 Flux linked LC tank circuits forming distributed clock networks 有权
标题翻译：形成分布式时钟网络的磁通链接LC电路
公开(公告)号：US07511588B2
公开(公告)日：2009-03-31
申请号：US11185001
申请日：2005-07-19
申请人： Thaddeus John Gabara
发明人： Thaddeus John Gabara
IPC分类号： H03B5/12
CPC分类号： G06F1/10 , H01L2224/16145 , H03B5/1212 , H03B5/1228 , H03B5/1243 , H03B2200/0076
摘要： CMOS LC tank circuits and flux linkage between inductors can be used to distribute and propagate clock signals over the surface of a VLSI chip or processor. The tank circuit offers an adiabatic behavior that recycles the energy between the reactive elements and minimizes losses in a conventional sense. Flux linkage can be used to orchestrate a number of seemingly individual and distributed CMOS LC tank circuits to behave as one unit. In one example, the distribution of a 45° separated multi-phase balanced oscillations over the surface of die 1.6 cm×1.6 cm at 10 GHz is expected to dissipate under 10 W and offers a potential to significantly reduce the road map predictions of 100 W. Simulations of several CMOS tank circuits indicate that the power dissipation can be reduced an order of magnitude when compared to conventional techniques. A passive flux linkage, mechanical, and finite state machine technique of frequency adjustment of an oscillator are described.
摘要翻译： CMOS LC槽电路和电感之间的磁链可用于在VLSI芯片或处理器的表面上分布和传播时钟信号。油箱回路提供了一种绝热的行为，可回收无功元件之间的能量，并将传统意义上的损耗降至最低。磁通联动可以用于编排一些看似独立和分布的CMOS LC电路，以作为一个单元。在一个示例中，在10 GHz处的1.6 cm×1.6cm的模具表面上的45°分离多相平衡振荡的分布预计将在10 W以下消散，并提供显着降低100 W的路线图预测的潜力几个CMOS电容电路的仿真表明，与常规技术相比，功耗可以降低一个数量级。描述了振荡器频率调整的无源磁链，机械和有限状态机技术。

53. 发明授权

US07501903B2 Frequency adjustment techniques in coupled LC tank circuits 有权
标题翻译：耦合LC电路中的频率调节技术
公开(公告)号：US07501903B2
公开(公告)日：2009-03-10
申请号：US11677053
申请日：2007-02-21
申请人： Thaddeus John Gabara
发明人： Thaddeus John Gabara
IPC分类号： H03B5/12 , H03B5/18
CPC分类号： G06F1/10 , H03B5/1212 , H03B5/1228 , H03B5/1243 , H03B27/00 , H03B2200/0076
摘要： CMOS LC tank circuits and flux linkage between inductors can be used to distribute and propagate clock signals over the surface of a VLSI chip or μprocessor. The tank circuit offers an adiabatic behavior that recycles the energy between the reactive elements and minimizes losses in a conventional sense. Flux linkage can be used to orchestrate a number of seemingly individual and distributed CMOS LC tank circuits to behave as one unit. Several frequency-adjusting techniques are presented which can be used in an distributed clock network environment which includes an array of oscillators. A finite state machine technique of frequency adjustment of oscillators is described. In addition, two methods of increasing the physcial layout and decreasing the power dissipation of an oscillator are described.
摘要翻译： CMOS LC槽电路和电感之间的磁链可用于在VLSI芯片或处理器的表面上分布和传播时钟信号。油箱回路提供了一种绝热的行为，可回收无功元件之间的能量，并将传统意义上的损耗降至最低。磁通联动可以用于编排一些看似独立和分布的CMOS LC电路，以作为一个单元。提出了可以在包括振荡器阵列的分布式时钟网络环境中使用的几种频率调整技术。描述了振荡器频率调整的有限状态机技术。此外，还描述了增加振荡器的物理布局和降低功耗的两种方法。

54. 发明申请

US20080150668A1 Generating Variable Inductances by Altering the Physical Characteristics of Inductors Connected in Parallel 审中-公开
标题翻译：通过改变并联连接的电感器的物理特性来产生可变电感
公开(公告)号：US20080150668A1
公开(公告)日：2008-06-26
申请号：US11764805
申请日：2007-06-18
申请人： Thaddeus John Gabara
发明人： Thaddeus John Gabara
IPC分类号： H01F5/00 , H01F27/28
CPC分类号： G06F1/10 , H03B5/1212 , H03B5/1228 , H03B5/1243 , H03B27/00 , H03B2200/0076
摘要： CMOS LC tank circuits and flux linkage between inductors can be used to distribute and propagate clock signals over the surface of a VLSI chip or μprocessor. The tank circuit offers an adiabatic behavior that recycles the energy between the reactive elements and minimizes losses in a conventional sense. The LC tank circuit contains a plurality of inductors coupled together in parallel. The area encompassed within each of these inductors can be altered causing the inductors coupled in parallel to have a variable self-inductance.
摘要翻译： CMOS LC槽电路和电感之间的磁链可用于在VLSI芯片或处理器的表面上分布和传播时钟信号。油箱回路提供了一种绝热的行为，可回收无功元件之间的能量，并将传统意义上的损耗降至最低。 LC谐振电路包含并联耦合在一起的多个电感器。可以改变包含在每个这些电感器内的区域，使得并联耦合的电感器具有可变的自感。

55. 发明授权

US07024000B1 Adjustment of a hearing aid using a phone 失效
标题翻译：使用电话调整助听器
公开(公告)号：US07024000B1
公开(公告)日：2006-04-04
申请号：US09589391
申请日：2000-06-07
申请人： Thaddeus John Gabara , Scott Wayne McLellan , David L. Smith
发明人： Thaddeus John Gabara , Scott Wayne McLellan , David L. Smith
IPC分类号： H04B29/00 , A61B5/00 , H04M11/00
CPC分类号： A61B5/121 , A61B5/0022 , H04R25/70 , H04R2225/55
摘要： A system and method for using a telephone to reconfigure or readjust the performance characteristics of a hearing aid or to check whether a user has a hearing problem. The telephone is used to generate one or more frequency tests covering the audible spectrum using a DSP contained in the phone, an external computer and/or a hearing aid. The keypad of the phone or keyboard of an attached computer is used as a feedback mechanism. The generated frequencies can be used to test the hearing of a user and the quality (or fit) of a hearing aid while being worn by the user. A local memory may be used to store the results of the tests for future reference or for transmission over the network for analysis at a later time. Once the hearing response of a user wearing the hearing aid has been measured, an updated compensation configuration (audiogram) can be downloaded into the hearing aid via an infra-red link, via a physical connection or a direct audio transmission from the telephone to the DSP in the hearing aid.
摘要翻译：一种使用电话机重新配置或重新调整助听器的性能特征或检查用户是否具有听力问题的系统和方法。电话用于使用包含在电话中的DSP，外部计算机和/或助听器来产生覆盖可听频谱的一个或多个频率测试。连接的计算机的电话或键盘的键盘用作反馈机制。产生的频率可用于测试用户的听力和用户佩戴时助听器的质量（或适合）。可以使用本地存储器来存储测试的结果以供将来参考或通过网络传输以在稍后的时间进行分析。一旦已经测量了佩戴助听器的用户的听力响应，则可以经由红外线链接经由物理连接或从电话到直接音频传输的直接音频传输，将更新的补偿配置（听力图）下载到助听器中 DSP助听器。

56. 发明授权

US06950678B1 Control technique for a communication system 有权
标题翻译：一种通信系统的控制技术
公开(公告)号：US06950678B1
公开(公告)日：2005-09-27
申请号：US09576999
申请日：2000-05-24
申请人： Syed Aon Mujtaba , Thaddeus John Gabara
发明人： Syed Aon Mujtaba , Thaddeus John Gabara
IPC分类号： H01Q3/26 , H04B7/26 , H04W16/32 , H04W88/08 , H04Q7/20 , H01Q3/24 , H04B1/38
CPC分类号： H04W16/32
摘要： A control technique for a communication system in which a microcell base station is co-located with a macrocell base station. The microcell base station tracks hot spots as they move within the macrocell. The microcell base station may utilize a two-dimensional (2-D) antenna array, which is co-located with the macro cell antenna. The two-dimensional antenna is steerable in both the horizontal and vertical directions. The size of the microcell coverage area depends upon the distance from the cell site antenna as well as the dimensionality of the array, which determines the angular spread of the beam. Filter tap weights may be adjusted to point the beam to any desired location in the macrocell. The orthogonality between the macrocell and the microcell may be obtained either in the frequency domain or in the code domain, depending upon the system in which it is implemented.
摘要翻译：一种用于其中微小区基站与宏小区基站共同定位的通信系统的控制技术。微小区基站在宏小区内移动时跟踪热点。微小区基站可以利用与宏小区天线共同定位的二维（2-D）天线阵列。二维天线在水平和垂直两个方向都是可操纵的。微小区覆盖区域的大小取决于距离小区站点天线的距离以及阵列的维数，这决定了射束的角度扩展。可以调整滤波器抽头权重以将波束指向宏单元中的任何所需位置。宏单元和微小区之间的正交性可以在频域或代码域中获得，这取决于其实现的系统。

57. 发明授权

US06930516B2 Comparator circuits having non-complementary input structures 有权
标题翻译：具有非互补输入结构的比较器电路
公开(公告)号：US06930516B2
公开(公告)日：2005-08-16
申请号：US09870436
申请日：2001-05-30
申请人： Thaddeus John Gabara
发明人： Thaddeus John Gabara
IPC分类号： H03K5/08 , G06F7/02 , G11C7/06 , H03K5/24 , G01R19/00
CPC分类号： G11C7/062 , G06F7/026 , H03K5/2481
摘要： A non-complementary comparator includes an evaluation element such as a memory cell, a differential amplifier, or another type of circuit capable adapted to perform an evaluation function, and at least first and second input legs each coupled to a corresponding one of a first and second node of the evaluation element. The first and second input legs have non-complementary structures relative to one another, with each of the non-complementary structures having associated therewith a variable parameter, e.g., a variable resistance, variable current or variable voltage, having a value that is a function of a corresponding input signal. The evaluation element performs a comparison of at least first and second inputs applied to the respective first and second input legs. The input legs may each be implemented as a weighted array of transistors, with each of the transistors in the weighted array associated with a given leg corresponding to a particular bit or other portion of an input signal applied to that leg. The non-complementary comparator may be used as a multi-digit comparator to determine the relative weight of digital words, or to implement other comparator circuits such as, e.g., majority rule circuits, analog common mode comparators, greater than/less than circuits, array addition and comparison circuits, serial adder-binary search (SA-BS) circuits, analog adders, add-compare-select (ACS) circuits, coupled memory cell comparators, and comparators with mask functions.
摘要翻译：非互补比较器包括诸如存储器单元，差分放大器或能够执行评估功能的另一类型的电路的评估元件，以及至少第一和第二输入支路，每个耦合到第一和第二输入脚评估要素的第二个节点。第一和第二输入支路相对于彼此具有非互补结构，其中每个非互补结构具有与其相关联的可变参数，例如可变电阻，可变电流或可变电压，其具有作为功能的值相应的输入信号。评估元件执行至少应用于相应的第一和第二输入支路的第一和第二输入的比较。输入支路可以各自被实现为晶体管的加权阵列，其中加权阵列中的每个晶体管与给定支路相对应，该特定位对应于施加到该支路的输入信号的特定位或其他部分。非互补比较器可以用作多位比较器，以确定数字字的相对权重，或者实现大于/小于电路的其他比较器电路，例如多数规则电路，模拟共模比较器，阵列加法和比较电路，串行加法器二进制搜索（SA-BS）电路，模拟加法器，加法比较选择（ACS）电路，耦合存储器单元比较器和具有掩码功能的比较器。

58. 发明授权

US06849937B2 Variable rotational assignment of interconnect levels in integrated circuit fabrication 有权
标题翻译：集成电路制造中互连电平的可变旋转分配
公开(公告)号：US06849937B2
公开(公告)日：2005-02-01
申请号：US10377239
申请日：2003-02-28
申请人： Thaddeus John Gabara , Tarek Chaker Jomaa
发明人： Thaddeus John Gabara , Tarek Chaker Jomaa
IPC分类号： G03F1/08 , G06F17/50 , H01L21/027 , H01L21/3205 , H01L21/768 , H01L21/82 , H01L23/52 , H01L23/528 , H01L27/108 , G06K9/32
CPC分类号： H01L21/76838 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuit fabrication techniques are provided which allow non-horizontal/non-vertical wires to traverse the entire chip surface, rather than just the corners as in the conventional Manhattan geometry, while interconnecting circuit points. This is achieved by employing a variable rotational assignment methodology with respect to the interconnect layers or levels during the IC fabrication operation. These techniques thus eliminate the litho step problem, reduce interconnect distances and lessen the influence of capacitance interaction between interconnect wires.
摘要翻译：提供集成电路制造技术，其允许非水平/非垂直导线横穿整个芯片表面，而不仅仅是传统的曼哈顿几何形状的拐角，同时互连电路点。这通过在IC制造操作期间使用关于互连层或电平的可变旋转分配方法来实现。因此，这些技术消除了光刻步骤问题，减少了互连距离并减轻了互连线之间的电容相互作用的影响。

59. 发明授权

US06515533B1 Multi-input comparator 有权
标题翻译：多输入比较器
公开(公告)号：US06515533B1
公开(公告)日：2003-02-04
申请号：US09162852
申请日：1998-09-29
申请人： Thaddeus John Gabara , Syed Aon Mujtaba
发明人： Thaddeus John Gabara , Syed Aon Mujtaba
IPC分类号： H03K1762
CPC分类号： H03K5/24
摘要： A multi-input comparator in accordance with the invention determines a minimum or maximum signal value in a given set of signal values. An illustrative embodiment of the multi-input comparator includes N inputs and generates an output corresponding to the maximum or minimum value in a set of signal values applied to the N inputs. The comparator includes a first comparison circuit, such as a sense amplifier, having inputs for receiving a subset of the N signal values, such as a pair of the inputs. The comparator also includes a first multiplexer having a select signal input coupled to an output of the first comparison circuit, and inputs coupled to the subset of the N signal values. The comparator further includes N-2 additional comparison circuits and N-2 additional multiplexers, with the N-2 additional multiplexers coupled to corresponding ones of the N-2 additional comparison circuits. The comparison circuits and multiplexers are arranged to select a particular one of the N signal values, e.g., the maximum or the minimum value. The additional comparison circuits and multiplexers may be arranged in, for example, a linear architecture or a logarithmic architecture. The comparator may be used in conjunction with a position determination circuit which indicates the position of the maximum or minimum value in the set of signal values, or produces a desired ordering of the signal values.
摘要翻译：根据本发明的多输入比较器确定给定的一组信号值中的最小或最大信号值。多输入比较器的说明性实施例包括N个输入并且产生对应于施加到N个输入的一组信号值中的最大值或最小值的输出。比较器包括具有用于接收N个信号值的子集的输入的诸如读出放大器的第一比较电路，例如一对输入。比较器还包括具有耦合到第一比较电路的输出的选择信号输入以及耦合到N个信号值的子集的输入的第一多路复用器。比较器还包括N-2个附加比较电路和N-2个附加多路复用器，其中N-2个附加多路复用器耦合到N-2个附加比较电路中的相应的。比较电路和多路复用器被设置为选择N个信号值中的特定一个，例如最大值或最小值。附加的比较电路和多路复用器可以被布置在例如线性架构或对数架构中。比较器可以与指示信号值集合中的最大值或最小值的位置的位置确定电路一起使用，或产生信号值的期望顺序。

60. 发明授权

US06249192B1 Clock injection system 有权
标题翻译：时钟注入系统
公开(公告)号：US06249192B1
公开(公告)日：2001-06-19
申请号：US09311589
申请日：1999-05-14
申请人： Thaddeus John Gabara , Syed Aon Mujtaba
发明人： Thaddeus John Gabara , Syed Aon Mujtaba
IPC分类号： H03B512
CPC分类号： H03L7/0805 , H03B5/1212 , H03B5/1228 , H03B5/1271 , H03K3/354 , H03L7/06 , H03L7/24 , H04L7/027 , H04L7/033
摘要： A tuning signal is injected into an LC tank circuit oscillator, e.g., through an impedance (either reactive, inductive, capacitive and/or resistive) to tune the phase and/or frequency of the LC tank circuit oscillator. A negative resistance is included in parallel with the LC tank circuit oscillator to compensate for losses in the LC tank circuit, and a bias signal is provided to power the operation of the LC tank circuit. The tuning signal may be, e.g., an AC signal or a data signal. The tuning signal is injected into the LC tank circuit using capacitors, resistors, FET or bipolar transistors, and/or inductors. Multiple LC tank circuit oscillators may be used to provide stable multiplied or divided frequencies. In this case, the output of one LC tank circuit oscillator may be used to tune another LC tank circuit oscillator. In another embodiment, the nominal frequency of the LC tank circuit oscillator may be adjusted using a varactor or other voltage-controlled element in the LC tank circuit oscillator under the control of, e.g., the output of a separate PLL loop including another LC tank circuit oscillator. In one application, the injection tuned LC tank circuit forms a clock recovery cell using a clock signal embedded in a NRZ (Non Return to Zero) pseudo-random data stream. The slave oscillator in turn generates a recovered clock signal. Differential clock recovery can be performed with as little as four active devices.
摘要翻译：调谐信号例如通过阻抗（无功，电感，电容和/或电阻）被注入LC振荡电路振荡器，以调谐LC振荡电路振荡器的相位和/或频率。 LC电路振荡器并联包含负电阻，以补偿LC电路中的损耗，并提供偏置信号为LC电路的运行提供动力。调谐信号可以是例如AC信号或数据信号。使用电容器，电阻器，FET或双极晶体管和/或电感器将调谐信号注入LC谐振电路。多个LC振荡电路振荡器可用于提供稳定的倍频或分频。在这种情况下，一个LC振荡电路振荡器的输出可用于调谐另一个LC振荡电路振荡器。在另一个实施例中，LC振荡电路振荡器的标称频率可以在LC振荡电路振荡器中使用变容二极管或其他电压控制元件进行调节，例如在包括另一个LC振荡电路的单独的PLL回路的输出振荡器在一个应用中，注入调谐的LC槽电路使用嵌入在NRZ（非归零）伪随机数据流中的时钟信号形成时钟恢复单元。从振荡器又产生恢复的时钟信号。差分时钟恢复可以用少至四个有源器件来执行。

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