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51. 发明授权

US09362384B2 Double diffused metal oxide semiconductor device and manufacturing method thereof 有权
公开(公告)号：US09362384B2
公开(公告)日：2016-06-07
申请号：US14559542
申请日：2014-12-03
申请人： Tzu-Cheng Kao , Jian-Hsing Lee , Jin-Lian Su , Huan-Ping Chu , Hung-Der Su
发明人： Tzu-Cheng Kao , Jian-Hsing Lee , Jin-Lian Su , Huan-Ping Chu , Hung-Der Su
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78 , H01L29/10 , H01L29/06
CPC分类号： H01L29/66681 , H01L29/0696 , H01L29/1095 , H01L29/66689 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.

52. 发明授权

US06246075B1 Test structures for monitoring gate oxide defect densities and the plasma antenna effect 有权
标题翻译：用于监测栅极氧化物缺陷密度和等离子体天线效应的测试结构
公开(公告)号：US06246075B1
公开(公告)日：2001-06-12
申请号：US09507883
申请日：2000-02-22
申请人： Hung-Der Su , Jian-Hsing Lee , Di-Son Kuo
发明人： Hung-Der Su , Jian-Hsing Lee , Di-Son Kuo
IPC分类号： H01L2358
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： An ensemble of test structures comprising arrays of polysilicon plate MOS capacitors for the measurement of electrical quality of the MOSFET gate insulation is described. The test structures also measure plasma damage to these gate insulators incurred during metal etching and plasma ashing of photoresist. The structures are formed, either on test wafers or in designated areas of wafers containing integrated circuit chips. One of the test structures is designed primarily to minimize plasma damage so that oxide quality, and defect densities may be measured unhampered by interface traps created by plasma exposure. Other structures provide different antenna-to-oxide area ratios, useful for assessing plasma induced oxide damage and breakdown. The current-voltage characteristics of the MOS capacitors are measured by probing the structures on the wafer, thereby providing timely process monitoring capability.
摘要翻译：描述了包括用于测量MOSFET栅极绝缘的电气质量的多晶硅板MOS电容器阵列的测试结构的集合。测试结构还测量在金属蚀刻和光致抗蚀剂的等离子体灰化期间引起的这些栅绝缘体的等离子体损伤。在测试晶片上或在包含集成电路芯片的晶片的指定区域中形成结构。其中一个测试结构主要设计为最小化等离子体损伤，从而可以通过等离子体曝光产生的界面陷阱来测量氧化物质量和缺陷密度。其他结构提供不同的天线到氧化物面积比，可用于评估等离子体诱导的氧化物损伤和击穿。通过探测晶片上的结构来测量MOS电容器的电流 - 电压特性，从而提供及时的过程监控能力。

53. 发明授权

US06765772B2 Electrostatic discharge protection device 有权
标题翻译：静电放电保护装置
公开(公告)号：US06765772B2
公开(公告)日：2004-07-20
申请号：US09963559
申请日：2001-09-27
申请人： Jian-Hsing Lee , Hung-Der Su
发明人： Jian-Hsing Lee , Hung-Der Su
IPC分类号： H02H900
CPC分类号： H01L27/0251
摘要： The present invention determines the ESD event by detecting the voltage value of the power source. The numbers N of the diodes 441 have to follow the condition of: N×VT(0.7)>Vcc (core) Therefore, the diodes 441 will not influence normal operation outside of ESD events. When an ESD pulse is generated, the PN junction of the PMOS transistor is turned on, so the voltage value of Vcc is raised. At this time, the voltage value of Vcc (core) is “Vcc−0.7−N1×(0.7)”, N1 represents the numbers of diodes between Vcc (core) and Vcc, which follows the condition of “N1×(0.7)>Vcc—Vcc (core)” to ensure the diodes remain turned on in normal operation.
摘要翻译：本发明通过检测电源的电压值来确定ESD事件。二极管441的数量N必须遵循以下条件：因此，二极管441不会影响ESD事件之外的正常工作。当产生ESD脉冲时，PMOS晶体管的PN结导通，因此Vcc的电压值升高。此时，Vcc（磁芯）的电压值为“Vcc-0.7-N1x（0.7）”，N1表示Vcc（磁芯）与Vcc之间的二极管数，其为“N1x（0.7）> Vcc -Vcc（核心）“，以确保二极管在正常工作状态下保持接通。

54. 发明授权

US06414532B1 Gate ground circuit approach for I/O ESD protection 有权
标题翻译：栅极接地电路用于I / O ESD保护
公开(公告)号：US06414532B1
公开(公告)日：2002-07-02
申请号：US09963596
申请日：2001-09-27
申请人： Hung Der Su , Jian-Hsing Lee , Yi-Hsun Wu , Mau-Lin Wu
发明人： Hung Der Su , Jian-Hsing Lee , Yi-Hsun Wu , Mau-Lin Wu
IPC分类号： H03K508
CPC分类号： H01L27/0266
摘要： An I/O ESD protection circuit is provided utilizing a driver circuit, an ESD protection circuit, a Vcc/Vss protection circuit, and a clamping circuit. The driver circuit and the ESD protection circuit each comprise a NMOS cascode circuit. NMOS transistors and biasing resistive means comprise the Vcc/Vss protection circuit. The clamping circuit is a diode coupled between the I/O pad of the protection circuit and the gate of that NMOS transistor. In an ESD event the diode turns on the NMOS transistor of the Vcc/Vss protection circuit , thus clamping off the first transistor of both NMOS cascode circuits. The clamping inhibits the gate of those first two transistors to be coupled up by an ESD voltage and creates a parasitic bipolar transistor in each cascode circuit. The parasitic bipolar transistors provide a uniform current flow in the buried area of the P-well of both NMOS cascode circuits.
摘要翻译：使用驱动电路，ESD保护电路，Vcc / Vss保护电路和钳位电路来提供I / O ESD保护电路。驱动电路和ESD保护电路各自包括NMOS共源共栅电路。 NMOS晶体管和偏置电阻装置包括Vcc / Vss保护电路。钳位电路是耦合在保护电路的I / O焊盘和该NMOS晶体管的栅极之间的二极管。在ESD事件中，二极管导通Vcc / Vss保护电路的NMOS晶体管，因此钳位了两个NMOS共源共栅电路的第一个晶体管。钳位禁止这些前两个晶体管的栅极通过ESD电压耦合，并在每个共源共栅电路中产生寄生双极晶体管。寄生双极晶体管在两个NMOS共源共栅电路的P阱的掩埋区域中提供均匀的电流。

55. 发明申请

US20150079755A1 DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：双重扩散金属氧化物半导体器件及其制造方法
公开(公告)号：US20150079755A1
公开(公告)日：2015-03-19
申请号：US14559542
申请日：2014-12-03
申请人： Tzu-Cheng Kao , Jian-Hsing Lee , Jin-Lian Su , Huan-Ping Chu , Hung-Der Su
发明人： Tzu-Cheng Kao , Jian-Hsing Lee , Jin-Lian Su , Huan-Ping Chu , Hung-Der Su
IPC分类号： H01L29/66
CPC分类号： H01L29/66681 , H01L29/0696 , H01L29/1095 , H01L29/66689 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.
摘要翻译：本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS器件包括：第一导电类型衬底，第二导电型高压阱，栅极，第一导电类型体区域，第二导电类型源极，第二导电类型漏极，第一导电型体电极和第一导电型浮动区域。浮动区域形成在电气浮动并且与源极和栅极电隔离的体区中，使得减轻静电放电（ESD）效应。

56. 发明授权

US08928078B2 Double diffused metal oxide semiconductor device and manufacturing method thereof 有权
标题翻译：双扩散金属氧化物半导体器件及其制造方法
公开(公告)号：US08928078B2
公开(公告)日：2015-01-06
申请号：US13726579
申请日：2012-12-25
申请人： Tzu-Cheng Kao , Jian-Hsing Lee , Jin-Lian Su , Huan-Ping Chu , Hung-Der Su
发明人： Tzu-Cheng Kao , Jian-Hsing Lee , Jin-Lian Su , Huan-Ping Chu , Hung-Der Su
IPC分类号： H01L29/76 , H01L29/94 , H01L29/78 , H01L29/66
CPC分类号： H01L29/66681 , H01L29/0696 , H01L29/1095 , H01L29/66689 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.
摘要翻译：本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS器件包括：第一导电类型衬底，第二导电型高压阱，栅极，第一导电类型体区域，第二导电类型源极，第二导电类型漏极，第一导电型体电极和第一导电型浮动区域。浮动区域形成在电气浮动并且与源极和栅极电隔离的体区中，使得减轻静电放电（ESD）效应。

57. 发明申请

US20140175545A1 DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：双重扩散金属氧化物半导体器件及其制造方法
公开(公告)号：US20140175545A1
公开(公告)日：2014-06-26
申请号：US13726579
申请日：2012-12-25
申请人： Tzu-Cheng Kao , Jian-Hsing Lee , Jin-Lian Su , Huan-Ping Chu , Hung-Der Su
发明人： Tzu-Cheng Kao , Jian-Hsing Lee , Jin-Lian Su , Huan-Ping Chu , Hung-Der Su
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/66681 , H01L29/0696 , H01L29/1095 , H01L29/66689 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.
摘要翻译：本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS器件包括：第一导电类型衬底，第二导电型高压阱，栅极，第一导电类型体区域，第二导电类型源极，第二导电类型漏极，第一导电型体电极和第一导电型浮动区域。浮动区域形成在电气浮动并且与源极和栅极电隔离的体区中，使得减轻静电放电（ESD）效应。

58. 发明授权

US06444511B1 CMOS output circuit with enhanced ESD protection using drain side implantation 有权
标题翻译： CMOS输出电路采用漏极侧注入增强ESD保护
公开(公告)号：US06444511B1
公开(公告)日：2002-09-03
申请号：US09867562
申请日：2001-05-31
申请人： Yi-Hsu Wu , Hung-Der Su , Jian-Hsing Lee , Boon-Khim Liew
发明人： Yi-Hsu Wu , Hung-Der Su , Jian-Hsing Lee , Boon-Khim Liew
IPC分类号： H01L218238
CPC分类号： H01L27/092 , H01L21/823814 , H01L27/0266
摘要： A new cascaded NMOS transistor output circuit with enhanced ESD protection is achieved. A driver PMOS transistor has the source connected to a voltage supply, the gate connected to the input signal, and the drain connected to the output pad. A dummy PMOS transistor has the source and the gate connected to the voltage supply, and the drain connected to the output pad. A driver NMOS cascaded stack comprises first and second NMOS transistors. The first NMOS transistor has the source connected to ground and the gate connected to the input signal. The second NMOS transistor has the gate connected to the voltage supply, the source connected to the first NMOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source. A dummy NMOS cascaded stack comprises third and fourth NMOS transistors. The third NMOS transistor has the gate and the source connected to ground. The fourth NMOS transistor has the gate connected to the voltage supply, the source connected to the third MOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source.
摘要翻译：实现了具有增强ESD保护的新型级联NMOS晶体管输出电路。驱动器PMOS晶体管的源极连接到电源，栅极连接到输入信号，漏极连接到输出焊盘。虚设PMOS晶体管的源极和栅极连接到电源，漏极连接到输出焊盘。驱动器NMOS级联堆叠包括第一和第二NMOS晶体管。第一个NMOS晶体管的源极连接到地，栅极连接到输入信号。第二个NMOS晶体管的栅极连接到电源，源极连接到第一个NMOS晶体管漏极，漏极连接到输出焊盘。 p-注入区域位于漏极的n +区域的下面，但不在源极的n +区域的下面。虚设NMOS级联堆叠包括第三和第四NMOS晶体管。第三个NMOS晶体管的栅极和源极接地。第四个NMOS晶体管的栅极连接到电源，源极连接到第三个MOS晶体管漏极，漏极连接到输出焊盘。 p-注入区域位于漏极的n +区域的下面，但不在源极的n +区域的下面。

59. 发明授权

US6028324A Test structures for monitoring gate oxide defect densities and the plasma antenna effect 失效
标题翻译：用于监测栅极氧化物缺陷密度和等离子体天线效应的测试结构
公开(公告)号：US6028324A
公开(公告)日：2000-02-22
申请号：US813758
申请日：1997-03-07
申请人： Hung-Der Su , Jian-Hsing Lee , Di-Son Kuo
发明人： Hung-Der Su , Jian-Hsing Lee , Di-Son Kuo
IPC分类号： H01L23/544 , H01L23/58 , H01L27/108
CPC分类号： H01L22/34 , H01L2924/0002
摘要： An ensemble of test structures comprising arrays of polysilicon plate MOS capacitors for the measurement of electrical quality of the MOSFET gate insulation is described. The test structures also measure plasma damage to these gate insulators incurred during metal etching and plasma ashing of photoresist. The structures are formed, either on test wafers or in designated areas of wafers containing integrated circuit chips. One of the test structures is designed primarily to minimize plasma damage so that oxide quality, and defect densities may be measured unhampered by interface traps created by plasma exposure. Other structures provide different antenna-to-oxide area ratios, useful for assessing plasma induced oxide damage and breakdown. The current-voltage characteristics of the MOS capacitors are measured by probing the structures on the wafer, thereby providing timely process monitoring capability.
摘要翻译：描述了包括用于测量MOSFET栅极绝缘的电气质量的多晶硅板MOS电容器阵列的测试结构的集合。测试结构还测量在金属蚀刻和光致抗蚀剂的等离子体灰化期间引起的这些栅绝缘体的等离子体损伤。在测试晶片上或在包含集成电路芯片的晶片的指定区域中形成结构。其中一个测试结构主要设计为最小化等离子体损伤，从而可以通过等离子体暴露产生的界面陷阱来测量氧化物质量和缺陷密度。其他结构提供不同的天线到氧化物面积比，可用于评估等离子体诱导的氧化物损伤和击穿。通过探测晶片上的结构来测量MOS电容器的电流 - 电压特性，从而提供及时的过程监控能力。

60. 发明授权

US08378422B2 Electrostatic discharge protection device comprising a plurality of highly doped areas within a well 有权
标题翻译：静电放电保护装置，其在井内包括多个高掺杂区域
公开(公告)号：US08378422B2
公开(公告)日：2013-02-19
申请号：US12609803
申请日：2009-10-30
申请人： Ming-Song Sheu , Jian-Hsing Lee , Yao-Wu Feng
发明人： Ming-Song Sheu , Jian-Hsing Lee , Yao-Wu Feng
IPC分类号： H01L23/62 , H01L29/72 , H01L29/74 , H01L31/111
CPC分类号： H01L29/66681 , H01L21/22 , H01L21/265 , H01L27/0259 , H01L29/0692 , H01L29/0839 , H01L29/0847 , H01L29/417 , H01L29/41758 , H01L29/66393 , H01L29/66659 , H01L29/7436 , H01L29/7835
摘要： Embodiments of the invention relate to an electrostatic discharge (ESD) device and method for forming an ESD device. An embodiment is an ESD protection device comprising a p well disposed in a substrate, an n well disposed in the substrate, a high voltage n well (HVNW) disposed between the p well and the n well in the substrate, a source n+ region disposed in the p well, and a plurality of drain n+ regions disposed in the n well.
摘要翻译：本发明的实施例涉及用于形成ESD装置的静电放电（ESD）装置和方法。一个实施例是ESD保护装置，其包括：良好地布置在衬底中，n阱设置在衬底中;高压n阱（HVNW），其设置在衬底中的p阱和n阱之间;源极n +区域设置在 p阱以及设置在n阱中的多个漏极n +区域。

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