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1. 发明申请

US20090122890A1 OFDM DCM DEMODULATION METHOD 审中-公开
标题翻译： OFDM DCM解调方法
公开(公告)号：US20090122890A1
公开(公告)日：2009-05-14
申请号：US11937007
申请日：2007-11-08
申请人： Mau-Lin Wu
发明人： Mau-Lin Wu
IPC分类号： H04L23/02
CPC分类号： H04L27/2649 , H04L27/0008 , H04L27/0012 , H04W52/16
摘要： An OFDM DCM demodulation method is provided. The OFDM DCM demodulation method mainly includes the following steps. First, calculate a log likelihood of a first demodulation mode. Then calculate a log likelihood of a second demodulation mode. Finally, calculate a demodulation output according to the log likelihoods of the first demodulation mode and the second demodulation mode. The demodulation output may serve as an output of a demodulator of a receiving end of a DCM communication system.
摘要翻译：提供OFDM DCM解调方法。 OFDM DCM解调方法主要包括以下步骤：首先，计算第一解调模式的对数似然。然后计算第二解调模式的对数似然。最后，根据第一解调模式和第二解调模式的对数似然度来计算解调输出。解调输出可以用作DCM通信系统的接收端的解调器的输出。

2. 发明申请

US20090285315A1 APPARATUS AND METHOD FOR ADAPTIVE CHANNEL ESTIMATION AND COHERENT BANDWIDTH ESTIMATION APPARATUS THEREOF 审中-公开
标题翻译：自适应信道估计的装置和方法及其相关带宽估计装置
公开(公告)号：US20090285315A1
公开(公告)日：2009-11-19
申请号：US12121334
申请日：2008-05-15
申请人： Mau-Lin Wu
发明人： Mau-Lin Wu
IPC分类号： H04L27/28
CPC分类号： H04L25/022 , H04L27/2647
摘要： An apparatus and a method for adaptive channel estimation and a coherent bandwidth estimation apparatus are provided. The adaptive channel estimation apparatus includes a first channel estimator, a coherent bandwidth estimator and a second channel estimator. The first channel estimator uses a predetermined approach to calculate a first channel response of each tone of an orthogonal frequency-division multiplexing (OFDM) signal. The coherent bandwidth estimator is coupled to the first channel estimator for calculating a coherent bandwidth according to the first channel responses. The second channel estimator is coupled to the first channel estimator and the coherent bandwidth estimator. For each of the tones, the second channel estimator calculates a weighted average according to the coherent bandwidth and the first channel responses of several adjacent tones including the aforementioned tone. The second channel estimator outputs the weighted average as the second channel response of the aforementioned tone.
摘要翻译：提供了一种用于自适应信道估计的装置和方法以及相干带宽估计装置。自适应信道估计装置包括第一信道估计器，相干带宽估计器和第二信道估计器。第一信道估计器使用预定的方法来计算正交频分复用（OFDM）信号的每个音调的第一信道响应。相干带宽估计器耦合到第一信道估计器，用于根据第一信道响应来计算相干带宽。第二信道估计器耦合到第一信道估计器和相干带宽估计器。对于每个音调，第二信道估计器根据相干带宽和包括前述音调的几个相邻音调的第一信道响应来计算加权平均。第二信道估计器输出加权平均值作为上述音调的第二信道响应。

3. 发明授权

US07424664B2 Duplicate detection circuit for receiver 有权
标题翻译：接收机重复检测电路
公开(公告)号：US07424664B2
公开(公告)日：2008-09-09
申请号：US11163398
申请日：2005-10-17
申请人： Mau-Lin Wu
发明人： Mau-Lin Wu
IPC分类号： H03M13/00
CPC分类号： H04L1/0045 , H03M13/09 , H04L1/0052 , H04L1/0061 , H04L1/0072 , H04L1/1829
摘要： A duplicate detection circuit for a receiver includes a CRC generator for generating a CRC value of frame header information, and a control circuit coupled to the CRC generator. The control circuit has a first output, a second output, and a control input. When the control input is not set, the control circuit outputs the CRC value at the first output. When the control input is set, the control circuit outputs the CRC value at the second output. A buffer has an input coupled to the first output of the control circuit. A compare circuit has an input coupled to an output of the buffer and another input coupled to the second output of the control circuit. The compare circuit compares a CRC value at the second output of the control circuit with a CRC value stored in the buffer, and outputs a duplicate indication when detecting a match.
摘要翻译：用于接收机的重复检测电路包括用于产生帧头信息的CRC值的CRC发生器和耦合到CRC发生器的控制电路。控制电路具有第一输出，第二输出和控制输入。当控制输入未设定时，控制电路在第一个输出端输出CRC值。当控制输入被设置时，控制电路在第二个输出端输出CRC值。缓冲器具有耦合到控制电路的第一输出的输入。比较电路具有耦合到缓冲器的输出和耦合到控制电路的第二输出的另一个输入的输入。比较电路将控制电路的第二输出端的CRC值与存储在缓冲器中的CRC值进行比较，并在检测到匹配时输出重复指示。

4. 发明授权

US07283926B2 Counter circuits and distance estimation methods 失效
标题翻译：计数器电路和距离估计方法
公开(公告)号：US07283926B2
公开(公告)日：2007-10-16
申请号：US11257591
申请日：2005-10-24
申请人： Mau-Lin Wu
发明人： Mau-Lin Wu
IPC分类号： G01C22/00
CPC分类号： G01S13/74 , G01S13/0209 , H03K23/54
摘要： Counting circuits applied to distance estimation for ultra wideband (UWB) application, in which a first counting unit generates a sequence of pseudo-random number series not including zero, a first recoding unit records a first series and a second series from the sequence according to a first signal and a second signal, and a transfer unit generates a binary counting value according to the first series and second series from the recording unit.
摘要翻译：应用于超宽带（UWB）应用的距离估计的计数电路，其中第一计数单元产生不包括零的伪随机数序列，第一记录单元根据序列记录第一序列和第二序列第一信号和第二信号，并且传送单元根据来自记录单元的第一串联和第二串行生成二进制计数值。

5. 发明申请

US20070093984A1 Counter circuits and distance estimation methods 失效
公开(公告)号：US20070093984A1
公开(公告)日：2007-04-26
申请号：US11257591
申请日：2005-10-24
申请人： Mau-Lin Wu
发明人： Mau-Lin Wu
IPC分类号： G06F15/00
CPC分类号： G01S13/74 , G01S13/0209 , H03K23/54
摘要： Counting circuits applied to distance estimation for ultra wideband (UWB) application, in which a first counting unit generates a sequence of pseudo-random number series not including zero, a first recoding unit records a first series and a second series from the sequence according to a first signal and a second signal, and a transfer unit generates a binary counting value according to the first series and second series from the recording unit.

6. 发明授权

US06750517B1 Device layout to improve ESD robustness in deep submicron CMOS technology 有权
标题翻译：器件布局，以提高深亚微米CMOS技术的ESD鲁棒性
公开(公告)号：US06750517B1
公开(公告)日：2004-06-15
申请号：US09706206
申请日：2000-11-06
申请人： Ming-Dou Ker , Mau-Lin Wu
发明人： Ming-Dou Ker , Mau-Lin Wu
IPC分类号： H01L2976
CPC分类号： H01L27/0277 , H01L23/585 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A layout form ESD-protection MOS transistors include gate electrodes of the ESD-protection MOS transistors being formed with wider ends at the periphery of the active region, whereby the transistors have improved turn-on uniformity. The ESD protection transistors are NMOS and PMOS. The source contacts and drain contacts for transistors are located inboard of the periphery of the active region leaving space for the wider ends of the gate electrodes. The wider ends of the gate electrodes straddle the peripheral boundaries of the active region. A modified layout style is provided for stacked NMOS and PMOS devices in the high-voltage-tolerant I/O circuits with the wider ends being provided on only the inner transistors.
摘要翻译： ESD保护MOS晶体管的布局形式包括在有源区的外围形成有较宽端的ESD保护MOS晶体管的栅电极，由此晶体管具有改善的导通均匀性。 ESD保护晶体管是NMOS和PMOS。用于晶体管的源极接触和漏极接触位于有源区的周边的内侧，留下用于栅电极较宽端的空间。栅电极的较宽端跨越有源区的周边边界。在高耐压I / O电路中为层叠的NMOS和PMOS器件提供了改进的布局样式，其较宽端仅提供在内部晶体管上。

7. 发明申请

US20060115024A1 Fast Walsh transform (FWT) demodulator and method thereof 失效
标题翻译：快速沃尔什变换（FWT）解调器及其方法
公开(公告)号：US20060115024A1
公开(公告)日：2006-06-01
申请号：US10999753
申请日：2004-11-29
申请人： Mau-Lin Wu
发明人： Mau-Lin Wu
IPC分类号： H04L27/06
CPC分类号： H04L23/02
摘要： A fast Walsh transform (FWT) demodulator and a method are provided. The FWT demodulator includes a FWT correlator for receiving and transforming a first information based on a FWT method to output third information; power approximation devices (PAD) for receiving and calculating one of the third information to output an approximating power value respectively. Wherein, the approximating power values are divided into subgroups. A first unit of comparators selects subgroup-max-values from each subgroup. A plurality of power calculation devices (PCD) are for receiving and calculating one of the subgroup-max-value to output a precise power value respectively. A second unit of comparators is for selecting max power value from each precise power value to output a second information. By applying “PAD” to replace “PCD” into “pre-selection” subgroups with “max-and-zero” property, the invention can reduce the implementation cost without performance degradation.
摘要翻译：提供了快速沃尔什变换（FWT）解调器和方法。 FWT解调器包括用于基于FWT方法接收和变换第一信息以输出第三信息的FWT相关器; 功率近似装置（PAD），用于接收和计算第三信息之一，以分别输出近似功率值。其中近似功率值被划分为子组。比较器的第一个单位从每个子组中选择子组 - 最大值。多个功率计算装置（PCD）用于接收和计算子组最大值之一，以分别输出精确的功率值。比较器的第二单元用于从每个精确功率值选择最大功率值以输出第二信息。通过应用“PAD”将“PCD”替换为具有“最大和零”属性的“预选”子组，本发明可以在不降低性能的情况下降低实现成本。

8. 发明授权

US06414532B1 Gate ground circuit approach for I/O ESD protection 有权
标题翻译：栅极接地电路用于I / O ESD保护
公开(公告)号：US06414532B1
公开(公告)日：2002-07-02
申请号：US09963596
申请日：2001-09-27
申请人： Hung Der Su , Jian-Hsing Lee , Yi-Hsun Wu , Mau-Lin Wu
发明人： Hung Der Su , Jian-Hsing Lee , Yi-Hsun Wu , Mau-Lin Wu
IPC分类号： H03K508
CPC分类号： H01L27/0266
摘要： An I/O ESD protection circuit is provided utilizing a driver circuit, an ESD protection circuit, a Vcc/Vss protection circuit, and a clamping circuit. The driver circuit and the ESD protection circuit each comprise a NMOS cascode circuit. NMOS transistors and biasing resistive means comprise the Vcc/Vss protection circuit. The clamping circuit is a diode coupled between the I/O pad of the protection circuit and the gate of that NMOS transistor. In an ESD event the diode turns on the NMOS transistor of the Vcc/Vss protection circuit , thus clamping off the first transistor of both NMOS cascode circuits. The clamping inhibits the gate of those first two transistors to be coupled up by an ESD voltage and creates a parasitic bipolar transistor in each cascode circuit. The parasitic bipolar transistors provide a uniform current flow in the buried area of the P-well of both NMOS cascode circuits.
摘要翻译：使用驱动电路，ESD保护电路，Vcc / Vss保护电路和钳位电路来提供I / O ESD保护电路。驱动电路和ESD保护电路各自包括NMOS共源共栅电路。 NMOS晶体管和偏置电阻装置包括Vcc / Vss保护电路。钳位电路是耦合在保护电路的I / O焊盘和该NMOS晶体管的栅极之间的二极管。在ESD事件中，二极管导通Vcc / Vss保护电路的NMOS晶体管，因此钳位了两个NMOS共源共栅电路的第一个晶体管。钳位禁止这些前两个晶体管的栅极通过ESD电压耦合，并在每个共源共栅电路中产生寄生双极晶体管。寄生双极晶体管在两个NMOS共源共栅电路的P阱的掩埋区域中提供均匀的电流。

9. 发明申请

US20090003385A1 TX EVM IMPROVEMENT OF OFDM COMMUNICATION SYSTEM 审中-公开
标题翻译： OFDM通信系统的TX EVM改进
公开(公告)号：US20090003385A1
公开(公告)日：2009-01-01
申请号：US11769996
申请日：2007-06-28
申请人： Mau-Lin Wu
发明人： Mau-Lin Wu
IPC分类号： H04B3/10
CPC分类号： H04L5/0007 , H04L25/022 , H04L25/0224
摘要： In a wireless communication method and system, a data/pilot constellation is modulated and generated based on input information bits. Channel estimation (CE) sequence in frequency-domain is off-line generated. The frequency-domain channel estimation sequence is transformed into a time-domain channel estimation sequence by ideal IFFT to avoid IFFT (Inverse Fast Fourier Transform) impact to EVM (Error Vector Magnitude) performance. Off-line resealing the time-domain CE sequence, multiplied by a rescaling coefficient, in time-domain improves EVM performance. Further, the time-domain channel estimation sequence is off-line quantized.
摘要翻译：在无线通信方法和系统中，基于输入信息比特来调制和生成数据/导频星座。频域中的信道估计（CE）序列是离线生成的。通过理想的IFFT将频域信道估计序列变换成时域信道估计序列，以避免对EVM（误差矢量幅度）性能的IFFT（快速傅立叶逆变换）影响。离线重新密封时域CE序列乘以重新缩放系数，在时域上提高EVM性能。此外，时域信道估计序列被离线量化。

10. 发明授权

US07369630B2 Fast Walsh transform (FWT) demodulator and method thereof 失效
标题翻译：快速沃尔什变换（FWT）解调器及其方法
公开(公告)号：US07369630B2
公开(公告)日：2008-05-06
申请号：US10999753
申请日：2004-11-29
申请人： Mau-Lin Wu
发明人： Mau-Lin Wu
IPC分类号： H03D1/00 , H04L27/06 , H04L27/00
CPC分类号： H04L23/02
摘要： A fast Walsh transform (FWT) demodulator and a method are provided. The FWT demodulator includes a FWT correlator for receiving and transforming a first information based on a FWT method to output third information; power approximation devices (PAD) for receiving and calculating one of the third information to output an approximating power value respectively. Wherein, the approximating power values are divided into subgroups. A first unit of comparators selects subgroup-max-values from each subgroup. A plurality of power calculation devices (PCD) are for receiving and calculating one of the subgroup-max-value to output a precise power value respectively. A second unit of comparators is for selecting max power value from each precise power value to output a second information. By applying “PAD” to replace “PCD” into “pre-selection” subgroups with “max-and-zero” property, the invention can reduce the implementation cost without performance degradation.
摘要翻译：提供了快速沃尔什变换（FWT）解调器和方法。 FWT解调器包括用于基于FWT方法接收和变换第一信息以输出第三信息的FWT相关器; 功率近似装置（PAD），用于接收和计算第三信息之一，以分别输出近似功率值。其中近似功率值被划分为子组。比较器的第一个单位从每个子组中选择子组 - 最大值。多个功率计算装置（PCD）用于接收和计算子组最大值之一，以分别输出精确的功率值。比较器的第二单元用于从每个精确功率值选择最大功率值以输出第二信息。通过应用“PAD”将“PCD”替换为具有“最大和零”属性的“预选”子组，本发明可以在不降低性能的情况下降低实现成本。

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